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Messages from 55525

Article: 55525
Subject: Re: Information about XC9536 ?
From: Spam Hater <spam_hater_7@email.com>
Date: Sun, 11 May 2003 23:03:57 GMT
Links: << >>  << T >>  << A >>

1) Go to the Xilinx web site and down-load the data sheets.

2) Go to the Xilinx web site and download the (free) software.

3) Go to the Xilinx web site and download the schematic.

Notice the common thread?  :)

Notes:

Yes, the 9536 has 3-state buffers.  You program it in VHDL or Verilog.
There are tutorials on the web, including (gasp! :) the Xilinx web
site.  And there's a company in Canada selling JTAG adapters on eBay
for cheap.  $15 IIRC.

Comment:

The one 'person' in the world that cares the most about you being able
to use Xilinx parts is ...  Xilinx!  Seriously, their web site has
everything that you need.

HTH,
SH


On Sun, 11 May 2003 22:16:20 +0200, "Gorgo" <chudzielec21@wp.pl>
wrote:

>Hey
>
>I'm new on this group and especialy in using CPLD products.
>What I want to do is to create buffer betwen ISA bus and my devices and I
>was wondering if it is possible by using XC9536 ? Does anybody know if this
>chip chas 3-state gates ?
>
>Secound my question is :
>
>Could anybody tell me how to start programing this chips. What kind of soft
>and spec I need to create some simple programs for this chips and finally
>how to upload this programs to the chip ?
>
>thank for any advices !
>
>Gorgo
>


Article: 55526
Subject: Re: help on FPGA-programming tutorial for students
From: "Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com>
Date: Mon, 12 May 2003 11:07:35 +1200
Links: << >>  << T >>  << A >>

"Philip Freidin" <philip@fliptronics.com> wrote in message
news:irkqbv4ng4gt2ugqqj92irn8hjrlss0rj4@4ax.com...
>
> Wow, ...  That is so "way cool"!!! Great class.

Yeah, right up to the part where you use a button and a switch to input a
196 bit bitstream.

Ralph



Article: 55527
Subject: Re: help on FPGA-programming tutorial for students
From: Eric Crabill <eric.crabill@xilinx.com>
Date: Sun, 11 May 2003 17:15:15 -0700
Links: << >>  << T >>  << A >>

Hi,

That is when the more intelligent students figure out
that they can build a small ROM using distributed RAM
instances, and make a serial PROM to include in the
top level design...  I'm going to include that in the
revised project for next semester.  You're right, 196
button presses is hard on the finger!

Eric

Ralph Mason wrote:
> 
> "Philip Freidin" <philip@fliptronics.com> wrote in message
> news:irkqbv4ng4gt2ugqqj92irn8hjrlss0rj4@4ax.com...
> >
> > Wow, ...  That is so "way cool"!!! Great class.
> 
> Yeah, right up to the part where you use a button and a switch to input a
> 196 bit bitstream.
> 
> Ralph

Article: 55528
Subject: QuartusII issue
From: "pc" <acosmos@freemail.gr>
Date: Mon, 12 May 2003 02:45:07 +0200
Links: << >>  << T >>  << A >>
I have downloaded the quartusII v2.2 web edition from altera BUT i cant use
it with the license i 've been send from them.
Has anyone the same problem? what is the solution? Thanks.



Article: 55529
Subject: Re: help on FPGA-programming tutorial for students
From: hmurray@suespammers.org (Hal Murray)
Date: Mon, 12 May 2003 01:34:50 -0000
Links: << >>  << T >>  << A >>
>That is when the more intelligent students figure out
>that they can build a small ROM using distributed RAM
>instances, and make a serial PROM to include in the
>top level design...  I'm going to include that in the
>revised project for next semester.  You're right, 196
>button presses is hard on the finger!

How about removing the debouncing circuit from the switch? :)

I assume they have to poke different switches for 0 and 1,
or flip another switch and then poke the clock button.

What are the chances of getting that right?

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 55530
Subject: Re: Altera Flex EPF81188A
From: "lc" <cupido@kkk.mail.ua.pt>
Date: Mon, 12 May 2003 03:55:32 +0100
Links: << >>  << T >>  << A >>
Got it...
The BASELINE versions don't have all devices.
On 10.0 full version all are there,

Thanks to all that replied.

Luis Cupido.


"Michael S" <already5chosen@yahoo.com> wrote in message
news:f881b862.0305110648.32a77322@posting.google.com...
> "lc" <cupido@kkk.mail.ua.pt> wrote in message
news:<1052621182.389816@newsfront2>...
> > Hi,
> >
> > What is the software that actually supports this
> > device? MaxPlus does not.
> > Quartus II also doesn't know this device.
> >
> > Any help is welcome.
> >
> > Luis Cupido.
> > (email, remove the kkk)
>
> Max+plus II 10.1 supports EPF81188AQC208, EPF81188AQC248 and
> EPF81188ARC240.
>
> However, I had the impression that the whole FLEX8000 family is
> obsolete for 6 or 7 years now. FLEX6000 devices are better for just
> about everything and they are near obsolete themselves. Did I miss
> something ?



Article: 55531
Subject: Re: Info about development kit
From: "Steve Casselman" <sc_nospam@vcc.com>
Date: Mon, 12 May 2003 04:20:40 GMT
Links: << >>  << T >>  << A >>
I just took a one day class using the Insight-Electronics Virtex2Pro board.

http://www.insight-electronics.com/cgi-bin/bvutf8/memec/scripts/local/mc_loc_b.jsp?Div=INSIGHT&Reg=AMERICAS&Country=UNITED_STATES&Lang=EN&isDetailPage=true&EDOID=200910&Manu=MD_XILINX

It is a long link but check it out. I was impressed by how easy it was to
program the V2Pro with the embedded development kit (EDK). You can take a
design and hook it into the PPC in no time. We were able to put together a
system hook it into the PC via com1 define com1 as the stdio and then
connect with the Microsoft HyperTerminal. Simple as you want but enough
potential to fuel any PhD project.


Steve

"Giando" <GOTEB@katamail.com> wrote in message
news:1402ce4.0305090536.2dd72fa@posting.google.com...
> Hi I'm a PhD student and have to buy a fpga development kit(board,
> chip, and software) that will be used by students of Electonic
> Engineer. I need a little suggest about it. The development kit must
> be simple to use for programming and debug and not very expensive. I'd
> like that the software included was able to simplify the configuration
> of the connections of the board and that the debug of the chip could
> be done by the software.
> An Altera reseller proposed me the Nios development kit, but I think
> it is difficult to use for the students. What do u think about it?
> There is a good product by Xilinx?
> Thanks for the answer.
>



Article: 55532
Subject: wire and reg and modelling of combinational logic
From: "geeko" <jibin@ushustech.com>
Date: Mon, 12 May 2003 10:28:39 +0530
Links: << >>  << T >>  << A >>
Hi all
        I have some questions about the modelling of combinational logic
using verilog . an AND gate can be modelled using the wire construct as
shown below .


module ( a, b, y);
  input a, b;
  output y;
  wire a, b, y;
  assign y = a & b;
endmodule


The same circut can also be modelled with a reg construct .



module ( a, b, y);
input a, b;
output y;
reg   y;
wire a, b;
always @ ( a or b)
y = a & b;
endmodule


Which description is considered as the best.What exactly the physical
significance of a reg constuct

cheers







Article: 55533
Subject: Re: where to buy 1 virtex-e fg680
From: Peter Rauschert <usenet@rauschert-online.de>
Date: Mon, 12 May 2003 08:14:18 +0200
Links: << >>  << T >>  << A >>
>Anybody know where I can buy a single fg680? I cannot even get the price.
>
>Thanks.
>
>Wei
>

Always good to know the price : http://www.plis.ru/price.html?ID=112 

But ordering can be a little bit difficult (.ru) :-) ..

maybe http://www.xilinx.com/company/sales/ww_disti.htm will help you
to find a distributor

Peter

Article: 55534
Subject: Xilinx : Tools
From: "Vlsi Champ" <vlsi_champ@indiatimes.com>
Date: Sun, 11 May 2003 23:19:50 -0700
Links: << >>  << T >>  << A >>
Hello Friends,

Can u pls tell me whats the diff between webpack tool an the ISE tool?
I found the GUI same for both....I have used ISe but never used webpack....

regards,

VLSI CHAMP....



Article: 55535
Subject: Exploting the DDR input registers in Virtex2
From: "John Daae" <john.daae@datarespons.no>
Date: Mon, 12 May 2003 08:47:03 +0200
Links: << >>  << T >>  << A >>
I am implementing a system using a PCI-X core from Xilinx and I want to to
use the spare input registers (the second DDR input register) that the core
is not using. I have tried using IOB attribute on the actual signals in my
VHDL code and I have tried IOB = TRUE constraint in the UCF file, but the
PAR seems to ignore these guidings.

Any suggestions?
Is there a primitive for inputs register that I can instatiate?


Thanks


John





Article: 55536
Subject: MMIX Implementation
From: Jon Masters <jonathan@jonmasters.org>
Date: Mon, 12 May 2003 08:09:08 +0100
Links: << >>  << T >>  << A >>
Hi,

Can someone update me on the status of implementing MMIX - has it been 
done? I would at least be interested in getting involved with it.

Cheers,

Jon.


Article: 55537
Subject: Register in FPGA
From: "Jens Nowack" <its.me.hates-spam@uni.de>
Date: Mon, 12 May 2003 10:23:57 +0200
Links: << >>  << T >>  << A >>
Hallo,

I want to create a register in the fpga to store control settings. There
should be e.g. 256 registers in it with a wide of e.g. 16 Bit.
The selection of internal registers will be done using the adress bus of the
microcontroller. The external databus must be bi-directional  and tristate.
The registers can be written from the microcontroller or the FPGA. And I
must have a direct read access to the registers in the FPGA without
adressing to controll the logical circuits. So a RAM is useless, i think.


Now my question:
whats the best way to realise this task? I use an Altera Cyclone FPGA with
VHDL as programming language. Maybe, a little example would be usefull.

Thanks a lot,

regards



Article: 55538
Subject: CRC Generator for 6Byte serial Transmission
From: "Markus Meng" <meng.engineering@bluewin.ch>
Date: Mon, 12 May 2003 09:23:30 -0000
Links: << >>  << T >>  << A >>
Hi all,

I was looking for a implementation - pref. VHDL - for an 7 or 8 bit CRC
generator
for a serial transmission unit that transports max length of 6 bytes. Any
hint or link would
be appreciated. Thank's.

best regards
markus


-- 
Mit freundlichen Grüssen
Markus Meng

P.S. Achtung wir haben eine neue FAX-Nummer
********************************************************************
** Meng Engineering        Telefon    056 222 44 10               **
** Markus Meng             Natel      079 230 93 86               **
** Bruggerstr. 21          Telefax    056 222 44 34 <-- NEU !!    **
** CH-5400 Baden           Email      meng.engineering@bluewin.ch **
**                         Web        www.meng-engineering.ch     **
********************************************************************
** You cannot create experience. You must undergo it. Albert Camus**







-----= Posted via Newsfeeds.Com, Uncensored Usenet News =-----
http://www.newsfeeds.com - The #1 Newsgroup Service in the World!
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Article: 55539
Subject: Re: Register in FPGA
From: Mario Trams <Mario.Trams@informatik.tu-chemnitz.de>
Date: Mon, 12 May 2003 12:54:51 +0200
Links: << >>  << T >>  << A >>
Jens Nowack wrote:

> Hallo,
> 
> I want to create a register in the fpga to store control settings. There
> should be e.g. 256 registers in it with a wide of e.g. 16 Bit.
> The selection of internal registers will be done using the adress bus of
> the
> microcontroller. The external databus must be bi-directional  and
> tristate. The registers can be written from the microcontroller or the
> FPGA. And I must have a direct read access to the registers in the FPGA
> without adressing to controll the logical circuits. So a RAM is useless, i
> think.

Would a Dual-Ported RAM also be useless?

> Now my question:
> whats the best way to realise this task? I use an Altera Cyclone FPGA with
> VHDL as programming language. Maybe, a little example would be usefull.

So the only way is a simple but very big multiplexer (i.e. 16 x 256:1 in
your case) that selects the right register for reading. For such a big one
you should build it upon a hierarchy of smaller muxes. If available, you
also might make use of tristatable busses.
But anyways, such big muxes are quite costly.

Perhaps your application allows you to use a mixture of RAM and registers
in order to simplify things a little bit.

Regards,
Mario

Article: 55540
Subject: Re: Xilinx : Tools
From: "Neeraj Varma" <neeraj@cg-coreel.com>
Date: Mon, 12 May 2003 17:18:29 +0530
Links: << >>  << T >>  << A >>
ISE Webpack is free and supports limited devices.
ISE Foundation needs to be purchased and supports all devices.

There are some more feature differences, which you can read here:
http://www.xilinx.com/ise/devsys_feature_guide.pdf

--Neeraj

"Vlsi Champ" <vlsi_champ@indiatimes.com> wrote in message
news:ee7d632.-1@WebX.sUN8CHnE...
Hello Friends,
Can u pls tell me whats the diff between webpack tool an the ISE tool? I
found the GUI same for both....I have used ISe but never used webpack....
regards,
VLSI CHAMP....



Article: 55541
Subject: Re: Register in FPGA
From: Ray Andraka <ray@andraka.com>
Date: Mon, 12 May 2003 11:58:00 GMT
Links: << >>  << T >>  << A >>
You can often simplfy readback of control registers that are written only by the
microcontroller by putting a shadow 'register' in RAM in addition to the
physical register.  The physical register provides the individual bits to the
circuit while a RAM which is simultaneously written provides a copy of the data
in a convenient form for easy readback.  If you have a small number of status
registers whose contents are updated by the FPGA logic, you can sometimes use a
dual port memory for the shadow register with the second port hardwired for
write at a specific address so that the status info winds up in the proper
location in the shadow RAM.

Jens Nowack wrote:

> Hallo,
>
> I want to create a register in the fpga to store control settings. There
> should be e.g. 256 registers in it with a wide of e.g. 16 Bit.
> The selection of internal registers will be done using the adress bus of the
> microcontroller. The external databus must be bi-directional  and tristate.
> The registers can be written from the microcontroller or the FPGA. And I
> must have a direct read access to the registers in the FPGA without
> adressing to controll the logical circuits. So a RAM is useless, i think.
>
> Now my question:
> whats the best way to realise this task? I use an Altera Cyclone FPGA with
> VHDL as programming language. Maybe, a little example would be usefull.
>
> Thanks a lot,
>
> regards

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 55542
Subject: Re: CRC Generator for 6Byte serial Transmission
From: Peter Rauschert <usenet@rauschert-online.de>
Date: Mon, 12 May 2003 14:05:53 +0200
Links: << >>  << T >>  << A >>
hi Markus ...

>I was looking for a implementation - pref. VHDL - for an 7 or 8 bit CRC
>generator
>for a serial transmission unit that transports max length of 6 bytes. Any
>hint or link would
>be appreciated. Thank's.

Create a LFSR with the right polynomial (see
http://www.xilinx.com/xapp/xapp052.pdf) for a sequential
implementation and make a polynomial division.

To get a fast solution just use the equations from this great webtool
: http://www.easics.com/webtools/crctool . Also Xilinx has an
application note under http://www.xilinx.com/xapp/xapp209.pdf for a
fast implementation.  But for these solutions I guess you have to use
a data width of 8bits ....

Hope this helps !

Article: 55543
Subject: Re: where to buy 1 virtex-e fg680
From: Ray Andraka <ray@andraka.com>
Date: Mon, 12 May 2003 12:19:43 GMT
Links: << >>  << T >>  << A >>
Did you try http://www.avnetmarshall.com/dynamic/search?

tsj wrote:

> Anybody know where I can buy a single fg680? I cannot even get the price.
>
> Thanks.
>
> Wei

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 55544
Subject: Re: PLL in fpga
From: "Jochen Frensch" <frensch@xsys.de>
Date: Mon, 12 May 2003 05:24:26 -0700
Links: << >>  << T >>  << A >>
Hi Austin, 

haven't found any specification for Spartan-III-DCM yet, but "DS099-3 (v1.0) April 11, 2003" says Minimum 25 MHz as a DLL-Input !?!!! - NOT 1 MHz 

Are there any further specifications (I haven't found yet) ? 



Article: 55545
Subject: Re: PacMan game in FPGA
From: Dave Vanden Bout <devb@xess.com>
Date: Mon, 12 May 2003 08:32:08 -0400
Links: << >>  << T >>  << A >>
Wil Limbacher wrote:

> I'm looking at the XSA100 for a project, but there's one thing I can't seem
> to find in the literature. What's the speed grade of the XC2S100 part on the
> board?

It's a -5 part.




>
>
> "Paul Hartke" <phartke@Stanford.EDU> wrote in message
> news:3EBE10BC.22087B6E@Stanford.EDU...
> > Pacman is a periodic final project for the Stanford intro to logic
> > design class--most recently last quarter.  We use the Xess XSA-100
> > boards: http://www.xess.com/prod026.php3.  Most of the projects use
> > between half and two thirds of the Spartan2 XC2S100 FPGA for the basics
> > of game play and a few bells and whistles.  As always, motivated and
> > clever folks could add features utilizing the largest FPGAs available
> > but you can certainly make a nice game with a XC2S100 size device.
> >
> > One group even implemented A-star search in gates for the ghost
> > movement.  Those ghosts were pretty hard to evade!  :-)
> >
> > Paul
> >
> > Kyle Davis wrote:
> > >
> > > Hi all,
> > > I am interested to build a PacMan game with Xilinx FPGA. I am going to
> use
> > > Verilog. How many gates do you think is required for this project? What
> type
> > > of chip should I consider for this project?
> > > Thanks!
> > >
> > > Hendra




--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 303-2883 ||
|| devb@xess.com           2501-B Ten-Ten Road      (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 303-2884 ||




Article: 55546
Subject: Re: QuartusII issue
From: "Ruth" <ruthsims@hotmail.com>
Date: Mon, 12 May 2003 13:35:19 +0100
Links: << >>  << T >>  << A >>
Open the license file in a text editor and check that each "Feature" starts
on a new line.  Sometimes but not always Quartus screws up if they don't
start on a new line.  ie you should see something like:

FEATURE maxplus2 alterad xxxxxxxxxxxxxxxxxxxxxxxxxxxxx\
 HOSTID=GUARD_ID=xxxxxxxxxxxxxxxxx\
 xxxxxxxxxxxxxxxxx\
 xxxxxxxxxxxxxxxx"
FEATURE quartus alterad xxxxxxxxxxxxxxxxxx\
 HOSTID=GUARD_ID=xxxxxxxxxxxxxxxxxxxxxx\
 xxxxxxxxxxxxxxxxxx\
xxxxxxxxxxxxxxxxxxx"
FEATURE xxxxxxxxxxxxxxxxxxxxxxx\
 xxxxxxxxxxxxxxHOSTID=GUARD_ID=xxxxxxxxxxxxxxxxxxxxxxxxx\
 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\
 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"
FEATURE maxplus2vhdl alterad xxxxxxxxxxxxxxxxxxxx\
.............................

not like:

FEATURE maxplus2 alterad xxxxxxxxxxxxxxxxxxxxxxxxxxxxx\
 HOSTID=GUARD_ID=xxxxxxxxxxxxxxxxx\
 xxxxxxxxxxxxxxxxx\
 xxxxxxxxxxxxxxxx" FEATURE quartus alterad xxxxxxxxxxxxxxxxxx\
 HOSTID=GUARD_ID=xxxxxxxxxxxxxxxxxxxxxx\
 xxxxxxxxxxxxxxxxxx\
xxxxxxxxxxxxxxxxxxx" FEATURE xxxxxxxxxxxxxxxxxxxxxxx\
 xxxxxxxxxxxxxxHOSTID=GUARD_ID=xxxxxxxxxxxxxxxxxxxxxxxxx\
 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\
 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"
FEATURE maxplus2vhdl alterad xxxxxxxxxxxxxxxxxxxx\
.............................

Ruth


"pc" <acosmos@freemail.gr> wrote in message
news:b9mna1$8bl$1@usenet.otenet.gr...
> I have downloaded the quartusII v2.2 web edition from altera BUT i cant
use
> it with the license i 've been send from them.
> Has anyone the same problem? what is the solution? Thanks.
>
>



Article: 55547
Subject: Re: Xilinx : Tools
From: "Leon Heller" <leon_heller@hotmail.com>
Date: Mon, 12 May 2003 13:24:22 +0000 (UTC)
Links: << >>  << T >>  << A >>

"Vlsi Champ" <vlsi_champ@indiatimes.com> wrote in message
news:ee7d632.-1@WebX.sUN8CHnE...
Hello Friends,
Can u pls tell me whats the diff between webpack tool an the ISE tool? I
found the GUI same for both....I have used ISe but never used webpack....

Webpack is a lot cheaper. 8-)

Seriously, Webpack only lets you use a (fairly small) subset of the devices.

Leon
-- 
Leon Heller, G1HSM
leon_heller@hotmail.com
http://www.geocities.com/leon_heller



Article: 55548
Subject: Re: CRC Generator for 6Byte serial Transmission
From: mrand@my-deja.com (Marc Randolph)
Date: 12 May 2003 06:29:13 -0700
Links: << >>  << T >>  << A >>
"Markus Meng" <meng.engineering@bluewin.ch> wrote in message news:<3ebf4d01_8@corp.newsgroups.com>...
> Hi all,
> 
> I was looking for a implementation - pref. VHDL - for an 7 or 8 bit CRC
> generator for a serial transmission unit that transports max length of 
> 6 bytes. Any hint or link would be appreciated. Thank's.

Howdy Markus,

It shouldn't be too difficult to find lots of VHDL examples that
implements the ATM header CRC (CRC-8 which uses the generating
polynomial X^8+X^2+X+1) using http://www.google.com ... here is but
one link: http://www.easics.be/webtools/crctool

Have fun,

   Marc

P.S. This was really a question for comp.lang.vhdl

Article: 55549
Subject: OK I am pissed off with Xilinx webpack.
From: Jan Panteltje <panteltje@yahoo.com>
Date: Mon, 12 May 2003 14:14:34 GMT
Links: << >>  << T >>  << A >>
It should:
Do as it is told.
Not change things.
Not give cryptographic messages like:
 'udc0_uf1_s2_Mrom_dout_inst_mux_f5_48'
 I can find out what it is perhaps, but it should refer to the verilog code
 names.
I do not care if it is driving a 'MUXF6', a F16 or an apple tree.
It should just do it if I requested it.
EVEN IF IT DOES NOT WORK OR CAUSES AN EARTHQUAKE
Else you get in a loop of endless trying.

If I use a hammer and break it on something fine.
I do NOT want a hammer that warns me and refuses to hit any nail it
thinks is bend.
'I' am the designer.
And I never asked for a MUXF5 OR a MUXF6.
This whole thing is just GATES!

Oh, I see, GATES -> Microsoft -> oh, should have known.
OK, cut that remark, it is unfair, but it shows US acquired Taliban...
OK cut that too.
But what has MS brought us? Advertizing on internet.
NSA backdoor, they know everything.
I bet they also know good tools to program FPGA.



Design Summary
--------------
   Number of errors:      0
   Number of warnings:   27
   Number of Slices:              2,350 out of  2,352   99%
   Number of Slices containing
      unrelated logic:               37 out of  2,350    1%
   Total Number Slice Registers:    281 out of  4,704    5%
      Number used as Flip Flops:                  280
      Number used as Latches:                       1
   Total Number 4 input LUTs:     4,183 out of  4,704   88%
      Number used as LUTs:                      3,761
      Number used as a route-thru:                422
   Number of bonded IOBs:             3 out of    140    2%
   Number of GCLKIOBs:                2 out of      4   50%
Total equivalent gate count for design:  38,728
Additional JTAG gate count for IOBs:  240

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:MapLib:157 - MUXF5 symbol "udc0_uf1_s2_Mrom_dout_inst_mux_f5_48" (output

   signal=udc0_uf1_s2_Mrom_dout_inst_mux_f5_48) is configured as a route-thru.

   However, since it is driving a MUXF6, such transformation will not be carried

   out.
WARNING:MapLib:157 - MUXF5 symbol "udc0_uf1_s2_Mrom_dout_inst_mux_f5_49" (output

   signal=udc0_uf1_s2_Mrom_dout_inst_mux_f5_49) is configured as a route-thru.

   However, since it is driving a MUXF6, such transformation will not be carried

   out.
WARNING:MapLib:157 - MUXF5 symbol "udc0_uf1_s2_Mrom_dout_inst_mux_f5_50" (output

   signal=udc0_uf1_s2_Mrom_dout_inst_mux_f5_50) is configured as a route-thru.

   However, since it is driving a MUXF6, such transformation will not be carried

   out.
WARNING:MapLib:157 - MUXF5 symbol "udc0_uf1_s2_Mrom_dout_inst_mux_f5_51" (output

   signal=udc0_uf1_s2_Mrom_dout_inst_mux_f5_51) is configured as a route-thru.

   However, since it is driving a MUXF6, such transformation will not be carried

   out.
WARNING:MapLib:157 - MUXF5 symbol "udc0_uf1_s2_Mrom_dout_inst_mux_f5_52" (output

   signal=udc0_uf1_s2_Mrom_dout_inst_mux_f5_52) is configured as a route-thru.

   However, since it is driving a MUXF6, such transformation will not be carried

   out.
WARNING:MapLib:157 - MUXF5 symbol "udc0_uf1_s2_Mrom_dout_inst_mux_f5_53" (output

   signal=udc0_uf1_s2_Mrom_dout_inst_mux_f5_53) is configured as a route-thru.

   However, since it is driving a MUXF6, such transformation will not be carried

   out.
WARNING:MapLib:157 - MUXF5 symbol "udc0_uf1_s2_Mrom_dout_inst_mux_f5_54" (output

   signal=udc0_uf1_s2_Mrom_dout_inst_mux_f5_54) is configured as a route-thru.

   However, since it is driving a MUXF6, such transformation will not be carried

   out.
WARNING:MapLib:157 - MUXF5 symbol "udc0_uf1_s2_Mrom_dout_inst_mux_f5_55" (output

   signal=udc0_uf1_s2_Mrom_dout_inst_mux_f5_55) is configured as a route-thru.

   However, since it is driving a MUXF6, such transformation will not be carried

   out.
WARNING:MapLib:155 - MUXF5 symbol "udc0_uf1_s3_Mrom_dout_inst_mux_f5_40" (output

   signal=udc0_uf1_s3_Mrom_dout_inst_mux_f5_40) can be reduced to a constant

   driver. However, since it is driving a MUXF6, such optimization will not be

   carried out.
WARNING:MapLib:155 - MUXF5 symbol "udc0_uf1_s3_Mrom_dout_inst_mux_f5_41" (output

   signal=udc0_uf1_s3_Mrom_dout_inst_mux_f5_41) can be reduced to a constant

   driver. However, since it is driving a MUXF6, such optimization will not be

   carried out.
WARNING:MapLib:155 - MUXF5 symbol "udc0_uf1_s3_Mrom_dout_inst_mux_f5_42" (output

   signal=udc0_uf1_s3_Mrom_dout_inst_mux_f5_42) can be reduced to a constant

   driver. However, since it is driving a MUXF6, such optimization will not be

   carried out.
WARNING:MapLib:155 - MUXF5 symbol "udc0_uf1_s3_Mrom_dout_inst_mux_f5_43" (output

   signal=udc0_uf1_s3_Mrom_dout_inst_mux_f5_43) can be reduced to a constant

   driver. However, since it is driving a MUXF6, such optimization will not be

   carried out.
WARNING:MapLib:155 - MUXF5 symbol "udc0_uf1_s3_Mrom_dout_inst_mux_f5_44" (output

   signal=udc0_uf1_s3_Mrom_dout_inst_mux_f5_44) can be reduced to a constant

   driver. However, since it is driving a MUXF6, such optimization will not be

   carried out.
WARNING:MapLib:155 - MUXF5 symbol "udc0_uf1_s3_Mrom_dout_inst_mux_f5_45" (output

   signal=udc0_uf1_s3_Mrom_dout_inst_mux_f5_45) can be reduced to a constant

   driver. However, since it is driving a MUXF6, such optimization will not be

   carried out.
WARNING:MapLib:155 - MUXF5 symbol "udc0_uf1_s3_Mrom_dout_inst_mux_f5_46" (output

   signal=udc0_uf1_s3_Mrom_dout_inst_mux_f5_46) can be reduced to a constant

   driver. However, since it is driving a MUXF6, such optimization will not be

   carried out.
WARNING:MapLib:155 - MUXF5 symbol "udc0_uf1_s3_Mrom_dout_inst_mux_f5_47" (output

   signal=udc0_uf1_s3_Mrom_dout_inst_mux_f5_47) can be reduced to a constant

   driver. However, since it is driving a MUXF6, such optimization will not be

   carried out.
WARNING:MapLib:157 - MUXF5 symbol "udc0_uf2_s7_Mrom_dout_inst_mux_f5_8" (output

   signal=udc0_uf2_s7_Mrom_dout_inst_mux_f5_8) is configured as a route-thru.

   However, since it is driving a MUXF6, such transformation will not be carried

   out.
WARNING:MapLib:157 - MUXF5 symbol "udc0_uf2_s7_Mrom_dout_inst_mux_f5_9" (output

   signal=udc0_uf2_s7_Mrom_dout_inst_mux_f5_9) is configured as a route-thru.

   However, since it is driving a MUXF6, such transformation will not be carried

   out.
WARNING:MapLib:157 - MUXF5 symbol "udc0_uf2_s7_Mrom_dout_inst_mux_f5_10" (output

   signal=udc0_uf2_s7_Mrom_dout_inst_mux_f5_10) is configured as a route-thru.

   However, since it is driving a MUXF6, such transformation will not be carried

   out.
WARNING:MapLib:157 - MUXF5 symbol "udc0_uf2_s7_Mrom_dout_inst_mux_f5_11" (output

   signal=udc0_uf2_s7_Mrom_dout_inst_mux_f5_11) is configured as a route-thru.

   However, since it is driving a MUXF6, such transformation will not be carried

   out.
WARNING:MapLib:157 - MUXF5 symbol "udc0_uf2_s7_Mrom_dout_inst_mux_f5_12" (output

   signal=udc0_uf2_s7_Mrom_dout_inst_mux_f5_12) is configured as a route-thru.

   However, since it is driving a MUXF6, such transformation will not be carried

   out.
WARNING:MapLib:157 - MUXF5 symbol "udc0_uf2_s7_Mrom_dout_inst_mux_f5_13" (output

   signal=udc0_uf2_s7_Mrom_dout_inst_mux_f5_13) is configured as a route-thru.

   However, since it is driving a MUXF6, such transformation will not be carried

   out.
WARNING:MapLib:157 - MUXF5 symbol "udc0_uf2_s7_Mrom_dout_inst_mux_f5_14" (output

   signal=udc0_uf2_s7_Mrom_dout_inst_mux_f5_14) is configured as a route-thru.

   However, since it is driving a MUXF6, such transformation will not be carried

   out.
WARNING:MapLib:157 - MUXF5 symbol "udc0_uf2_s7_Mrom_dout_inst_mux_f5_15" (output

   signal=udc0_uf2_s7_Mrom_dout_inst_mux_f5_15) is configured as a route-thru.

   However, since it is driving a MUXF6, such transformation will not be carried

   out.

And indeed it gives an error and asks me to RELOC or whatever something
that I cannot even locate as it has not mapped anything....

All this stuff takes too much time.

And this is highly expanded optimized logic for SPEED.

 



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