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> Number of Slices: 192 out of 192 100% > Number of Slice Flip Flops: 292 out of 384 76% > Total Number 4 input LUTs: 339 out of 384 88% > Number of bonded IOBs: 69 out of 86 80% > Number of Tbufs: 16 out of 224 7% > Number of Block RAMs: 3 out of 4 75% > Number of GCLKs: 4 out of 4 100% > Number of GCLKIOBs: 4 out of 4 100% Don't like Tbufs? :) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 55651
Followup to: <3EC2AF0E.331C@designtools.co.nz> By author: jim.granville@designtools.co.nz In newsgroup: comp.arch.fpga > > Ray Andraka wrote: > > > <snip> > > Design Summary > > -------------- > > Number of errors: 0 > > Number of warnings: 147 > > Number of Slices: 192 out of 192 100% > > Number of Slices containing > > unrelated logic: 34 out of 192 17% > > :)) - amusing choice of words, just what can 'containing unrelated > logic' > mean!. > > One would hope that all logic was related to the design ? > "Unrelated logic" seems to mean that the fitter has packed more than one piece of logic into the same slice without there being any particular connection between them. A high number here *might* mean that you're starting to be capacity-constrained, and that your timings will start to suffer. -hpa -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 55652
Hi Mike,
Here's the code. Its fine with the functional simulation but after
P&R, I have the problems as mentioned. Thanks.
library ieee;
use ieee.std_logic_1164.all;
entity mooredemo is
port (
output : out std_logic_vector ( 1 downto 0 );
clk, rst, input : in std_logic
);
end;
architecture arch of mooredemo is
type statetype is (S0,S1,S2,S3);
signal current_state, next_state : statetype;
begin
sequential_proc : process (rst, clk)
begin
if rst = '0' then
current_state <= S0;
elsif clk'event and clk = '1' then
current_state <= next_state;
end if;
end process;
combinational_proc : process ( current_state, input )
begin
case current_state is
when S0 => if input = '1' then
next_state <= S1;
output <= "00";
else
next_state <= S0;
output <= "11";
end if;
when S1 => if input = '0' then
next_state <= S2;
output <= "01";
else
next_state <= S1;
output <= "00";
end if;
when S2 => if input = '1' then
next_state <= S3;
output <= "10";
else
next_state <= S2;
output <= "01";
end if;
when S3 => if input = '1' then
next_state <= S0;
output <= "11";
else
next_state <= S3;
output <= "10";
end if;
when others => next_state <= S0;
output <= "11";
end case;
end process;
end arch;
Article: 55653In article <3EC2A28D.BE2641B@andraka.com>, Ray Andraka <ray@andraka.com> wrote: > Total Number 4 input LUTs: 339 out of 384 88% > Number used as LUTs: 229 > Number used as Shift registers: 110 HA, less than 1/2 are used as SRLs. Why you complainin about Spartan 3's 1/2 capacity of SRLs anyway? :) -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 55654
Muzaffer Kal <kal@dspia.com> wrote in message news:<7ev4cv8kt30u4ltkisda3l6jtevjss68nk@4ax.com>... > On 13 May 2003 19:15:15 -0700, tatto0_2000@yahoo.com (Wong) wrote: > > >Hi Mike, > > Thanks for the pointer. But what if I have a synchronous design or > >output registers and the device pins (make it simple, let say 2 bit > >bus) still glitchy ? For example, I have the following SDF : > > If you're talking about the outputs of the registers arriving at the > pins at different times, you can't avoid it completely. The best you > can do is to instantiate the output registers at known locations > (better yet, use the flops in the IOs) and make sure that the loads of > the registers are the same (mainly the IO input capacitance). In that > case, the two outputs are as balanced as they can get and the rest has > to be tolerated by receiving logic. I think you are talking about the IOB using Xilinx FPGAs, correct? Since I am doing the P&R using anti-fuse FPGAs and I might not be able to find the flops in the IOs except the loading(capacitance) of the 'output buffers'. Anyhow, thanks Muzaffer. > > Muzaffer Kal > > http://www.dspia.com > ASIC/FPGA design/verification consulting specializing in DSP algorithm implementationsArticle: 55655
hi i need some help on how to multiplex multipliers( and other inbuilt resources) used in different clock cycles, or if else statements.as in the following code where my synthesis tool uses 12 multipliers( where only 4 is needed,the multipliers here are 14-bit multipliers).i am using xilinx virtex-II xc2v2000 fpga and xilinx ISE 2.3 is the synthesis tool. if(sel="00") then sin1<=signed(s)*signed(cosine3(z(5)/2)); sin2<=signed(c)*signed(si3(z(5)/2)); cos1<=signed(c)*signed(cosine3(z(5)/2)); cos2<=signed(s)*signed(si3(z(5)/2)); si<=si3(z(5)/2); co<=cosine3(z(5)/2); elsif(sel="01") then sin1<=signed(s)*signed(cosine2(z(5)/2)); sin2<=signed(c)*signed(si2(z(5)/2)); cos1<=signed(c)*signed(cosine2(z(5)/2)); cos2<=signed(s)*signed(si2(z(5)/2)); si<=si2(z(5)/2); co<=cosine2(z(5)/2); else sin1<=signed(s)*signed(cosine1(z(5)/2)); sin2<=signed(c)*signed(si1(z(5)/2)); cos1<=signed(c)*signed(cosine1(z(5)/2)); cos2<=signed(s)*signed(si1(z(5)/2)); si<=si1(z(5)/2); co<=cosine1(z(5)/2); end if; do let me know of any suggestions. thanks johnArticle: 55656
Hi Marc & Avrum, Thanks for your time and advice. I want to use the second IFF in IOB for sampling analyzing the PCI-X bus in parallel to the PCI-X core. Unfortunately the PCI-X core use pci-rst as asynchronous reset for the IFFs while I need to sample the bus correctly also during pci-rst. This might be core of my problem. I thought I could disable the asynchronous reset for one of the IFFs and keep it for the other. Now, I tried this in FPGA Editor, which reports an error when I try this. Thanks anyway for your help. If still have any suggestions getting around this problem that would be most welcome. "Avrum" <avrum@REMOVEsympatico.ca> wrote in message news:Lf6wa.1564$z13.321658@news20.bellglobal.com... > Marc, > > It seems that you are right - the tools have some ability to use otherwise > unused IOBs (bonded or unbonded) as resources. > > However, the answer to the original question is the same - if the IOB is > used as an input (in the original posting it was used by the PCI-X core), > the other INFF flop is only useable for clocking in data from the pin - the > D inputs of the two INFF flops are hard wired together. > > Avrum > > > "Marc Randolph" <mrand@my-deja.com> wrote in message > news:15881dde.0305122001.1f5946e9@posting.google.com... > > "Avrum" <avrum@REMOVEsympatico.ca> wrote in message > news:<XzRva.2205$mK2.183157@news20.bellglobal.com>... > > > What do you want to do with the DDR flops. These are not general purpose > > > flops that can be used in place of a core flop; they are specifically > there > > > to clock the data on the input pin - the D input of both INFF flops in > an > > > IOB can ONLY be connected to the input receiver of the IOB. > > > > > > > Howdy Avrum, > > > > I don't believe this is correct. Certainly, there are some > > restrictions, but investigate the "use Bonded I/Os" option on the par > > (Place & Route) program. > > > > In fact (I just discovered), it appears you can even use the registers > > in UNbonded IOB's! Learn something new everyday... see > > > > > http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID= > 1&getPagePath=12209 > > > > for details (if the link wraps, click here instead: > > http://tinyurl.com/bmb4 ). > > > > Have fun, > > > > Marc > >Article: 55657
John Williams <jwilliams@itee.uq.edu.au> wrote: :... : I know you're a bit of an "ISE under linux" guru - are you able to run : xflow successfully? I'm using fpga.flw, the implementation flow, and : fast_runtime.opt. I must admit that I have no idea about xflow at all. I mostly use ISE or cut and paste the commands from xxx..cmd_log. Can you send me an example, an explication how to run, what result to expect and what you consider an error. I then would try to have a look at the problem. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 55658
hi all, can anyone tell me which state machine is good (Moore or Mealy).. Why? rgds,Article: 55659
Rewrite your code so that the if/elsif/else stuff just selects the operands, then do the 4 multiplys outside this structure, using the selected operands. probably looks like this: if(sel="00") then op1<=signed(cosine3(z(5)/2)); op2<=signed(si3(z(5)/2)); op3<=signed(cosine3(z(5)/2)); op4<=signed(si3(z(5)/2)); si<=si3(z(5)/2); co<=cosine3(z(5)/2); elsif(sel="01") then op1<=signed(cosine2(z(5)/2)); op2<=signed(si2(z(5)/2)); op3<=signed(cosine2(z(5)/2)); op4<=signed(si2(z(5)/2)); si<=si2(z(5)/2); co<=cosine2(z(5)/2); else op1<=signed(cosine1(z(5)/2)); op2<=signed(si1(z(5)/2)); op3<=signed(cosine1(z(5)/2)); op4<=signed(si1(z(5)/2)); si<=si1(z(5)/2); co<=cosine1(z(5)/2); end if; sin1<=signed(s)*signed(op1); sin2<=signed(c)*signed(op2); cos1<=signed(c)*signed(op3); cos2<=signed(s)*signed(op4)); Philip Freidin On 14 May 2003 22:34:18 -0700, jeffry15@rediffmail.com (john paul) wrote: >hi > > i need some help on how to multiplex multipliers( and other inbuilt >resources) >used in different clock cycles, or if else statements.as in the >following code > where my synthesis tool uses 12 multipliers( where only 4 is >needed,the multipliers here are 14-bit multipliers).i am using xilinx >virtex-II xc2v2000 fpga and xilinx ISE 2.3 is the synthesis tool. > >if(sel="00") then > sin1<=signed(s)*signed(cosine3(z(5)/2)); > sin2<=signed(c)*signed(si3(z(5)/2)); > cos1<=signed(c)*signed(cosine3(z(5)/2)); > cos2<=signed(s)*signed(si3(z(5)/2)); > si<=si3(z(5)/2); > co<=cosine3(z(5)/2); > > > elsif(sel="01") then > > sin1<=signed(s)*signed(cosine2(z(5)/2)); > sin2<=signed(c)*signed(si2(z(5)/2)); > cos1<=signed(c)*signed(cosine2(z(5)/2)); > cos2<=signed(s)*signed(si2(z(5)/2)); > si<=si2(z(5)/2); > co<=cosine2(z(5)/2); > > else > sin1<=signed(s)*signed(cosine1(z(5)/2)); > sin2<=signed(c)*signed(si1(z(5)/2)); > cos1<=signed(c)*signed(cosine1(z(5)/2)); > cos2<=signed(s)*signed(si1(z(5)/2)); > si<=si1(z(5)/2); > co<=cosine1(z(5)/2); > > end if; > >do let me know of any suggestions. >thanks >john Philip Freidin FliptronicsArticle: 55660
I am going to programme a 8x8 shared-buffer memory routing switch, and I am using Verilog on Xilinx Webpack 5.1i. However, I encounter the following problem: NgdBuild:755 - Line line_no in 'filename': Could not find net(s) 'net_name' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. I have found from the Xilinx Answer Database that the service pack has already fixed the problems. But I encounter the same error message after I have installed the service pack. Can anyone please help me? Thanks. IsabelArticle: 55661
Hi all, my Spartan-II 2S200 has 7 different clock domains! Four of them use the global clock buffers with speed ratio of 24, 48 and 96 MHz. I do have 3 additional clock domains that do have minimal logic in a decoder and must use others 'glock' resources. How can I in the UCF File or in an other place speed constrain those seven logic groups, that it really works. Logic related to 24 Mhz must not run at 100 Mhz and so on ... I'am using ISE 5.1i I must use Spartan-II ... Thank's for any hint or help Markus -- Mit freundlichen Grüssen Markus Meng P.S. Achtung wir haben eine neue FAX-Nummer ******************************************************************** ** Meng Engineering Telefon 056 222 44 10 ** ** Markus Meng Natel 079 230 93 86 ** ** Bruggerstr. 21 Telefax 056 222 44 34 <-- NEU !! ** ** CH-5400 Baden Email meng.engineering@bluewin.ch ** ** Web www.meng-engineering.ch ** ******************************************************************** ** You cannot create experience. You must undergo it. Albert Camus** -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 55662
Now XC3S-50 is a usefull SPARTAN-3, or just, now it is a SPARTAN-3. Very good! Luiz Carlos Oenning Martins KHOMP SolutionsArticle: 55663
Nope. The physical pitch doesn't match the bit pitch making them a PITA. In
this case they are used as a mux to shoe horn more function in.
Hal Murray wrote:
> > Number of Slices: 192 out of 192 100%
> > Number of Slice Flip Flops: 292 out of 384 76%
> > Total Number 4 input LUTs: 339 out of 384 88%
> > Number of bonded IOBs: 69 out of 86 80%
> > Number of Tbufs: 16 out of 224 7%
> > Number of Block RAMs: 3 out of 4 75%
> > Number of GCLKs: 4 out of 4 100%
> > Number of GCLKIOBs: 4 out of 4 100%
>
> Don't like Tbufs? :)
>
> --
> The suespammers.org mail server is located in California. So are all my
> other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
> commercial e-mail to my suespammers.org address or any of my other addresses.
> These are my opinions, not necessarily my employer's. I hate spam.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55664> Search this newsgroup to find out why it did not work. > It's a combination of broken software and an inferior schematic. > The impact replaced the broken hardware debugger, whats left is the > inferior schematic. > > Adding feedback resistors of 2K or so between the buffer outputs and > inputs helps in many cases. Using a HCT chip with a low switching > point (0.3 time VCC) improves the results even further. > > Kolja Sulimma Thanks, Kolja, I've found the old threads you're talking about. As soon as I find the time, I'll make the changes to the schematics/PCB and post a new version.Article: 55665
Yeah, and the clock rate is much slower than what I usually do too.
"Nicholas C. Weaver" wrote:
> In article <3EC2A28D.BE2641B@andraka.com>,
> Ray Andraka <ray@andraka.com> wrote:
> > Total Number 4 input LUTs: 339 out of 384 88%
> > Number used as LUTs: 229
> > Number used as Shift registers: 110
>
> HA, less than 1/2 are used as SRLs. Why you complainin about
> Spartan 3's 1/2 capacity of SRLs anyway? :)
>
> --
> Nicholas C. Weaver nweaver@cs.berkeley.edu
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55666Hello, I have a design on an Apex20K 400. After some procedures, a mux-like process has to select 2 31-bits long words out of 12 of the same size. Everything works fine, I need to run the design @ 40 MHz and I have no problems. What I would like to do now is to have a 31 bits wide output bus and to output the 2 selected words in a single 25 ns period, sequentially. Like running the output @ 80 MHz, or like using output registers working on both rising and falling edge of the 40 MHz clock. What I would like to do is to achieve this result not having DDR support on IO buffers, nor a PLL to generate the 80 MHz clock, nor feeding the FPGA with a 80 MHz clock and dividing it inside to get the 40 MHz. The first two because of the chip I already have (no DDR, no PLL), the latter because in working conditions I only have 40 MHz on the board. I would like to avoid an external PLL, if I'll find no solutions I'll switch to a chip with the PLL inside. So, wishing to do it in the present situation.... The only idea I got is to add, for each output bit, a 2 to 1 mux after the last registers (1 word with rising edge reg, the other one on falling edge), properly sincronized with the 40 MHz clock as the select signal, but some simulation showed me this is not so good, because it adds skew between buses signals, and bad glitches too. Probably a good manual placement would help. Can you have any idea to do this 2x serialization in these conditions? Thank you very much, Luigi from BolognaArticle: 55667
Ray- Yes, XST allows one to build an inferred module (m2_1.v, say) and then use synthesis attributes to RLOC/LOC it to a specified location. This is what I ended up doing, of course. I just didn't like the need to add another level of hierarchy (the m2_1.v) to the design. It's reasonable for Xilinx to want to 'trim the fat' and get rid of macros, it's just annoying because those macros constitute a very nice set of devices to use in a design. The primitives are a good start, but they did such a nice job of fleshing out the database with macros that I find it a shame to see them go. (as pre-fabricated blocks that don't need to be inferred) Now I just need to start building a library of these pre-fab macros as required. If only Xilinx would offer a 'contrib' library for folks like me to download and augment XST, it would be nice. Jake Ray Andraka <ray@andraka.com> wrote in message news:<3EC2648A.5BC3BC67@andraka.com>... > With synplify you can use the xc_map attribute to essentially do what fmaps used to do. To do so, the > inferred M2_1 has to be in a separate component so that you can put an RLOC on the component instance. I > pasted in the 2:1 mux from our fmap_logic.vhd file at the bottom of this post. I'm not sure if XST has > a similar attribute or not. That said, as long as you have only one layer of logic between flip-flops, > the placer should put the LUT in the slice with the flip-flop so you should be able to just place the > flip-flop and let the placer do the rest. Another option is to write a boolean string parser that > converts a boolean string to a LUT INIT= string which you then put on both the LUT INIT generic and the > attribute (synplify will now read the generic and generate the attribute automatically, I don't believe > XST does that yet). > > --FMAP'd 2:1 mux > library IEEE; > use IEEE.std_logic_1164.all; > > entity fmap_mux2 is > port ( d0,d1,s : in std_logic; > z : out std_logic); > end fmap_mux2; > architecture rtl of fmap_mux2 is > attribute xc_map : STRING; > attribute xc_map of rtl : architecture is "lut"; > attribute syn_hier: string; > attribute syn_hier of rtl:architecture is "hard"; > begin > z <= d0 when s='0' > else d1; > end rtl; > --------------------------------------------------------------------------------------------- > > > > Jake Janovetz wrote: > > > Pete, > > > > Yes, Synthesizers know how to construct carry chains, etc. However, > > Jake knows where the mux should go. When you infer a mux, you have > > little control over where it goes and its more difficult and less > > readable to attach an RLOC to that 'inferrence'. > > > > The place and route tools haven't gotten all that smart and, despite > > timing constraints, area_group placement constraints, etc, they still > > place something 5 CLBs away from where it should go! (and thus not > > making timing). I took a short hiatus from FPGAs and returned hoping > > that the rumors I'd heard about the tools were correct -- they had > > gotten smarter. Unfortunately, it appears they'd gotten just smart > > enough to make people believe they could rip away certain features but > > not smart enough to justify the absence of those features. > > > > It's really unfortunate, too, because structural HDL with those nice > > primitives is a tolerable alternative to the > > worst-schematic-entry-tool-ever, ECS. What amazes me is that ECS > > somehow knows how to build a M2_1 out of the real primitives so it > > seems Xilinx has some QA and maintenance over those blocks -- why not > > just HDL them and let XST use 'em? > > > > Cheers, > > Jake > > > > "Pete Dudley" <pete.dudley@comcast.net> wrote in message news:<Ax-dnSERrd0XVVyjXTWcqQ@comcast.com>... > > > Jake, > > > > > > I think you are right. XST no longer supports the direct instantiation of > > > the M2_1 primitive. The libraries guide states "For HDL, this design element > > > is inferred rather than instantiated". > > > > > > This is probably a good thing to avoid now anyway. Synthesizers know how to > > > construct carry chains and when to use block multipliers. Where I work we > > > have built up a library of synthesizable, parametized elements. This lets us > > > code in a structural style when we want but the library is architecture > > > independent so our code is portable except for proprietary elements like > > > block rams. > > > > > > There should really be a public domain library like this but I haven't found > > > one. > > > > > > -- > > > Pete Dudley > > > > > > Arroyo Grande Systems > > > > > > "Jake Janovetz" <jakespambox@yahoo.com> wrote in message > > > news:d6ad3144.0305132010.7e425ff1@posting.google.com... > > > > Folks- > > > > > > > > How does one instantiate the schematic primitives in XST -- or is this > > > > even possible now? Let's say I want a M2_1 (2-1 mux). The 'unisims' > > > > directory of the Foundation toolset doesn't include these > > > > 'primitives'. Rather, it includes things such as LUTs. > > > > > > > > Of course, I can instantiate a LUT with the proper init values, but it > > > > would go a long way in readability not to mention "error protection" > > > > to have the MUX available as a primitive. > > > > > > > > This goes for all the other less-primitive blocks such as ACC1(4/8/16) > > > > and so on. Are these just not available in XST as blocks? > > > > > > > > Jake > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 55668
You are looking for an optimization called "resource sharing" that all of the commercial synthesis tools have. john paul wrote: > hi > > i need some help on how to multiplex multipliers( and other inbuilt > resources) > used in different clock cycles, or if else statements.as in the > following code > where my synthesis tool uses 12 multipliers( where only 4 is > needed,the multipliers here are 14-bit multipliers).i am using xilinx > virtex-II xc2v2000 fpga and xilinx ISE 2.3 is the synthesis tool. > > if(sel="00") then > sin1<=signed(s)*signed(cosine3(z(5)/2)); > sin2<=signed(c)*signed(si3(z(5)/2)); > cos1<=signed(c)*signed(cosine3(z(5)/2)); > cos2<=signed(s)*signed(si3(z(5)/2)); > si<=si3(z(5)/2); > co<=cosine3(z(5)/2); > > > elsif(sel="01") then > > sin1<=signed(s)*signed(cosine2(z(5)/2)); > sin2<=signed(c)*signed(si2(z(5)/2)); > cos1<=signed(c)*signed(cosine2(z(5)/2)); > cos2<=signed(s)*signed(si2(z(5)/2)); > si<=si2(z(5)/2); > co<=cosine2(z(5)/2); > > else > sin1<=signed(s)*signed(cosine1(z(5)/2)); > sin2<=signed(c)*signed(si1(z(5)/2)); > cos1<=signed(c)*signed(cosine1(z(5)/2)); > cos2<=signed(s)*signed(si1(z(5)/2)); > si<=si1(z(5)/2); > co<=cosine1(z(5)/2); > > end if; > > do let me know of any suggestions. > thanks > john >Article: 55669
If you're pushing the technology, the aftermarket synthesizer MAY help. Don't expect miracles. If you're not bumping into Fmax limits, use XST. In a recent (low/medium volume) design, it was cheaper to get the faster/bigger parts than to buy/rent the better synthesizer. $.02, SH On 14 May 2003 01:45:26 -0700, yuhaiwen@hotmail.com (Yu Haiwen) wrote: >Hi, Folks > >I'm doing design with Xilinx Virtex-II, and already have Xilinx ISE >5.1i. The pack has its own synthesizer: XST. I've never used it before >and know little about its performance. > >My question is whether it's worth for me to buy another third party >synthesizer such as synplify or FPGA Compiler. They seem more powerful >yet cost a lot. > >Can you give me any advice or comparison of these tools? > >Thanks and Best RegardsArticle: 55670
Hal Murray wrote: > . > How about metastability? Find anything in the data sheet to cover > that? Seen any numbers at other than "typical" conditions? Was > Peter's lab "typical"? > As reported and documented, I varied Vcc from 1.35 to 1.65 V ( plus/minus 10%) which changed the MTBF by a factor of up to 15. That gives a good indication of worst-case sensitivity. Even the worst-case numbers were better than excellent, so I saw no reason to go any further. Peter AlfkeArticle: 55671
Pick one, and use it consistently in a design. Makes it tougher to meet timing otherwise. The time you get burned is when you mix them. I always forget which one is which, but I prefer the one where the outputs come directly from the flops. And yes, it's a -personal- bias. $.02, SH On Thu, 15 May 2003 14:27:12 +0530, "LIJO" <lijo_eceNOSPAM@hotmail.com> wrote: >hi all, >can anyone tell me which state machine is good (Moore or Mealy).. Why? > >rgds, >Article: 55672
Jim Granville wrote: > > Interesting that IC's tend to have 130'C or 150'C Tj max, > whilst PowerMOSFETS often have Tj of 175'C > Silicon is one tough material ! The 125 or even 150 degree limit is more a plastic package issue than a silicon issue. I have helped down-hole ( oil-drilling) applications where our chips functioned (with relaxed performance) for many weeks at 175 degree ambient, and the user was pushing for 200 degrees. They used Xilinx FPGAs, Z80 uPs, SRAMs and even some analog stuff "down there". This worked, but we never guaranteed it. We ship millions of parts, each with hundreds of guaranteed parameters, often into demanding applications where any failure is unacceptable, therefore we have to be conservative. That's why our specs are worded the way they are. Peter Alfke, Xilinx ApplicationsArticle: 55673
Spam Hater <spam_hater_7@email.com> wrote in news:jve7cvgldg4va3thk6pbubq18rjuh07van@4ax.com: > I always forget which one is which, but I prefer the one where the > outputs come directly from the flops. And yes, it's a -personal- > bias. That's true of a correct implementation of either model. In a Mealy machine, the output at time t+1 is a function of both the current state at time t and the input at time t. In a Moore machine, the output is a function of the current state only. Some people implement Mealy machines sloppily, with the output being a *combinatorial* function of the current state and the input, but that's not an inherent characteristic of the model.Article: 55674
LIJO wrote: > can anyone tell me which state machine is good (Moore or Mealy) If you synchronize all inputs to the machine, take your pick. It's all good. Mealy has fewer bubble but busier arrows. For a given Mealy description, you can make a Moore description that generates the same hardware, so there's no difference in cost except for ink to draw bubbles. A synchronous hdl process is a superset of these models. -- Mike Treseler
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