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Hi i'm looking for the orcad library and toolchain that lets palasm handle Orcad
netlists
Anyone ?
regards
vincent
--------------------------------------------------------------
Vincent Himpe
/////
Internet : O *)
vincent.himpe@ping.be /
vi_himpe@mietec.be \__/
Fido :
2:291/1912.8
http://www.ping.be/~ping0751
--------------------------------------------------------------
Article: 1426Does anyone have a XNF (XC2018 device) to either ABEL or some other PLD language program that I can use? Let me know. Thanks, Norm AdreArticle: 1427
In article <3s6c32$302$1@mhade.production.compuserve.com>, Uwe Kremmin <100114.2166@CompuServe.COM> writes: |> In case you have access to CompuServe and would like to use |> AMD's MACHs: |> |> Go MAGNA, section "Design & Elektronik". There you find MACHXL |> 2.0 including docu and download softare for Windows |> for FREEEEEE! Is this available on an ftp site somewhere? Thanks -- Scott ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Scott Gargash Email: scott@plab.dmll.cornell.edu 009 Morrill Hall Phone (607) 255-0708 Cornell University Consultant/Advisor Ithaca, NY 14853 DMLL - Phonetics LaboratoryArticle: 1428
>>>> Mr. Irani, You can get the PREP certified data in the PREP homepages: www.prep.org. We try to make the data available as soon as certificatinos are achieved. There are no "rounds" of benchmarking or certifications. Vendors make submissions to the PREP verification and certification process whenever they wish. New data is being posted quite frequently. If you are a subscriber you can get regular hard copies of the data. It takes a few weeks to independently verify the data and have the PREP Steering Committee certify it. Your question about PREP being political is very interesting. I very much like your comments about this and any other PREP matter. At this point, PREP has been working on making test benches available for the 9 PREP benchmarks and new circuits that are much larger "real" applications. You will find information on this and postings of developments about evaluationg synthesis tools in the Synthesis Corner of www.prep.org. Happy browsing. Stan Baker President, PREP Corp.Article: 1429
I have recently been doing an analysis of Altera FLEX8000 CPLDs and am wondering about the usable gates numbers they include in their data sheets. I have talked to people at Altera about these numbers and they assure me these are based on circuits compiled with ASIC libraries then re-compiled and fitted into a FLEX800 device to see if they fit. The numbers they quote are supposed to be an average of such experiments so these numbers should be equivalent to those quoted by ASIC vendors. Essentially then, a design that fits into a 12 000 gate ASIC should fit into an EPF81188 which is supposed to have 12 000 usable gates. I decided to do my own experiment with a small FIFO I designed. I compiled it in design_compiler from Synopsys and pointed to a TI library (TGB2000). I obtained a count of 1487 gates. I then used the same RTL, synthesized in the exactly the same way but pointed to Altera libraries instead then pulled the EDIF file into MAX+PLUSII and mapped to an EPF81188 and got a utilization of 22%. Based on 12 000 gates, this is 2640 gates which is much higher than the 1487 gates I got with an ASIC library. I would be interested to know whether anybody has some insight and experience with the usable gates numbers quoted by Altera and other PLD vendors.Article: 1430
What does the PLDMAP library "symbol" do for you in programming Xilinx FPGA's? It appears to give you some level of control over the placement and routing of your design. On the other hand, it places restrictions on the PPR (place&route) program that might hinder optimization. I don't desire to get into hand placing each gate if a computer program can do it for me. I notice the Xilinx examples don't use PLDMAP, but a couple of big FPGA's done by an outside contractor for us assigned every gate and flip-flop to a CLB using CLBMAP's. What's the best deal here? David J. StarrArticle: 1431
Michael J. Wirthlin (wirthlim@fpga.ee.byu.edu) wrote: : |> >In article <1995Jun9.034024.4769@super.org>, : |> >Steve Casselman <sc@vcc.com> wrote: : |> >>We are designing a low cost ISA board for reconfigurable : |> >>computing/prototype development and would like to have : |> >>everyones thoughts on the subject like: : |> >> << stuff deleted >> : It seems to me that there are plenty of boards out there already with one or : only a couple FPGAs. As has been said earlier in this newsgroup, what we really : need is low cost tools. There has been some discussion on the one-FPGA board << stuff deleted >> : - Mike : -- : Michael J. Wirthlin : Brigham Young University - Electrical Engineering Department : Reconfigurable Logic Laboratory (801) 378-7206 How many people out there would be willing to put some time and effort into a project to develop good solid tools, perhaps something akin the the FSF ( gnu stuff). I personally would LOVE to see a suite of good solid front end tools that interfaced to various backends depending on what FPGA/CPLD/etc that one choose to use. I realise getting the programming information for the backends might take some doing, however.. the front end we can get started on now. I am more than willing to put some effort into programming and organizing such a project, if I can get a few other people (at least) willing to spend some time at it. Jonathan Smith http://red-branch.mit.edu/~jsmith/alpha/alpha.html (if your bored take a look at it)Article: 1432
Altera's MAX+PLUS II software can read an XNF file in directly. That should be as quick an easy as possible.Article: 1433
scott@fire.dmll.cornell.edu (Scott Gargash) writes:
>In article <3s6c32$302$1@mhade.production.compuserve.com>, Uwe Kremmin <100114.2166@CompuServe.COM> writes:
>|> In case you have access to CompuServe and would like to use
>|> AMD's MACHs:
>|>
>|> Go MAGNA, section "Design & Elektronik". There you find MACHXL
>|> 2.0 including docu and download softare for Windows
>|> for FREEEEEE!
>Is this available on an ftp site somewhere? Thanks
Try:
ftp.fh-wolfenbuettel.de: /pub2/Magazine/elrad/060/MXL*
MXL_20_1.LZH 851665 01.12.94 [0046] Mach XL 2.0, Disk 1 von 4
MXL_20_2.LZH 1081419 01.12.94 [0045] Mach XL 2.0, Disk 2 von 4
MXL_20_3.LZH 785560 01.12.94 [0043] Mach XL 2.0, Disk 3 von 4
MXLDOCV2.ZIP 1003384 01.12.94 [0054] Mach XL 2.0, Handbuecher im
Winword-Format, Disk 4 von 4
Ulrich.
--
Ulrich Hack
Amyastrasse 22, D-52066 Aachen, Germany
phone: +49 241 603184 FAX: +49 241 603042
EMail: uh@pool.informatik.rwth-aachen.de
Article: 1434
David J Starr (dstarr@world.std.com) wrote:
: What does the PLDMAP library "symbol" do for you in programming Xilinx
: FPGA's? ... I notice the Xilinx examples don't use PLDMAP, but a couple of
: big FPGA's done by an outside contractor for us assigned every gate and
: flip-flop to a CLB using CLBMAP's. What's the best deal here?
It gives control over the grouping of gates into Xilinx CLBs. Opinions vary on
the value of CLBMAPs, you MAY see a benefit for
1) Chip inputs direct to CLB where you want to use DI pin to minimise Tsu.
2) High clock rates (E.g. >=20 MHz for 3000-6).
3) Tightly packed chips with >90% CLB utilization.
Otherwise forget it, ppr / xnfmap does a good enough job.
Much more important than CLBMAPs is to include redundant gates wherever
necessary to get the logic partitiond efficiently into CLBs. XACT tools do not
duplicate gates (inverters excepted) even when this saves CLBs and delay
overall.
N.B. 1) For big FPGAs (especially XC4025) the automated tools may need help
with _placement_. CLBMAPs may be used to control placement, but you can
also attach location properties to gates or to hierarchical blocks.
Contact Xilinx for advice.
Article: 1435Hi, I'm working on a new design and would appreciate some feed- back from experienced FPGA designers. I want to use a RAM based FPGA because I feel the design will change over time (more features integrated into h/w). Has anyone had experience with the Atmel AT6005 part? -- Dick_Ginther@Develcon.comArticle: 1436
Hi: I am interested in FPGA partitioning, especially Xilinx 3000/4000 series. Everybody knows that the interchip delay is much longer than the delay between CLBs. But what's the approximate order? Thanks. -- =============================== Hsien-Ho Chuang eea80593@yankees.ee.nctu.edu.tw ===============================Article: 1437
Michael J. Wirthlin (wirthlim@fpga.ee.byu.edu) wrote: : |> Something : |> similar to TI's $99.00 TMS320C5x development kit... : It seems to me that there are plenty of boards out there already : with one or only a couple FPGAs. Is there a list of these boards anywhere? -- ------------------------------------------------------------- Will Ware <wware@world.std.com> web - http://world.std.com/~wware/ PGP fingerprint 45A8 722C D149 10CC F0CF 48FB 93BF 7289 "Government is not reason. It is not eloquence. It is a force. LikeArticle: 1438
Your FIFO probably has a high % FFs to gates. Try something with a more balanced mix. --- - Bill Wolf, Raleigh NC - My opinions, NOT my employer'sArticle: 1439
|> How many people out there would be willing to put some time and effort into |> a project to develop good solid tools, perhaps something akin the the FSF ( |> gnu stuff). I personally would LOVE to see a suite of good solid front end |> tools that interfaced to various backends depending on what FPGA/CPLD/etc |> that one choose to use. |> I think this is a great idea. I do agree that it would take some work. It seems to me that there are enough public domain tools currently available (schematic editors, simple optimizers, netlist converters, etc.) that could be used for FPGAs (I do know a few people who do this). Assuming you have the back end tools (place&route, bitstream generation), you could integrate a suite of other available tools to any FPGA. |> I realise getting the programming information for the backends might take |> some doing, however.. the front end we can get started on now. This is the main problem with good *free* tools. This newsgroup has already discussed the reasons why FPGA/PLD vendors do not make the back-end programming information available. Perhaps some of the hardware vendors will be willing to sell the back end tools at a significantly reduced price (i.e. sell the bitstream generation program at a nominal cost) in order to maintain control of the proprietary information, yet allow hobbiests to use the tools. If anybody knows whether or not this is done now, let me know. It would be nice if some vendor could allow free access to back-end tools (with no support, of course). The problem facing such a project is both high cost of design-entry tools (i.e. schematic entry, sythensis, etc.) and the highly sensitive nature of the FPGA back-end information. These problems can be solved by 1) integrating existing free tools and 2) obtaining low-cost access to FPGA back-end tools. #1 is a lot easier than #2. |> |> I am more than willing to put some effort into programming and organizing |> such a project, if I can get a few other people (at least) willing to spend |> some time at it. |> |> Jonathan Smith |> |> http://red-branch.mit.edu/~jsmith/alpha/alpha.html (if your bored take a look |> at it) -- Michael J. Wirthlin Brigham Young University - Electrical Engineering Department Reconfigurable Logic Laboratory (801) 378-7206Article: 1440
>>>>> "Will" == Will Ware <wware@world.std.com> writes:
In article <DAL7Az.LAB@world.std.com> wware@world.std.com (Will Ware) writes:
Will> Michael J. Wirthlin (wirthlim@fpga.ee.byu.edu) wrote: : |>
Will> Something : |> similar to TI's $99.00 TMS320C5x development
Will> kit... : It seems to me that there are plenty of boards out
Will> there already : with one or only a couple FPGAs.
Will> Is there a list of these boards anywhere? --
Sure. Look at our web page: http://splish.ee.byu.edu. In the
links to related WWW sites is a pointer to Steve Guccione's
list of FPGA computing machines. Steve has compiled a nice
list. Have a look see.
--
Brad L. Hutchings - (801) 378-2667 - hutch@ee.byu.edu
Brigham Young University - Electrical Eng. Dept. - 459 CB - Provo, UT 84602
Reconfigurable Logic Laboratory
Article: 1441
CALL FOR OPINIONS FOR THE 4TH ANNUAL ESNUG/DAC AWARDS!
------------------------------------------------------
Heads up! This is a call for EDA user opinions about what they saw
at this year's DAC in San Francisco last week for the 4th Annual ESNUG
DAC Review & Awards. Tell me what you thought was hot, what you thought
was not and WHY. What was your agenda at this year's DAC? What was the
biggest lie you had told you? What was the best party? Worst party?
Best freebie? Cheapest freebie? What tool caught your eye but cost way
too much? What tool are you going to buy right away? What bit of
surprizing gossip did you hear? Who had the best exhibit floor show?
What was the best/worst/sleepyest panel you saw?
AS ALWAYS, YOUR RESPONSE TO THIS WILL BE KEPT ANONYMOUS AND WILL ONLY
BE USED FOR AWARDS PURPOSES. Please! Be specific when you write; also
try to answer the "why" as much as "who", "what" and "where"!
I thank you for your input; you'll see the awards write-up shortly!
- John Cooley
Part Time EDA Consumer Advocate
Full Time ASIC, FPGA & EDA Design Consultant
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 3443 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 1442Hi! Everybody, we are now using the Xilinx FPGA XC4000 to implement a design. There are InOut port mode that we use and this don't work when we run the xmake command. Can anybody tell me what's the problem ? By the way, how can the InOut mode be used in the Xilinx FPGA ? We use the VHDL to describe the design.Article: 1443
> l93in@cis.nctu.edu.tw (Feng-Chen Chang) writes: > Hi! Everybody, we are now using the Xilinx > FPGA XC4000 to implement a design. > There are InOut port mode that > we use and this don't work > when we run the xmake command. > Can anybody tell me > what's the problem ? > By the way, how can the InOut > mode be used in the Xilinx FPGA ? > We use the VHDL to describe the design. > Verify that you understand the polarity of the tri-state control pin on the I/O pad's IOB. The Xilinx "data book" [at least one vintage] isn't very clear on which level turns the output driver off. If you have the polarity correct, then zero in on at least one pin by bringing the "outgoing" signal to an external pin (not through a three-state IOB), and bring the three-state control signal to another external pin, and verify that the signals are doing the right thing. You should be able to resolve this problem in short order. Bob Elkind, Videotek ************************************************************************** Bob Elkind email:videotek@rain.com CIS:72022,21 Videotek NorthWest Design Centre PO Box 5609 Beaverton, OR 97006-0609 voice/fax: 503.648.7532(w) cell:503.709.1985 home:503.359.4903Article: 1444
dstarr@world.std.com wrote: > > What does the PLDMAP library "symbol" do for you in programming Xilinx >FPGA's? It appears to give you some level of control over the placement >and routing of your design. On the other hand, it places restrictions >on the PPR (place&route) program that might hinder optimization. I >don't desire to get into hand placing each gate if a computer program can >do it for me. I notice the Xilinx examples don't use PLDMAP, but a couple of >big FPGA's done by an outside contractor for us assigned every gate and >flip-flop to a CLB using CLBMAP's. What's the best deal here? >David J. Starr Here we see the difference between the way things are really done, and the imaginary world that marketing would like to see. I have never done a Xilinx design that didn't require a lot of hand mapping, placing, and routing. It's nice that they have all these automatic tools that work well with slow, simple designs, but it sucks that these are provided instead of a decent floor-planning and interactive routing/layout tool. (Until release 5, it wasn't even possible to do re-entrant routing on 4000 parts. This shows how much the marketing folks bought into the "automatic" dogma.) CLBMAPS, FMAPS, and HMAPS are used for: Making obvious mapping optimizations that the software misses. Allowing names to be assigned that don't get mangled by the software. These are necessary for placement constraints to work well.Article: 1445
Chuang Hsien-Ho (eea80593@rockys.EE.NCTU.edu.tw) wrote:
: I am interested in FPGA partitioning, especially Xilinx 3000/4000 series.
: Everybody knows that the interchip delay is much longer than the delay
: between CLBs. But what's the approximate order?
(While awaiting completion of a crucial simulation run)
A very rough estimate is >= 3 to 1 assuming:
XC3100A-3
outputs configured as combinatorial
outputs configured for fast slew-rate
zero allowance for PCA track delay.
CLB to CLB metal delay = 4.4 ns (my estimate of what's achieveable in a
fairly full designs)
IOB O to PAD + PAD to IOB I delay = 5.5 ns (from databook)
My calculation is:
(metal delay) : (metal delay) + (IOB O to I delay) + (track delay) + (metal delay)
ie. 4.4 ns : (4.4 + 5.5 + 0 + 4.4) ns
Of course this is optimistic, it's not wise to use lots of fast slew-rate
outputs and track delay is usually significant.
(My simulation just completed. Success!)
Article: 1446
SJ Research designs, develops and markets ATM switches. We have been
selling low-end ATM systems for the past four years and have to date
sold over 3000 ATM switches.
For the past two years we have been specializing in "Access Switches"
to provide broadband ATM connections to residential and small business
users. Typically our switches will be installed in street cabinets.
The company is run in a very open way; employees are encouraged to
understand the wider issues of management, including the financial
figures.
We are looking for a number of engineers, hardware and software
to join our design team. You will have the opportunity to make
a major contribution to the design of our switch products at
every level from overall architecture to production engineering
and field testing.
Experience in any of the following areas would be relevant:
Development environments:
VHDL
C, C++
ARM Assembler
Viewlogic
FPGAs
ASICs
Design experience:
ATM switches or software
Telecomms hardware or software
CATV technology
RF Analog technology
SJ Research is a non-smoking environment.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Please mail, e-mail, or fax your resume today, indicating the position
you are applying for, and where you saw this notice.
Kim Spence-Jones (kim@sj.co.uk)
SJ Research Ltd.
J1 The Paddocks
347 Cherry Hinton Road
Cambridge CB1 4DH
England
Tel. +44-1223-416715
Fax. +44-1223-416440
For more information, contact jobs@sj.co.uk
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Glossary:
UK United Kingdom
ATM Asynchronous Transfer Mode -- the technology underlying
the so-called information superhighway
RBB Residential Broadband -- a sub-type of ATM to do with
providing wide-area broadband (i.e. fast) connections to
homes and small businesses.
VHDL, FPGA, ASIC ...if you don't know, don't apply :-)
--
John Cox (jc@sj.co.uk (work)/ jc@cix.compulink.co.uk (home))
Article: 1447
In <3se5hg$bc0@debbie.cc.nctu.edu.tw> l93in@cis.nctu.edu.tw (Feng-Chen Chang) writes:
> Hi! Everybody, we are now using the Xilinx
>FPGA XC4000 to implement a design.
>There are InOut port mode that
>we use and this don't work
>when we run the xmake command.
>Can anybody tell me
>what's the problem ?
>By the way, how can the InOut
>mode be used in the Xilinx FPGA ?
>We use the VHDL to describe the design.
You should avoid signal type INOUT all together.
To make bi-directional signals, split the signal
into separate IN and OUT signals within your VHDL
description. Then, combine then at the bidirectional
Pad component using a tristate output buffer and an
input buffer. Ill attempt to illustrate below.
You have to include an output enable in your design.
sig_out |-------|
--------------->| obuft |----->
|-------| |
out_en | | |-------|
-------->| |<---->| Bipad |
| |-------|
sig_in |-------| |
<---------------| ibuf |<----
|-------|
Good Luck,
Dave Lanza
--
David Lanza
dlanza@harris.com
Article: 1448The PREP benchmarks are available on the net at //www.techwin.org/prep/prep.html -tomArticle: 1449
In article <robc.801773455@appliedmicro.ns.ca> Rob Christopher, robc@appliedmicro.ns.ca writes: >Does anyone have any info on a low cost programmer that I can use on >Flex780 devices. If you have the Intel lead, or equivalent, it is not that difficult to come up with a circuit to program the chips in situe. _____________________________________________________________ Dr John Forrest Tel: +44-161-200-3315 Dept of Computation Fax: +44-161-200-3321 UMIST E-mail: jf@ap.co.umist.ac.uk MANCHESTER M60 1QD UK
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