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I used the ucf file to specify the load values using the INIT parameters. Do I need to do something else to put data in them at startup for the simulation? Thanks again! Adam Ray Andraka wrote: > Check to make sure they have valid data in them. You need to load them at > somepoint. Until they have valid data at the addresses you are reading you > will get 'x's out. > > Adam J. Elbirt wrote: > > > I'm using the embedded RAM within a Virtex chip and having some troubles > > with the post-route simulation. It seems that the RAM aren't "turned > > on" and all I get out of them is X's. Is there anything special that I > > need to do to access the data in the simulation? > > > > Thanks. > > > > Adam > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randrakaArticle: 15976
At Worcester Polytechnic Institute we use the Xilinx XChecker. Not sure what the price is but its pretty easy to use and we teach VHDL using the board for design implementation. Adam Kolaga Xiuhtecuhtli wrote: > What is a good eval board for a hobbyist? I'm talking > about the daydreamer sort of electronics fan. The kind > who wants to realize a CPU out of a FPGA. But actually > something easy on the wallet and ego...Article: 15977
Hi Adam, I think you will have to do an INIT of the RAM via a NCF file rather than a ucf file. A ucf file won't initialize the block ram currently. Best Regards Terry "Adam J. Elbirt" wrote: > > I'm using the embedded RAM within a Virtex chip and having some troubles > with the post-route simulation. It seems that the RAM aren't "turned > on" and all I get out of them is X's. Is there anything special that I > need to do to access the data in the simulation? > > Thanks. > > AdamArticle: 15978
If you are talking about a VHDL simulation, putting this in the header
deals with the _pre-synthesis_ situation, which was not what you asked
about :)
--synthesis translate_off
library unisim;
use unisim.vcomponents.all;
--synthesis translate_on
The unisim model of a Virtex RAM has all-zero INITs as generics. This
also applies to the post-P&R simprim library, which will be automatically
called out by the Xilinx tools,
AFAIK, what happens in the post-synthesis simulation case depends on the
synthesis vendor.
Of course, there is an 90% or greater chance that you were not asking
about a VHDL simulation at all...
--
Simon
In article <37212AC6.D079B9D7@nac.net>,
"Adam J. Elbirt" <aelbirt@nac.net> wrote:
> I used the ucf file to specify the load values using the INIT parameters. Do
I
> need to do something else to put data in them at startup for the simulation?
>
> Thanks again!
>
> Adam
>
> Ray Andraka wrote:
>
> > Check to make sure they have valid data in them. You need to load them at
> > somepoint. Until they have valid data at the addresses you are reading you
> > will get 'x's out.
> >
> > Adam J. Elbirt wrote:
> >
> > > I'm using the embedded RAM within a Virtex chip and having some troubles
> > > with the post-route simulation. It seems that the RAM aren't "turned
> > > on" and all I get out of them is X's. Is there anything special that I
> > > need to do to access the data in the simulation?
> > >
> > > Thanks.
> > >
> > > Adam
> >
> > --
> > -Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email randraka@ids.net
> > http://users.ids.net/~randraka
>
>
-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own
Article: 15979Hello. I'm in the design phase of a new electronic card, and at present evaluating FPGA circuit. I'm familiar with the xilinx 3xxx series, but consider to use the Spartan series, XC520, XC530 or XC540. Any experience whith pittfals or general problems using this device(es)? (Design information: registers, buffers and counters, totally about 300 CLB. CPU buss interface to an Am186ES) Regards Jon S. Dev. engineer Thomson-CSF Nortech asArticle: 15980
Terry (and all who are interested), I am doing a post-route VHDL simulation. The ucf was used to init the RAM during layout. I was under the impression that an ncf file is the same as a ucf file - no? Adam zule wrote: > Hi Adam, > > I think you will have to do an INIT of the RAM via a NCF file rather > than a ucf file. A ucf file won't initialize the block ram currently. > > Best Regards > Terry > > "Adam J. Elbirt" wrote: > > > > I'm using the embedded RAM within a Virtex chip and having some troubles > > with the post-route simulation. It seems that the RAM aren't "turned > > on" and all I get out of them is X's. Is there anything special that I > > need to do to access the data in the simulation? > > > > Thanks. > > > > AdamArticle: 15981
> one tip: if you can, do a timing simulation, since this > is the only way to check that your constraints are right, and that > they work. Would you please elaborate on that? I do full coverage TIMESPECS (the tools tell me all my paths are covered), and only do static timing analysis, which the tools tell me if I make timing or not. I only do unit delay simulations. I have never had a problem with timing at all that couldn't be traced down to a mistake in the TIMESPEC. If I can't get my TIMESPECs right, then how can I be sure I got my timing simulation stimulus correct? AustinArticle: 15982
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Manish Mahajan
3500, Granada Ave. #351
Santa Clara, California 95051
E-mail:manishm@cyberspace.org, m_a_n_i_s_h_m@hotmail.com
Preferred E-mail : m_a_n_i_s_h_m@hotmail.com
URL address:http://www.cyberspace.org/~manishm/res
Phone : (408)246-8952 (W)
(408)261-6775 Ext. 14 (W)
______________________________________________________________________
Experience Summary: 6 years of experience in the areas of hardware
design including FPGA's based on PCI Bus, VHDL/Verilog synthesis using
Synopsys DC, working knowledge of HDL simulation and analysis,
advanced ASIC design, hands on experience taking ASIC design through to
tape out, floor planning tools, testability and ASIC testing.
Areas of Interest: Hardware Digital design, Chip level design and
verification, Hardware and software co-design of ASIC's and
reconfigurable FPGA's based on USB, IEE1394 (firewire), ATM,
networking chipset and synthesis using Synopsys-DC software.
Education: Bachelors Degree in Electronics & Telecommunication
Engineering in 1994 from V.R.C.E Nagpur India
http://www.ag.uiuc.edu/~basolem/vrce
Computer Skills :
Design Tools/ Languages
o SYNOPSYS (VHDL Compiler, HDL Compiler, Design Compiler, Design
Analyzer, VSS, Prime Time)
o Xilinx design tools (XACT, Floorplanner)
o Viewlogic tools (Proseries, Workview Office, Powerview, VCS, Motive)
o Verilog and PLI (Programming language interface), VHDL
o Mentor Graphics (Modeltech VHDL Simulator(MTI), Exemplar Synthesis
tools Galelio)
o LaTeX, FrameMaker, PageMaker
Programming Languages: VHDL, Verilog, Shell scripts, C, Perl.
Operating Systems: DOS, UNIX (SUN OS, HP-UX), X-Windows, MS-Windows
98/NT and Macintosh Platforms.
Project Details :
-- Project done for adding test vectors for getting high testablity
coverage for PCI to SCSI chipset ASIC.
This was for Adaptec as an employee from 08/98 till date
The design for the PCI to SCSI chip set did not have the in-built
SCAN so multiple test vectors were written to find out the faults in
the design. The fault coverage was low (about 78% of the total chip)
so in order to improve on the fault coverage to 98% more test vectors
were written in verilog and the whole chip was run on the Zycad fault
analyzer to detect the fault coverage, this run for detection was
running for about 2 months. It involved extensive simulation of the
chip as a whole and writing of test vectors to detect the undetected
and untested faults in the chip.
-- Project involving design and implementation of a specific command
channel block in PCI chipset in ASIC.
This project was done for Adaptec as an Employee from 10/97 to 08/98
In this a block for COMMAND CHANNEL was designed and implemented in
verilog. The basic functionality of the block is to transfer the data
between the PCI block to the internal or external scsi command block.
This block had three state machines which controlled the ram modules
and the registers which were read/write or read only registers for
this particular block. Later on, the synthesis for this block was done
and then SCAN was inserted in the block during synthesis in Synopsys
DC. Also the check on the functionality of the block was done using
different test cases for the different internal modules. Then the
timing analysis of the design was done using the Synopsys Prime-time
and the timing check was performed and corrected.
-- Project done for design, verification and testing of a particular
block for a PCI to SCSI chipset ASIC.
This project was done for Adaptec as an Employee from 04/97 to 10/97
In this project the design, implementation, verification and testing
of the PCI Power Management requirements for the PCI bus was done.
The chipset did not have the Power Management features for PCI bus so
the addition registers and handling of different power levels by the
chipset was implemented and tested on the board. A preliminary test
was done by doing a cut and jump by the Focussed Ion beam machine to
test out the functionality. Later on most of the work was done for
getting the fault coverage of the chipset on the tester. Due to lack
of SCAN in the design it was required to have a lot of test vectors
to detect the fults in the actual silicon, which is required because
of large volume of silicon after finalization of the design.
-- Project for a PCI to PCI bridge between Intel Pentium processor
and the Power PC (Mac):
This Project was done at Comit systems as an Technical Project Lead of
Comit systems for company Reply Corporation which was later on merged
into Radius Inc. from 10/96 to 04/97
In this project the main idea for the board design was to have a DOS
on the Macintosh platform. In this we were developing the PCI to PCI
bus bridge between PowerPC and Pentium. The design was done using
WorkView Office. The final design was targeted onto the Xilinx FPGA
XC4013E. The PC side PCI bus has to communicate with the MAC side PCI
bus through the logic that was put on the FPGA on the board. For this
the PCI macro was used to communicate with the PCI bus on either side.
The logic was put on two Xilinx devices the XC4013E, and the logic
between the two chips was designed and put on the Xilinx devices along
with the PCI macro on either side. Basically, the transfer took place
through the memory cycle burst and non-burst cycles for the data to be
read as well as written to the memory by the PCI bus on the oppposite
side. Along with these data transfer the cycles could be started on
the PCI bus to read some status registers and to write some command
registers inside the Xilinx devices. The configuration of the device
could be done on the PCI core by starting the configuration cycles
after every starting reset condition of the devices. Finally, after
testing of the design on FPGA's testability was inseted and the
design was targeted to ASIC.
-- Project done for verification of the PCI bus functionality of a an
FPGA :
This project was done at Comit Systems as an employee of Comit,
Technical Project Lead for Altera Corporation between 06/96 to 10/96.
For another Altera based FPGA which supported the PCI bus
functionality the test cases for verifying the full functionality of
the PCI logic on FPGA was done. The testbench cointained the Master
and the Slave functionality inside the testbench. The arbiter was also
included inside the testbench. This testbench was written in VHDL and
simulated using the Modeltech simulator on PC. The brief description
of the testbench is as follows: the master could be made to start a
cycle by giving it a start signal, then it went and read the cycle to
be performed in and as indicated by a command file. The target could
be configured and would respond on a hit on any of it's base address
registers. This was used to find out if the chip was PCI 2.1 & 2.2
compliant.
-- DRAM controller for Intel Processor :
This project was done for Unisys Corporation with Comit Systems from
02/96 to 06/96 as an employee of Comit, Technical Project Lead.
An FPGA-based DRAM-Controller for the Intel 486 Processor was
designed. This device interfaces between the CPU, the DMA and the
DRAM. The design was targeted to the Xilinx FPGA 4008E device and the
design was done using the Xilinx tools on the MS-Windows platform.
This project done was the design of an FPGA as a DRAM-Controller for
the Intel 486 processor. The design was targeted to the Xilinx FPGA
4008E device and the design was done using the Xilinx tool from
Viewlogic on the MS-Windows platform. The Xilinx device interfaces
between the cpu I486, the DMA and the DRAM. This design supports
32MB/16MB of memory (DRAM) which can be used by the i486 processor on
the mother-board. The design was targeted to a Xilinx chip (the
XC4008E device) and was simulated using PROSIM. The design once
complete, the gate level design on the Xilinx was converted to Verilog
and was simulated using the VCS simulator from Viewlogic. The test
cases were hand written in Verilog and then were used to test the DRAM
Controller FPGA. One pass was also given for it for optimisation of
the timing on the Xilinx chip by synthesysing the desgin entered in
schematic using the Synopsys software. The timing were marginally
improved because of the few logic optimisations done by the Synopsys
software. The final design went into production as an ASIC after
testability was inserted.
-- PCI-DS Link Interface Card :
This project was done for C-DAC between 04/95 to 02/96 as an employee
of C-DAC Pune, as Hardware Engineer
The card was basically meant for converting the serial data to and
from DS-Link to the parallel data on the PCI bus of Alpha chip. In
this a chip from AMCC S5933 is used to have a general purpose PCI bus
interface. The logic for the design has to be put on the Xilinx FPGA.
The modules of the design are being prototyped on Xilinx FPGA's and
the final design has to be a gate array chip. The complete modelling
was done in VHDL, SYNOPSYS synthesizer and simulator. In this the
data path logic from the AMCC S5933 and the DS-Link was written in
VHDL by me then tested using a behavioral test bench in VHDL and the
SYNOPSYS simulator. The synthesis of the state machine was done in
Design Analyzer from SYNOPSYS. In this along with the data path logic
there were also some Command and Status Registers for giving a
particular command to the chip and to read the status of the chip.
-- CCP (Complex Communication Processor) :
This project was done for C-DAC from 05/94 to 06/95 as an employee of
CDAC Pune, Hardware Engineer.
This project is on a Complex Communication Processor based chip, based
on DS-Link. The chip CCP, Communication Co-prosessor is a highly
functional communication interface from an SBus (as defined by SUN
Micro Systems) based node to a DS link (as defined by INMOS) based
communication network. CCP is based on the device C101, which is a
DS-link adapter from INMOS.
The CCP was being designed to reduce the software latency which is a
major bottleneck in MPP communication. It provides a flexible
interface to system programmers.
-- Microcontroller based image processing
College project work.
For this project a hardware board having the microcontroller chip 8251
was made and connected to PC through a RS232-C serial link. The
overheads of the communication were taken up by the hardware board and
the PC had to just transfer the data as and when required.
--------------06D34B24EA8FDC3F9369E82A--
Article: 15983I used the following line in one of my designs:NET "TENMHZ" PERIOD = 90.0 ; # commentthe "90.0" is in nanoseconds, it could have been "100.0" in this case, for a 10Mhz clock -**** Posted from RemarQ, http://www.remarq.com/?a ****- Search and Read Usenet Discussions in your Browser - FREE -Article: 15984
On Sat, 24 Apr 1999 00:18:07 -0400, "Adam J. Elbirt" <aelbirt@nac.net> wrote: >At Worcester Polytechnic Institute we use the Xilinx XChecker. Not sure >what the price is but its pretty easy to use and we teach VHDL using the >board for design implementation. Here's one web site that has a "design your own processor" FPGA eval board: http://www.tefbbs.com/spacetime/index.htm And this is the XESS eval board(s) at http://www.xess.com/FPGA/ And maybe this place: http://www.associatedpro.com/index.html >Kolaga Xiuhtecuhtli wrote: > >> What is a good eval board for a hobbyist? I'm talking >> about the daydreamer sort of electronics fan. The kind >> who wants to realize a CPU out of a FPGA. But actually >> something easy on the wallet and ego...Article: 15985
First, if you are initializing RAM via a constraints file, I think you need to use an NCF file, not a UCF file. A ucf file cannot specify the contents of RAM or ROM for 4K/spartan/Virtex parts. If this is the case, a post route simulation will not work, and the design will not have the proper initial values in the ram cells. You can verify this by looking at the LUTs in Epic. If you generate the memory by way of Logiblox or CORE gen, the memory model looks for a *.MIF file for the memory contents. The behavioral model uses this ascii file for theinitial contents, so no further initialization is needed. If you are doing a post route simulation from the routed design, the initialization is included in the LUTs in the netlist constructed by the xilinx router tools. These should simulate correctly. So the problem must be in a pre-route functional simulation using RAM primitives. You should be using the Unisim RAM primitives for VHDL. You can specify the initial values as a generic to pass it into the model. That requires the init values to be embedded in your HDL code. If you are using viewlogic simulation you can use the loadm to initialize contents of memory elements in the design. Hope this helps. Adam J. Elbirt wrote: > I used the ucf file to specify the load values using the INIT parameters. Do I > need to do something else to put data in them at startup for the simulation? > > Thanks again! > > Adam > > Ray Andraka wrote: > > > Check to make sure they have valid data in them. You need to load them at > > somepoint. Until they have valid data at the addresses you are reading you > > will get 'x's out. > > > > Adam J. Elbirt wrote: > > > > > I'm using the embedded RAM within a Virtex chip and having some troubles > > > with the post-route simulation. It seems that the RAM aren't "turned > > > on" and all I get out of them is X's. Is there anything special that I > > > need to do to access the data in the simulation? > > > > > > Thanks. > > > > > > Adam > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email randraka@ids.net > > http://users.ids.net/~randraka -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 15986
There is a list of boards at http://dmoz.org/Computers/Hardware/Programmable_Logic/FPGA/Boards/ If you find some more, feel free to add them --reto -- Opinions are mine and not those of my companyArticle: 15987
Have you applied a positive pulse on GSR at the beginning of the simulation? Adam J. Elbirt wrote: > I'm using the embedded RAM within a Virtex chip and having some troubles > with the post-route simulation. It seems that the RAM aren't "turned > on" and all I get out of them is X's. Is there anything special that I > need to do to access the data in the simulation? > > Thanks. > > AdamArticle: 15988
Check your Synopsys edif options on busses. You may want to brute-force it and bit blast the buses in Synopsys before edif. --Ross > I am using the VCC HotWorks board for the Xilinx XC6200 FPGA. I am > writing in VHDL and using Xilinx's XACTstep 6000 software to read an > EDIF file generated by Synopsys. For some reason, it keeps giving errors > for any blocks which have std_logic_vectors as inputs or outputs. Does > anyone know of any problems along these lines, and more importantly, any > solutions?Article: 15989
TM Associates will be presenting the course VHDL Introduction by Jim Lewis of SynthWorks Design, Inc. May 26-27 in Portland, OR. VHDL Introduction Understanding VHDL with highlights in design and test. Basic Level, 70% Lecture, 30% Labs by Jim Lewis of SynthWorks Design Inc. An introductory course that teaches VHDL constructs relevant to a hardware designer. Appropriate for design engineers who follow it with additional training or for support engineers who only need an overview of the language. Examples show how to apply the language to hardware design and test. Concepts presented in each section are reinforced with exercises and labs. For complete details of the course as well as a writeup on the instructor, visit our website: http://www.tm-associates.com. To enroll contact Tom Wille. ************************ Tom Wille TM Associates Training Specialists http://www.tm-associates.com 503-656-4457 503-656-4775 fax tw@tm-associates.com ************************ -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 How-to, hands-on VHDL training with a focus on hardware design and test. Learn VHDL from a designer's perspective with SynthWorks. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Article: 15990
mench@mench.com wrote: > > Don't do it (as someone else said). > Is this the rule (and written somewhere) of this newsgroup. My personal opinion is that I don't mind (and am very welcomed actually) to see any job posting as long as it is strongly related to the subject of the newsgroup. I think it is a very good way to pass the information from the job providers. I don't see any reason why opposing posting a job oppertunity here.Article: 15991
I tried using it about a month ago, excited to know that finally a web based tool is available. But gave up on it eventually. It gets constrained by the net speed and the browser settings at the time of submission of the file. Also, how do we simulate/synthesize the design that we obtain - the EDIF/DB file? We have to resort to using the tools that go with the CPLD/FPGA supplied by the manufacturer - Xilinx in this case. So what we get on the webfitter as an immediate validation of our HDL desc. is only a textual confirmation that it was indeed a fit. You donot have any GUI tool that validates the design on the web?? Thanks. WK In article <37211682.E74E9A50@xilinx.com>, Sanjeev Kwatra <sanjeev@xilinx.com> wrote: > The report has links to VHDL (or Verilog or EDIF, as required) netlist > and SDF file that you can click on to download. Alternatively you > can click on the "download" button to save a file called allfiles.zip > which contains all the relevant files created during implementation. > The report also has a link to the VHDL or Verilog models of > Xilinx primitives used in the implementation netlist. > > Sanjeev > > Richard Guerin wrote: > > > Using the WebFITTER tool, how would an individual obtain a back > > annotated VHDL netlist and SDF file for post-route > > simulation/verification ? > > -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 15992
Vincent Ma wrote: > mench@mench.com wrote: > > > > > Don't do it (as someone else said). > > > > Is this the rule (and written somewhere) of this newsgroup. My personal > opinion is that I don't mind (and am very welcomed actually) to see any > job posting as long as it is strongly related to the subject of the > newsgroup. I think it is a very good way to pass the information from the > job providers. I don't see any reason why opposing posting a job > oppertunity here. agreed - a posting about a relevant job seems reasonable and is a good way to communicate. and as long as it says "JOB:" or something like that in the header, one could choose whether to open it up or not. rkArticle: 15993
On Mon, 26 Apr 1999 10:23:53 -0700, Vincent Ma <vinma55@hotmail.com> wrote: >mench@mench.com wrote: >> Don't do it (as someone else said). > >Is this the rule (and written somewhere) of this newsgroup. My personal >opinion is that I don't mind (and am very welcomed actually) to see any >job posting as long as it is strongly related to the subject of the >newsgroup. I think it is a very good way to pass the information from the >job providers. I don't see any reason why opposing posting a job >oppertunity here. > (1) these newsgroups go out all over the world. how would you feel if your news feed was flooded by job advertisements from, say, shanghai? and why should they be interested in job advertisements from the US or the UK? (2) at any one time, there are probably several thousand worldwide job vacancies in the areas of fpgas, vhdl, and verilog. do you want all these job ads on your newsgroup? do you want to download them all just to discard them? (3) these are technical newsgroups, for the exchange of technical information. there are other newgroups for jobs wanted and jobs advertised. (4) these groups aren't moderated, so there's nothing to stop people posting job vacancies if they really want to. however, the groups would quickly become worthless if even a small fraction of all job vacancies were to be posted here. evanArticle: 15994
On 24 Apr 1999 18:36:28 GMT, "Austin Franklin" <austin@darkr9oom.com> wrote: >> one tip: if you can, do a timing simulation, since this >> is the only way to check that your constraints are right, and that >> they work. > >Would you please elaborate on that? I do full coverage TIMESPECS (the >tools tell me all my paths are covered), and only do static timing >analysis, which the tools tell me if I make timing or not. I only do unit >delay simulations. > >I have never had a problem with timing at all that couldn't be traced down >to a mistake in the TIMESPEC. If I can't get my TIMESPECs right, then how >can I be sure I got my timing simulation stimulus correct? there are 2 problems here - the first is, as you say, mistakes in the timespecs. this is a lot easier than it sounds. for example, there are cases, in a multiple clock design, where you have to individually timespec every path to a F/F with a FROM:TO, and you may have to repeat this for a lot of F/Fs. trce won't tell you if you've missed one of these paths. this particular problem is due to a 'feature' related to forward-tracing through a BUFG. however, whether or not this problem has been fixed, there are always cases in which trce will be unable to determine whether a path has been correctly covered - a multi-cycle exception, for example. in short, IMO, "100% coverage" doesn't mean either that all the paths have been covered, or that all the paths have been covered correctly. the second problem is simply that we have no guarantee that the timespecs are being correctly interpreted by the back end tools. this may sound facile, but i've already mentioned one problem above that has caused me a *lot* of aggravation. which leads to timing simulation. this is the only way to test your timespecs and the tool's interpretation of your timespecs (although, of course, a working timing simulation doesn't necessarily verify your timespecs, but at least the design is known to work). > If I can't get my TIMESPECs right, then how >can I be sure I got my timing simulation stimulus correct? if you've done a functional simulation, then you already have the stimulus. all you're lacking at this stage is some timing on the inputs, outputs, and clocks. this is a trivial addition to an existing functional test (for VHDL, anyway), and it's good practice to put this information into your functional test (so that both simulations have the same testbench). given that a timing simulation is so straightforward, and that it's the only way to check your specs and your tool, what reason can there be for *not* doing a timing simulation? evanArticle: 15995
I have ESP V4.21 and SDT V4 installed as a backup schematic CAD system. I also have PLD386 V2.01H. I have installed PLD and selected ESP V4 as the interface but ESP cannot see PLD386. The MERGEDAT operation fails with 'vendor file not found' for all design directories. I have even tried a manual installation. FIXDAT works fine but I cannot proceed from there. I'M STUCK! Any assistance would be most helpful. I need to get PLD386 setup for a contractor who will be starting on a project soon... Nino. -- ****************************************************** * Antonio (Nino) Benci * * Electronic Services Manager * * Monash University - Dept of Physics * * Wellington Rd, Clayton. 3168 * * Victoria, Australia. * * TEL - 61 3 9905 3649, FAX - 61 3 9905 3637 * * Mobile - 0414 764 763 (private and ah only) * * EMAIL - nino.benci@sci.monash.edu.au (work) * * - fleatech@excite.com (private) * * WWW - www.physics.monash.edu.au/ * ******************************************************Article: 15996
**********************************
APS EDA Newsletter Release Notice Q199
**********************************
The APS EDA Q199 Newsletter has been officially released.
The newsletter can be seen at:
http://www.associatedpro.com/Newsletter/1q99/nlq199.html
CONTENTS:
* A rework of a XILINX schematic based FIFO design in VHDL with C
control and Verification code.
* The APS-X240 FPGA Board with Ethernet control.
* Uart core and RS-232 drivers on the APS-X240
* Also a look at the X208 Bit Generator Application Core
* VHDL Topic: two's compliment numbers in VHDL
* A highly programmable PN Sequence Core in XILINX FPGAs.
Products Focus:
* Essential VHDL book now available with X240 examples
* Prism HDL editor now available
* ST-111 QPSK Direct Sequence Spread Spectrum Signal Generator from
SIGTEK
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Article: 15997ems@riverside-machines.com.NOSPAM wrote: > <snip> > > given that a timing simulation is so straightforward, and that it's > the only way to check your specs and your tool, what reason can there > be for *not* doing a timing simulation? > > evan I have to chime in on the side against timing sim. As a means for verifying timing I think it's far inferior to static timing analylis. I'll stop short of saying it's a waste of time, but 1) It's very vulnerable to the coverage of your test vectors, and 2) It's not always as straightforward as you imply. The back annotation path for Lucent's ORCA tools is basically broken, for example, and I've had problems in the past with Xilinx as well. Not to mention that that full timing simulations are very slow. The only time I ever bother with back-annotated FPGA simulation (post- synthesisis, post-map, or post-place & route) is to verify the implementation after each step to isolate a problem in the lab that brings the tools into question. I agree that it takes a lot of work to completely spec some designs, but you have to do that anyway. If a timing sim reveals a broken path the only way to fix it is to constrain the path correctly. Bob Sefton A grizzled veteran of the FPGA timing wars.Article: 15998
Hi all, I have to implement a Digital Phase Locked Loop in an FPGA. The center-frequency is in the order of KHz, but it has to be in lock over a few KHz. Does anyone has experience with that ? Or if you have doc's on that subject, let me know. Thanks john.troch@barco.comArticle: 15999
Ingmar Hohmann wrote: > Does anybody has instantiated a TDO pin for output with Exemplar ? Hello You a part of the answer in the LeonardoSpectrum Synthesis and Technology help book. This explain that you must define and instantiate the components bscan, tdo, tdi, tms, tck. Do not create any entity or architecture for these components. If you have to create one to create your vhdl file with a tool like Renoir, do not specify the bscan, tdo, tdi, tms, tck files in the input list for Leonardo. In the LeonardoSpectrum, specify to use the xilinx 4000 library. I use the LeonardoSpectrum Level 2 and I do by : go in the quick setup menu, put you mouse cursor above the file list, click the right button and choose set technology all xilinx 4000. I guess that with Level 3 you have a graphical interface to do this. This can be use to specify Leonardo to choose any special macro : adder, ram ... In the summary report, you will see in the component list that the origin of the bscan, tdo, tdi, tms and tck components is xilinx 4000. If the origin is your library or if they do not appear in the list, something completed wrong. Hope this helps, Michel Le Mer Gerpi sa (Xilinx Xpert) 3, rue du Bosphore Alma city 35000 Rennes (France) (02 99 51 17 18) http://www.xilinx.com/company/consultants/partdatabase/europedatabase/gerpi.htm
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