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Messages from 72800

Article: 72800
Subject: the global output enable pins of lattice ispxpld 5000mv
From: No This Rat <nothisrat@yahoo.com>
Date: Fri, 03 Sep 2004 00:13:17 +0800
Links: << >>  << T >>  << A >>
Hi,friends,
   I use a lattice ispXPLD 5512mv in my design, but i dont use the 
goe(global output enable) pins, how should I deal with it? pull down 
it?will it affect my design logic?
   In my design, there is a pci interface but I dont design the PAR 
logic, both perr and serr, how should I connect them? pull up? pull down 
or just leave them away?
   Thanks a lot!

Regards

Article: 72801
Subject: Re: the global output enable pins of lattice ispxpld 5000mv
From: mikeandmax@aol.com (Mikeandmax)
Date: 02 Sep 2004 16:28:07 GMT
Links: << >>  << T >>  << A >>
not this one wrote -

>Hi,friends,
>   I use a lattice ispXPLD 5512mv in my design, but i dont use the 
>goe(global output enable) pins, how should I deal with it? pull down 
>it?will it affect my design logic?

The GOE pins do not need to be terminated in your design.  If your design is
not specifically using them, the will not be connected to any of the I/O, and
the internal pullup in the I/O pad will prevent floats, etc.....

>   In my design, there is a pci interface but I dont design the PAR 
>logic, both perr and serr, how should I connect them? pull up? pull down 
>or just leave them away?

without more info on the design, I can only  provide a clue on this one - 
if perr or serr are active high, and you aren't using them, either tie the pin
low, or program the pulldown option for the pin, to keep inactive -

the 5K families all provide induvidual pullup/pulldown/bus hold/ none option
for pin configuration -

you might also give your local Lattice FAE a call, he/she would be happy to
help -
>   Thanks a lot!
>
>Regards
>
>
have a good day -
Mike Thomas
Lattice SFAE - Ny/NJ


Article: 72802
Subject: Re: EDK core wrapping and include files
From: "E.S." <emu@ecubics.com>
Date: Thu, 02 Sep 2004 10:33:25 -0600
Links: << >>  << T >>  << A >>
Antti Lukats wrote:

> "John Williams" <jwilliams@itee.uq.edu.au> wrote in message
> news:4131c785$0$27241$61ce578d@news.syd.swiftdsl.com.au...

>>Good plan!  I would love to see a wishbone -> opb bridge to get some of
>>that great opencores.org stuff into microblaze projects.
> 
> opencores stuff is actually being used in OPB/Microblaze systems at many
> places :)

Where ?



Article: 72803
Subject: Re: Spartan 3 Starter Kit and ISE WebPACK
From: Kroko <Kroko@nil.com>
Date: Thu, 02 Sep 2004 19:30:15 +0200
Links: << >>  << T >>  << A >>
On Wed, 01 Sep 2004 15:03:41 -0700, Shalin Sheth
<Shalin.Sheth@xilinx.com> wrote:

>Yes, you will be able to complete a VHDL design for the Spartan-3 
>Starter kit using the ISE Web Pack software.

Thats very good, that means i will buy it :-)

Is it only possible for a limited time, or is there no time limit ?
What I mean is, I don't want to use an evaluation version of some
software that costs me a lot to buy later when the evaluation period
is over ! And I need more that a few month to complete the project i
have in mind ....



Article: 72804
Subject: Re: The Effect of Pin Assginment
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Thu, 02 Sep 2004 18:27:30 GMT
Links: << >>  << T >>  << A >>
Take a step back and study the internal structure of the FPGA you are using.
Become familiar with the logic resources, connectivity, routing, IOB
structure and features, etc.  Use FPGA Editor to look inside.  Try to
understand what it takes to have a signal from a selected I/O pad reach a
multiplier or a FF or block ram.  Then your I/O assignment choices might
come into context.

You might very well find out that only a few of your I/O's are compromised.
If you have, for example, a source-synchronous bus comming into the FPGA
through less-than-ideal channels, you might be able to carefully add a few
reclocking stages to get the signals where they need to go and not have
timing problems.


-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"




"Ying Hu" <huying@lastechnologies.com> wrote in message
news:ee88431.6@webx.sUN8CHnE...
> Thanks Marlboro,
>
> I did what you recommended and find FPGA A reaches timing closure with the
automatic pin assignment.
>
> Good lesson for me.
>
> But how can i minimize the effect of pin assignment? I think i should do
floorplanning but i just don't know where to start.
>
> can you recommend me some documents about floorplanning?
>
> Thanks a lot.



Article: 72805
Subject: Re: Spartan 3 Starter Kit and ISE WebPACK
From: Kroko <Kroko@nil.com>
Date: Thu, 02 Sep 2004 21:13:43 +0200
Links: << >>  << T >>  << A >>
>(To the best of my knowledge)  It isn't time limited in any way. I think
>the largest Spartan 3 fpga the free version will work with is around
>400K gates.

Thanks, I can select these devices in Project Navigator, I just
thought I read somewhere it will only support the 50K version ....

>The question I would ask though is the 200K gates on the Spartan 3
>board going to be enough for your design?

Well, I am a FPGA newbie and have to start somewhere. I just want to
learn and make some experiments ....And I don't want to stop after
3 month of trial.

When my designs don't fit into this device, I can easily switch to a
bigger one :-) I think 99$ is a very good price, if there is free
software available as well ....

Kroko.

Article: 72806
Subject: reg: clock generatred by combinational logic
From: vinodece@yahoo.co.in (vinod)
Date: 2 Sep 2004 13:50:48 -0700
Links: << >>  << T >>  << A >>
hi

i am designing one receiver which had 2 data input
lines(indatax,indatay) and i have to extract clock from that. with
change of data(ie.comparing present bit with previous bit ) i have to
genrate clock. so i used ex-or logic.like this


 if ( (x xor indatax)= '1' or (y xor indatay)= '1') then
    if ( var = '0') then
         intclk <= '1';
           
         var := '1';
         
          x := indatax;
          y := indatay;
         
   end if;
 end if;  
   if ((indatax xor x)= '1' or (y xor indatay)= '1')then
 if ( var = '1') then      
    intclk <= '0';
            
          var := '0';
          
        x := indatax;
       y := indatay;
         
    end if;
 end if;
   

now i want to use intclk as a clock. i used it as a clock but in
synthesis(XST for virtex 2) i got this warning
------------------
> -----------------------------------+------------------------+-------+
> Clock Signal                       | Clock buffer(FF
> name)  | Load  |
> -----------------------------------+------------------------+-------+
> clk                                | BUFGP
>      | 61    |
> invclk                             | BUFGP
>      | 2     |
> I_intclk:O                         |
> NONE(*)(dataword_15)   | 44    |
> -----------------------------------+------------------------+-------+
> (*) This 1 clock signal(s) are generated by
> combinatorial logic,
> and XST is not able to identify which are the primary
> clock signals.
> Please use the CLOCK_SIGNAL constraint to specify the
> clock signal(s) generated by combinatorial logic.

so how shud i overcome..plz help me in that

thank you.
vinod

Article: 72807
Subject: StateCad, IO vector question.
From: "J.W. Holloway" <holloway@mit.edu>
Date: Thu, 02 Sep 2004 17:41:56 -0400
Links: << >>  << T >>  << A >>
I'm fairly new to this FPGA work, so my apologies if this is silly.

I'm using Xilinx's StateCad software to implement a simply FSM (~30
states) with the intention of using a Spartan3, XC3S200.

I have a number of 12-bit buses coming into the FSM. Three of these buses
are IO buses -- I want to read data off of the bus in some states, and
write to the bus in other states. Seems like a reasonable request, eh?

The problem: I've laid out the vectors in StateCad, reading and writing to
the VHDL variable names in various states. Additionally, I have set the
tristate bit on these buses in the appropriate states. When StateCad
generates the VHDL, it pronounces these vectors as OUTPUT vectors. Hrm, a
little strange.

I tried to get around this by having a separate set of buses that are
dedicated input buses. The PCB would then just short the input bus pins to
the output bus pins, and I'd jockey buses around so the output buses would
be high-impedance when appropriate. I know, I know, what a kludge, but I
need this done ASAP.

Well, to make a long story short, I can't map the FSM to the device I'm
using (and I basically have to use this particular device) -- I'm using to
many IOB. So, I need to get rid of 3 of those dedicated input buses, and
get some actual IO buses.

Is there any way to do this in StateCad? Am I missing something simple
here? I only have ~4 days experience with the Xilinx software, so bear
that in mind.

Useful details on my StateCad configuration:

Options: Full Vector Support, Retain Output Values Datatype: std_logic,
Bit: std_logic, Vector: std_logic_vector VHDL output
Language Vendor: IEEE 1076


Anyway, any advice would be appreciated. Thanks.

-Jack


-- 
Jack W. Holloway	holloway@mit.edu


Article: 72808
Subject: Re: Spartan 3 Starter Kit and ISE WebPACK
From: "Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com>
Date: Thu, 2 Sep 2004 17:00:32 -0700
Links: << >>  << T >>  << A >>
"Kroko" <Kroko@nil.com> wrote in message
news:porej01o4afe1rh9250jr2crvcrkur8vat@4ax.com...
> >(To the best of my knowledge)  It isn't time limited in any way. I think
> >the largest Spartan 3 fpga the free version will work with is around
> >400K gates.

Just to clarify what comes with the Spartan-3 Starter Kit, it includes two
software license codes.  One code is for the Xilinx WebPack software (CD-ROM
included), which never expires.  WebPack supports the XC3S200 FPGA found on
the Starter Kit board as well as the smaller XC3S50 and the larger XC3S400
FPGAs.

The other code is a 60-day license for the full-featured, no-holds-barred
ISE Foundation software.  This is a superset of the WebPack software and
supports additional software features like CoreGenerator and supports _all_
Xilinx devices.  If you decide that you don't want to upgrade to ISE
Foundation, then you can continue using the WebPack software.  Again, there
is no expiration date for the WebPack software.

Here's a link comparing the various software versions.  Hey, these options
often confuse me and I work for the company!
http://www.xilinx.com/ise/devsys_feature_guide.pdf

Spartan-3 Starter Kit Board
http://www.xilinx.com/s3boards

[snip]

> When my designs don't fit into this device, I can easily switch to a
> bigger one :-) I think 99$ is a very good price, if there is free
> software available as well ....
>
> Kroko.
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3:  Make it Your ASIC



Article: 72809
Subject: Re: Spartan 3 Starter Kit and ISE WebPACK
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 02 Sep 2004 18:09:57 -0700
Links: << >>  << T >>  << A >>
Kroko <Kroko@nil.com> writes:
> Is it only possible for a limited time, or is there no time limit ?
> What I mean is, I don't want to use an evaluation version of some
> software that costs me a lot to buy later when the evaluation period
> is over ! And I need more that a few month to complete the project i
> have in mind ....

If they're the usual Xilinx evaluation CDs, they'll work as both
a time-limited full-featured ISE evaluation, and as a non-time-limited
Webpack.  You can use the time-limited evaluation to decide whether
the features missing from Webpack are worth purchasing.

I've found that WebPack is sufficient for doing some fairly sophisticated
things, though I sometimes wish it had the FPGA Editor.

Article: 72810
Subject: the pci signal
From: "NoThisRAT" <nothisrat@yahoo.com>
Date: Fri, 3 Sep 2004 09:31:13 +0800
Links: << >>  << T >>  << A >>
Hi,Friends,
  In my pci interface design, I dont design the PAR signal logic, how should
I deal with the PAR pin? and PERR and SERR? thanks!

Regards



Article: 72811
Subject: Re: EDK core wrapping and include files
From: "Antti Lukats" <antti@case2000.com>
Date: Thu, 2 Sep 2004 18:59:33 -0700
Links: << >>  << T >>  << A >>

"E.S." <emu@ecubics.com> wrote in message
news:pXHZc.1$tT5.0@fe61.usenetserver.com...
> Antti Lukats wrote:
>
> > "John Williams" <jwilliams@itee.uq.edu.au> wrote in message
> > news:4131c785$0$27241$61ce578d@news.syd.swiftdsl.com.au...
>
> >>Good plan!  I would love to see a wishbone -> opb bridge to get some of
> >>that great opencores.org stuff into microblaze projects.
> >
> > opencores stuff is actually being used in OPB/Microblaze systems at many
> > places :)
>
> Where ?

in secret places, I did not say those designs are in public, only that
wishbone peripherals are in use in OPB based systems.

Antti





Article: 72812
Subject: Completed my first Virtex4 design
From: Philip Freidin <philip@fliptronics.com>
Date: Fri, 03 Sep 2004 05:32:06 GMT
Links: << >>  << T >>  << A >>
Well,
Xilinx shipped me my Foundation 6.3i software update,
and since it has the initial support for Virtex 4,
I installed it and did a design.

Here it is:

====

module top(in_bus,out_bus);
    input [15:0] in_bus;
    output [15:0] out_bus;

assign out_bus = {in_bus[14:0],in_bus[15]};

endmodule

====

Par Report (trimmed):

Release 6.3i Par G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Thu Sep 02 19:16:08 2004
Loading device database for application Par from file "top_map.ncd".
   "top" is an NCD, version 2.38, device xc4vfx12, package sf363, speed -11
Loading device for application Par from file '4vfx12.nph' in environment
Device speed data version:  PREVIEW 1.46 2004-07-09.
Device utilization summary:
   Number of External IOBs            32 out of 240    13%
      Number of LOCed External IOBs    0 out of 32      0%

Total REAL time to PAR completion: 19 secs 
Total CPU time to PAR completion: 18 secs 

Peak Memory Usage:  105 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

====

Some of the manuals are single page PDFs, that point you to
the web site to get the real thing.

Although you all do HDL designs only, you might want to get
the Schematic Designers library guide as well as the HDL guide,
as the HDL one is 290 pages, and the schematic one is 700 pages.
Most of the extra stuff is stuff you don't need, such as 4 bit
counter macros, but there are also some things that are pretty
interesting that seem to have been left out of the HDL version.
Probably fixed in the next version.

FPGA editor shows lots of interesting new stuff. Still waiting
for a data sheet, as the FPGA editor shows you details of the
forest from the perspective of having your nose pressed against
a huge tree :-) and the library guides is mostly very detailed
for simple stuff like logic and FF primitives, and not nearly
as much info as you might want for the complex stuff.

If this is the sort of thing you like, then you will probably
like this sort of thing.

Philip



Philip Freidin
Fliptronics

Article: 72813
Subject: Re: DDR SDRAM
From: "H. Peter Anvin" <hpa@zytor.com>
Date: Thu, 02 Sep 2004 22:34:37 -0700
Links: << >>  << T >>  << A >>
Marcus Harnisch wrote:
> Hi Andre,
> 
> Don't get me wrong, but if you are trying to decypher the waves at the
> SDRAM interface it would help if you'd know about some of the basics
> of DDR SDRAMs. The "usual suspects" (Micron, Samsung, etc.) provide
> good datasheets for download. JEDEC79x (x >= C) might be a little
> dry but is certainly the most comprehensive source of information in
> that respect.
> 

I personally find the Micron data sheets to be very good references, myself.

	-hpa

Article: 72814
Subject: Re: Completed my first Virtex4 design
From: Jim Granville <no.spam@designtools.co.nz>
Date: Fri, 03 Sep 2004 17:52:50 +1200
Links: << >>  << T >>  << A >>
Philip Freidin wrote:
> Well,
> Xilinx shipped me my Foundation 6.3i software update,
> and since it has the initial support for Virtex 4,
> I installed it and did a design.
<snip>
> Par Report (trimmed):
> 
> Release 6.3i Par G.35
> Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
> Thu Sep 02 19:16:08 2004
> Loading device database for application Par from file "top_map.ncd".
>    "top" is an NCD, version 2.38, device xc4vfx12, package sf363, speed -11
> Loading device for application Par from file '4vfx12.nph' in environment
> Device speed data version:  PREVIEW 1.46 2004-07-09.
> Device utilization summary:
>    Number of External IOBs            32 out of 240    13%
>       Number of LOCed External IOBs    0 out of 32      0%

  Wot, No Speed reports ?
You should try a 32 bit ctr, and see what it reports :)
-jg


Article: 72815
Subject: Re: reg: clock generatred by combinational logic
From: ALuPin@web.de (ALuPin)
Date: 2 Sep 2004 23:48:55 -0700
Links: << >>  << T >>  << A >>
Hi,

you should try not to use combinatorial clocks, that leads
to an asynchronous design. Instead use outputs of registers.

vinodece@yahoo.co.in (vinod) wrote in message news:<f9919650.0409021250.111f924@posting.google.com>...
> hi
> 
> i am designing one receiver which had 2 data input
> lines(indatax,indatay) and i have to extract clock from that. with
> change of data(ie.comparing present bit with previous bit ) i have to
> genrate clock. so i used ex-or logic.like this
> 
> 
>  if ( (x xor indatax)= '1' or (y xor indatay)= '1') then
>     if ( var = '0') then
>          intclk <= '1';
>            
>          var := '1';
>          
>           x := indatax;
>           y := indatay;
>          
>    end if;
>  end if;  
>    if ((indatax xor x)= '1' or (y xor indatay)= '1')then
>  if ( var = '1') then      
>     intclk <= '0';
>             
>           var := '0';
>           
>         x := indatax;
>        y := indatay;
>          
>     end if;
>  end if;
>    
> 
> now i want to use intclk as a clock. i used it as a clock but in
> synthesis(XST for virtex 2) i got this warning
> ------------------
> > -----------------------------------+------------------------+-------+
> > Clock Signal                       | Clock buffer(FF
> > name)  | Load  |
> > -----------------------------------+------------------------+-------+
> > clk                                | BUFGP
> >      | 61    |
> > invclk                             | BUFGP
> >      | 2     |
> > I_intclk:O                         |
> > NONE(*)(dataword_15)   | 44    |
> > -----------------------------------+------------------------+-------+
> > (*) This 1 clock signal(s) are generated by
> > combinatorial logic,
> > and XST is not able to identify which are the primary
> > clock signals.
> > Please use the CLOCK_SIGNAL constraint to specify the
> > clock signal(s) generated by combinatorial logic.
> 
> so how shud i overcome..plz help me in that
> 
> thank you.
> vinod

Article: 72816
Subject: Re: Spartan 3 Starter Kit and ISE WebPACK
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Fri, 3 Sep 2004 07:50:09 +0000 (UTC)
Links: << >>  << T >>  << A >>
Steven K. Knapp <steve.knappNO#SPAM@xilinx.com> wrote:
: "Kroko" <Kroko@nil.com> wrote in message
: news:porej01o4afe1rh9250jr2crvcrkur8vat@4ax.com...
: > >(To the best of my knowledge)  It isn't time limited in any way. I think
: > >the largest Spartan 3 fpga the free version will work with is around
: > >400K gates.

: Just to clarify what comes with the Spartan-3 Starter Kit, it includes two
: software license codes.  One code is for the Xilinx WebPack software (CD-ROM
: included), which never expires.  WebPack supports the XC3S200 FPGA found on
: the Starter Kit board as well as the smaller XC3S50 and the larger XC3S400
: FPGAs.

: The other code is a 60-day license for the full-featured, no-holds-barred
: ISE Foundation software.  This is a superset of the WebPack software and
: supports additional software features like CoreGenerator and supports _all_
: Xilinx devices.  If you decide that you don't want to upgrade to ISE
: Foundation, then you can continue using the WebPack software.  Again, there
: is no expiration date for the WebPack software.

Is this 60-day license also a time-based license (TBL)?
http://www.xilinx.com/ise/license/license.htm tells:
The Time-Based License does provide for "archival use" of the software. That
is, any designer who needs to modify a design or fix a bug after the one
year license has ended is permitted to do so.

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 72817
Subject: Re: vga to ethernet converter
From: "Rune Christensen" <rune.christensen@adslhome.dk>
Date: Fri, 3 Sep 2004 12:02:36 +0200
Links: << >>  << T >>  << A >>
"Ian"
<${send-direct-email-to-news1021-at-jusme-dot-com-if-you-must}@jusme.com>
skrev i en meddelelse news:Q0qZc.555637$6p.104886@news.easynews.com...
> On Wed, 1 Sep 2004 12:36:04 +0200, Rune Christensen
<rune.christensen@adslhome.dk> wrote:
>
> >Does anyone know if it's possible to build a VGA to ethernet converter? A
> >device that converts a VGA signal to a digital videostream.
> >I want to be able to operate a computer from a remote position also when
the
> >computer boots. So I will be able to change bios settings, starting mode
of
> >Windows, etc.
>
> Some "server management" cards do just this. Needs to either snoop the bus
for VGA
> accesses or fully emulate a VGA adapter (i.e. they /are/ the VGA adapter
for the
> machine). Quite expensive to buy, quite hard to make...
>
>
> -- 
> Ian
>
> 'Milk below!'

I think that this must the easiest solution to the problem. Create a VGA
card that transfer the screen to ethernet instead of a screen. Maybe a PCI
FPGA card could be used to do this.

To the people on comp.arch.fpga have anyone tried to create a VGA card on a
PCI FPGA card?

Thanks
Rune Christensen



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Article: 72818
Subject: Unisim Library
From: mnamky@hotmail.com (Mohamed Elnamaky)
Date: 3 Sep 2004 03:38:14 -0700
Links: << >>  << T >>  << A >>
Dear All;

please, I need to use the library of Unisim from Xilinx in my VHDL
code simulated with ModelSim. How can I make the link? I appreciate
your time answering a basic question like that but it is urgent.

Thank you

Article: 72819
Subject: Re: Xilinx XQ4036-3PG411 problem
From: rui_ferreira@megamail.pt (Rui Ferreira)
Date: 3 Sep 2004 03:51:56 -0700
Links: << >>  << T >>  << A >>
Fatal Omission. Forgot to add the XL. The part is a XQ4036XL-3PG411.

Best Regards,
Rui Ferreira

Article: 72820
Subject: spartan3 pci above 33MHz
From: colin_toogood@yahoo.com (colin)
Date: 3 Sep 2004 04:35:48 -0700
Links: << >>  << T >>  << A >>
Hi all

I am interfacing a spartan 3 to a device that happens to use PCI. As
the two devices will be about an inch apart with a point to point bus
I'm curious about the right buffer to instantiate, particularly as
bandwith calculations suggest that I need to run this bus at about
50MHz and the datasheet says that only pci_3v_33 exists in the IOB
when pci_3v_66 exists for virtex 2.

Presumably on a standard PCI card the requirements for clock, req and
the other few point to point signals also aren't electrically PCI. In
particular clock is almost certainly provided by a standard LVCMOS
clock driver so what IOB settings to people use?

Thanks in advance for any suggestions.

Colin

Article: 72821
Subject: ADC unit with 2 input channels, 12 bit, 10MHz conversion rate, 4Ksamples FIFO, USB (or PCI on PC104+ form) interface, Linux, QNX driver
From: <Karl Johansen>
Date: Fri, 3 Sep 2004 21:48:15 +1000
Links: << >>  << T >>  << A >>
I'm looking Analog to Digital Converter (ADC) board with
    2 Input channels
    12 bit resolution
    10 Mega saples/second conversion rate
    4 K samples buffer
    USB interface (or PCI on PC104+ form)
    Linux and QNX (and Windows) SW drivers

Does anybody recomment any board with above characteristics?

Thx 



Article: 72822
Subject: Fanout Xilinx
From: ted644@hotmail.com (Ted)
Date: 3 Sep 2004 05:03:55 -0700
Links: << >>  << T >>  << A >>
Hello All,

I am trying to obtain the total fanout of all nets in my design. I
tried using timing to do it and yes, I have all the fanouts. However,
there seems to be number of problems:

1) Path overlaps indicating that the same net might be used more than
the total number of fanouts indicated.

2) What are Tiopi, Tilo and Tioop? Are they different type of wires?
Where is documentation for these things? I can't seem to find them in
the help files.

Is there any straight forward way of finding total fanout besides
parsing the output file with perl or something? Thanks.

Ted

Article: 72823
Subject: Re: Unisim Library
From: Michal <NOmhusm@SPAMyahoo.com>
Date: Fri, 03 Sep 2004 14:47:55 +0200
Links: << >>  << T >>  << A >>
Mohamed Elnamaky wrote:
> Dear All;
> 
> please, I need to use the library of Unisim from Xilinx in my VHDL
> code simulated with ModelSim. How can I make the link? I appreciate
> your time answering a basic question like that but it is urgent.
> 
> Thank you

Hi Mohamed

The best solution is to use compxlib program from XilinxISE packet. For 
this open windows console and type:

compxlib -help

read examples and descriptions for all options.

This is a example for VirtexIIPro, ModelsimSE, Unisims and Verilog/VHDL. 
Compiled libraries will be placed in c:\Xilinx\comp_libs directory.

compxlib -s mti_se -f virtex2p:u -l all -o c:\Xilinx\comp_libs

After compilation, path to Unisims will be added to modelsim.ini file. I 
think that's all. I don't have experience with ModelsimXE. By the way, 
which version do you have ? :)

Michal


Article: 72824
Subject: Re: modelsim and rocketio
From: "Hans" <hansydelm@no-spam-ntlworld.com>
Date: Fri, 03 Sep 2004 12:49:14 GMT
Links: << >>  << T >>  << A >>
Make sure you have set your smartmodel mappings in your modelsim.ini file
(end of it). These mappings are used by Modelsim to find out were the
compiled smartmodel library is located. Also have a look on the Xilinx
website which contains lots of info on how to use RocketIO with Modelsim :-)

Hans
www.ht-lab.com


-- 
Regards,
Hans.
"shalini" <shalini_rao27@yahoo.co.in> wrote in message
news:bb192883.0408310354.538b339f@posting.google.com...
> When doing behavioral simulation using modelsim 5.8b SE version for
> rocket io
> i am getting the warning as
> # No default binding for component 'gt_fibre_channel_4'(no entity
> gt_fibre_channel) was found.
>
> and all the outputs of mgt are having the value 'U'.





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