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Messages from 73750

Article: 73750
Subject: Read back FPGA configuration
From: "alonzo" <rha_x@yahoo.com>
Date: Wed, 29 Sep 2004 03:10:57 -0400
Links: << >>  << T >>  << A >>
Hello,
I'm trying to readback the configuration file of an FPGA. Does anybody has
ideas about how would be the best way to do it? I'm trying to use iMPACT
command readbackToFile and I get the following error: 
// *** BATCH CMD : readbackToFile -p 1 -f remay
ERROR:iMPACT:1353 - ACD entry  READBACK_PROGRESS_COUNT not found for
device
   family xc2s200e.
EXCEPTION:iMPACT:ConstraintsManager.c:394:1.34.2.1 - Data not found.


Any ideas??

Thanks!
Alonzo.


Article: 73751
Subject: Re: Spartan-3 VCCIO ramp up time
From: hmurray@suespammers.org (Hal Murray)
Date: Wed, 29 Sep 2004 02:13:58 -0500
Links: << >>  << T >>  << A >>
>This issue is (was) new:  the ESD protection of the Vcco pins was firing 
>on a high (very fast) dV/dt.  Later mask sets got fixed, but some early 
>  mask sets are still in production with this restriction.

Interesting to see 600 microseconds referred to as very fast.  :)

Thanks everybody for taking the time to explain things.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 73752
Subject: Re: VHDL inout used for non bidirectional uses
From: hmurray@suespammers.org (Hal Murray)
Date: Wed, 29 Sep 2004 02:19:00 -0500
Links: << >>  << T >>  << A >>
>If I need to read an OUT port from
>the same process that drives it, 
>then I have written a state machine that
>lacks a process variable or architecture
>signal to maintain the local state value.

There are analog/timing reasons for wanting to use
a signal after it has gone out and back in the same
pin.

I'd probably try to stuff that sort of hackery
into a subroutine.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 73753
Subject: Re: Would flash/antifuse-based vendors be more likely to disclose
From: Adam Megacz <adam@megacz.com>
Date: Wed, 29 Sep 2004 01:07:38 -0700
Links: << >>  << T >>  << A >>

actela <actela@nowhere.net> writes:
> If you developed a field-process to extract the config-bitstream
> of 1 loaded/configured FPGA, presumably you could do it to any
> other FPGA based on the same die.

> So does it really matter whether the 'secret key' was unique to each
> customer's bitstream?

I suspect that any such process would have high variable cost and low
fixed cost.

But I could be wrong.

  - a

Article: 73754
Subject: Re: MicroBlaze is no available as Open-Source!! (from independant 3rd party)
From: jon@beniston.com (Jon Beniston)
Date: 29 Sep 2004 01:48:01 -0700
Links: << >>  << T >>  << A >>
"Antti Lukats" <antti@case2000.com> wrote in message news:<cjbrus$csk$02$1@news.t-online.com>...
> Hi All
> 
> finally today the project maintainer at opencores uploaded the verilog
> design files for MicroBlaze compliant IP-Core. Download is available at
> opencores.com - as project aeMB !!

How long before Xilinx try to get them to remove it do we reckon?

Cheers,
Jon

Article: 73755
Subject: Content of RAM in Modelsim
From: ALuPin@web.de (ALuPin)
Date: 29 Sep 2004 02:44:24 -0700
Links: << >>  << T >>  << A >>
Hi,

I use the ALTSYNCRAM component in Altera QuartusII version 4.1 SP2

It has the following ports:

data_a[35..0]
address_a[1..0]
wren_a
byteena_a[3..0]
q_a[35..0]
clock_a
aclr_a

data_b[35..0]
address_b[1..0]
wren_b
q_b[35..0]
clock_b
aclr_b

To make the content of the RAM visible during simulation with MODELSIM
I choose the component ALTSYNCRAM in Modelsim and open the PROCESS
and the VARIABLES window.
When I choose the line__21837 I see the variable m_mem_data_a which
seems to represent the content of the RAM.

When I add this array to my wave window and simulate my design I can see
that m_mem_data_a changes  while 'wren_b' is high ?  ('wren_a' is deasserted)
The output a PORT A  q_a also changes its value.

I do not understand that. Why does the output of PORT A change with
the clock of PORT B when 'wren_b' is asserted?

Does m_mem_data_a show the content with reference to PORT A or PORT B or
both?

When I look at an additional array called "m_mem_data_b" I see that
its content remains "XXX...XXX" during the complete simulation. So what
does this array represent?


Any idea of what is going on ?

I would appreciate your help.

Rgds

Article: 73756
Subject: Re: MicroBlaze & SRAM
From: Ben G <nospam@nospam.nospam>
Date: Wed, 29 Sep 2004 10:52:30 +0100
Links: << >>  << T >>  << A >>
Philip,

many thanks for your help, using your suggestion I am now able to access 
the full SRAM device. I had connected addr bit 0 to SRAM addr bit 0 not 
realising this was incorrect, your description was spot on.

Ben.

Article: 73757
Subject: Re: luts are optimized away
From: Marc Randolph <mrand@my-deja.com>
Date: Wed, 29 Sep 2004 06:51:16 -0500
Links: << >>  << T >>  << A >>
van de Kerkhof wrote:
> Hi.

Howdy Bram,

> I made a programmable lut delay.

A LUT delay?  How much of a delay, and how did you attempt do this? 
Unless you are using an SRL, you are probably not getting what you are 
wanting.

> Xilinx ise thinks it may optimize some luts away how can i prevent this.

Use FF's or SRL's.

> I use synplicity for synthesis.
> 
> I already tried: keep keep_architecture syn_noprune syn_keep syn_preserve.
> 
> Changing the lut init by making an other design will change the number of
> luts it will optimize but it should be possible to say dont touch the luts??

Unless you instantiate the LUTs and Fx muxes, I could see it being very 
hard to keep a good synthesis tool from doing its job.  After all, 99% 
of the users want the synthesis tool to optimize the LUTs as much as 
possible.  It typically leads to faster designs and lower utilization.

Good luck,

    Marc

Article: 73758
Subject: Re: Microblaze : ilmb_Cntrl
From: Shalin Sheth <Shalin.Sheth@xilinx.com>
Date: Wed, 29 Sep 2004 04:56:38 -0700
Links: << >>  << T >>  << A >>
I have seen this error when I increased the memory in my MHS file and 
did not increase the memory specified in my linker script?

If you remove your linker script what are the size of the text, bss and 
data sections reported by the tools?  What is the size of the memory you 
have specified?

Cheers.
Shalin-

Madhura wrote:
> Hi,
> 
> I get the following error, I am not sure how to fix that. I have tried increasing the memory size, but that doesnt help.
> 
> mb-ld: region ilmb_cntlr is full (TestApp/executable.elf section .sdata2)
> mb-ld: region ilmb_cntlr is full (TestApp/executable.elf section .sdata2)
> mb-ld: section .data [00000000 -> 0000005f] overlaps section .text [00000000 -> 0000109f]
> make: *** [TestApp/executable.elf] Error 1
> 
> Any suggestion in this direction will help.
> 
> Thanks,
> Madhura


Article: 73759
Subject: Re: luts are optimized away
From: "van de Kerkhof" <bvdk@NOSPAMMoce.nl>
Date: Wed, 29 Sep 2004 14:00:52 +0200
Links: << >>  << T >>  << A >>
It is ment for dqs delay in a ddr design.

synthesis is ok the delay line is still there but ISE is deleting them.

Bram


 "Marc Randolph" <mrand@my-deja.com> wrote in message
news:R-idndwld6koPMfcRVn-gQ@comcast.com...
> van de Kerkhof wrote:
> > Hi.
>
> Howdy Bram,
>
> > I made a programmable lut delay.
>
> A LUT delay?  How much of a delay, and how did you attempt do this?
> Unless you are using an SRL, you are probably not getting what you are
> wanting.
>
> > Xilinx ise thinks it may optimize some luts away how can i prevent this.
>
> Use FF's or SRL's.
>
> > I use synplicity for synthesis.
> >
> > I already tried: keep keep_architecture syn_noprune syn_keep
syn_preserve.
> >
> > Changing the lut init by making an other design will change the number
of
> > luts it will optimize but it should be possible to say dont touch the
luts??
>
> Unless you instantiate the LUTs and Fx muxes, I could see it being very
> hard to keep a good synthesis tool from doing its job.  After all, 99%
> of the users want the synthesis tool to optimize the LUTs as much as
> possible.  It typically leads to faster designs and lower utilization.
>
> Good luck,
>
>     Marc



Article: 73760
Subject: Re: Co-Processor for Microblaze or PowerPC Processor
From: Shalin Sheth <Shalin.Sheth@xilinx.com>
Date: Wed, 29 Sep 2004 05:01:30 -0700
Links: << >>  << T >>  << A >>
Roger,

Check out XAPP529 "Connecting Customized IP to the MicroBlaze Soft 
Processor Using the Fast Simplex Link (FSL) Channel"

http://direct.xilinx.com/bvdocs/appnotes/xapp529.pdf

This shows an example of connecting a IDCT function in hardware to the 
MicroBlaze processor using the FSL link.  The design files are also 
linked from the application note itself.

Cheers,
Shalin-

Roger Planger wrote:

> Hi
> 
> I am currently developing a Co Processor which performs some arithmetic 
> operations more efficiently, and I want to test this within a processor. I 
> have done this once with den LEON Processor, but now I wanna try it with 
> Microblaze or Power PC Processor if this is possible. I use VHDL as design 
> language, so is there some online tutorial which explains me how I can add 
> my Co Processor and the new op-Codes which should be performed by the 
> Coprocessor. Unfortunately I wasnt able to find any information about this 
> on the web
> 
> Cheers
> Roger 
> 
> 


Article: 73761
Subject: Encoding systems
From: Dominik Gawlowski <D.M.Gawlowski@tue.nl>
Date: Wed, 29 Sep 2004 14:47:57 +0200
Links: << >>  << T >>  << A >>
Hello

I have found that XST have several methods of FSM (Final State 
Machine)encoding:
auto		this is automatically chosen method
1-hot		every one knows how it works
compact		what is it????
sequential	what is it????
gray		most of the people know
johnson		what is it??
user		how to declare own method of encoding
none		every one knows

I have the following problems:

1. There is encoding called binary encoding in which I am interested and 
I do not know if one of the above is the one which I am looking for.
(maybe I am calling it improperly, but I have found informatuons about 
this encoding on xilinx webpage)

2. How to use this user encoding??
I do not know how to force the XST to encode the FSM in other meethods 
(for example jedi)


thank you in advance for help


best regards

Dominik

Shalin Sheth wrote:
> Roger,
> 
> Check out XAPP529 "Connecting Customized IP to the MicroBlaze Soft 
> Processor Using the Fast Simplex Link (FSL) Channel"
> 
> http://direct.xilinx.com/bvdocs/appnotes/xapp529.pdf
> 
> This shows an example of connecting a IDCT function in hardware to the 
> MicroBlaze processor using the FSL link.  The design files are also 
> linked from the application note itself.
> 
> Cheers,
> Shalin-
> 
> Roger Planger wrote:
> 
>> Hi
>>
>> I am currently developing a Co Processor which performs some 
>> arithmetic operations more efficiently, and I want to test this within 
>> a processor. I have done this once with den LEON Processor, but now I 
>> wanna try it with Microblaze or Power PC Processor if this is 
>> possible. I use VHDL as design language, so is there some online 
>> tutorial which explains me how I can add my Co Processor and the new 
>> op-Codes which should be performed by the Coprocessor. Unfortunately I 
>> wasnt able to find any information about this on the web
>>
>> Cheers
>> Roger
>>
> 


Article: 73762
Subject: Re: luts are optimized away
From: "Steven Archibald" <steven.archibald_no_spam@baesystems.com>
Date: Wed, 29 Sep 2004 14:09:03 +0100
Links: << >>  << T >>  << A >>

"van de Kerkhof" <bvdk@NOSPAMMoce.nl> wrote in message
news:1096459252.191676@news-ext.oce.nl...
> It is ment for dqs delay in a ddr design.
>
> synthesis is ok the delay line is still there but ISE is deleting them.
>
> Bram
>



try specifying a location for the LUTs in the constraints file to stop it
being optimized away.  Place the LUTs near the DQS pad to get a small delay



Article: 73763
Subject: Re: Looking for a Design for a Small FPGA Board
From: rwyoung@ieee.org (Rob Young)
Date: 29 Sep 2004 06:10:59 -0700
Links: << >>  << T >>  << A >>
--snip--
> Also, does anybody know about a source for generic usb dongle cases?
> Our quantities are not large enough to have a custom case molded.
> 
> Kolja Sulimma
> 
 --snip--

Pactec makes several cases that are appropriately sized.  I've seen
several comercial designs that use their CM line.

Rob Young
rwyoung@ieee.nospam.org

Article: 73764
Subject: Re: Spartan-3 VCCIO ramp up time
From: brimdavis@aol.com (Brian Davis)
Date: 29 Sep 2004 06:19:32 -0700
Links: << >>  << T >>  << A >>
Austin wrote:
> 
> This issue is (was) new:  the ESD protection of the Vcco pins
> was firing on a high (very fast) dV/dt.  
<snip>
> The circuit can not be triggered in normal operation, as it is
> only used on the Vcco pins, not the IO pins themselves.
> 

 My question was whether the internal VCCO rail collapse/ringing
induced by the parallel DCI startup current transient in a leaded
package would be sufficient to trigger the problematic ESD circuit.

 The VQ/TQ/PQ packages have a slower VCCO ramp rate spec than the
BGA packages, and have only one or two VCCO pins per bank.

 As a bitstream with parallel DCI finishes loading, the FPGA
experiences the mother-of-all-SSO transients when those split
terminators all turn on simultaneously.

back-of-envelope calculation: 

 If Bank 7 of a PQ208 were configured with 9 LVDS_25_DCI input
pairs plus a VRP/VRN pair, the DCI startup current spike for that
bank at the end of configuration would be ~400 mA.

 That current spike would have to flow through only two VCCO pins,
with a lead inductance of perhaps 8~12 nH for pin & wire bond in
a PQ208, as these appear to be standard leadframe packages(???).

 Guessing at a range of possible values for the internal VCCO rail
capacitance and the turn-on edge rate of the DCI terminators, this
might produce an on-die VCCO rail collapse or ringing of anywhere
from a few hundred millivolts to several volts in amplitude.


Brian

Article: 73765
Subject: Re: High speed counters on Xilinx CoolRunner-II
From: rsg@payload.com (Robert S. Grimes)
Date: 29 Sep 2004 06:55:22 -0700
Links: << >>  << T >>  << A >>
Yeah, that's sounds right, Glen; it's what I'm assuming.  The problem
is that I don't know how to tell it otherwise!  I've done fairly
complex designs before, but I've never had to deal with high speed. 
This project is fairly simple, but needs to high speed counters to
measure the arrival times of pulses on two signals.  So, I have three
signals that enter via pins (counter clock and the two pulse trains of
interest); the rest of the design can be relatively slower, maybe as
much as three orders of magnitude.

I have found the Xilinx tools really easy to learn and use, but to
really gain highest performance, they're not so simple...

Just looking for some pointers...

Thanks!
-Bob

glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote in message news:<cjcn1k$5ta$1@gnus01.u.washington.edu>...
> Robert S. Grimes wrote:
> 
> (snip of fast counter code)
> 
> > This runs pretty nicely; WebPACK reports max clock of 416.667 MHz. 
> > But the output cannot be read, so I added an output vector.  I also
> > added an enable signal.  The semantics I need is when the counter is
> > enabled, it counts clocks.  When it is not enabled, it holds the last
> > count.  I will only read the output count when the counter is not
> > counting.  Pretty simple, but it drops my maximum clock frequency to
> > 333.333 MHz!  
> 
> Does the timing analysis know you will only read it when it
> is not enabled?  I would guess it is setup time to the latch
> reading the count.  Static timing analysis probably assumes
> it could be counting.
> 
> -- glen

Article: 73766
Subject: PSL pros and cons
From: vizziee@yahoo.com (Kumar Vijay Mishra)
Date: 29 Sep 2004 07:03:13 -0700
Links: << >>  << T >>  << A >>
Hi.

I would like to know the pros and cons of having Property
Specification Language now offered with ModelSim 6.0. What is its
future? In this respect, what is assertion-based verification (ABV)?
And why all this now?

Thanx in advance.

KVM.

Article: 73767
Subject: Clock Edge notation
From: ALuPin@web.de (ALuPin)
Date: 29 Sep 2004 07:06:36 -0700
Links: << >>  << T >>  << A >>
Hi,

I have a question concerning the following phenomenon:

I have a signal which is registered by the following way:


entity xy is
port (...
      DQS : inout std_logic_vector(15 downto 0);
     );
end xy;

architecture zy of xy is
signal l_input_cell : std_logic_vector(15 downto 0);
begin

process(Reset, Clk)
begin
  if Reset='1' then
     l_input_cell <= (others => '0');
  elsif rising_edge(Clk) then
     l_input_cell <= DQS;
  end if;
end process;
end zy;

When I simulated the design (I had changed a different design to my
own
VHDL style) I got different simulation results (functional simulation
Modelsim) with respect to the signal "l_input_cell".

Then I changed "rising_edge(Clk)" back to "Clk'event and Clk='1'" and
I got the same result as in the original design.

So why is there a difference at all?
Does the use of an INOUT port play any role ?

I would appreciate your help.

Kind regards

André

Article: 73768
Subject: Re: suggestions for Xilinx tool enhancements
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 29 Sep 2004 15:14:33 +0100
Links: << >>  << T >>  << A >>
"Brannon King" <bking@starbridgesystems.com> writes:
<snip>
> The batch support on the tool is nice but I 
> have no way to pass in parameters. You know, like %1 %2 etc. -- general 
> features to make the batch stuff usable on a real project?
> 

My solution to that goes like this (in a file called prog.bat - call
it with the bitstream in %1):

echo setPreference -pref StartupClock:Auto_Correction >temp.impact
echo setMode -bs >>temp.impact
echo setCable -port lpt1 >>temp.impact
echo addDevice -position 1 -file %1 >>temp.impact
echo program -p 1 >>temp.impact
echo quit >>temp.impact

impact -batch temp.impact
pause

Nasty, but it works!

Cheers,
Martin

-- 
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

Article: 73769
Subject: Re: Clock Edge notation
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Thu, 30 Sep 2004 00:37:48 +1000
Links: << >>  << T >>  << A >>
On 29 Sep 2004 07:06:36 -0700, ALuPin@web.de (ALuPin) wrote:

[snip]
>Then I changed "rising_edge(Clk)" back to "Clk'event and Clk='1'" and
>I got the same result as in the original design.
>
>So why is there a difference at all?

http://groups.google.com/groups?selm=3d63466b.185967697%40netnews.agilent.com

Regards,
Allan

Article: 73770
Subject: Re: suggestions for Xilinx tool enhancements
From: "Brannon King" <bking@starbridgesystems.com>
Date: 29 Sep 2004 10:58:10 EDT
Links: << >>  << T >>  << A >>
That's a beautiful solution. I'm glad there are people in the world who can 
see the obvious.

"Martin Thompson" <martin.j.thompson@trw.com> wrote in message 
news:umzz9duwm.fsf@trw.com...
> "Brannon King" <bking@starbridgesystems.com> writes:
> <snip>
>> The batch support on the tool is nice but I
>> have no way to pass in parameters. You know, like %1 %2 etc. -- general
>> features to make the batch stuff usable on a real project?
>>
>
> My solution to that goes like this (in a file called prog.bat - call
> it with the bitstream in %1):
>
> echo setPreference -pref StartupClock:Auto_Correction >temp.impact
> echo setMode -bs >>temp.impact
> echo setCable -port lpt1 >>temp.impact
> echo addDevice -position 1 -file %1 >>temp.impact
> echo program -p 1 >>temp.impact
> echo quit >>temp.impact
>
> impact -batch temp.impact
> pause
>
> Nasty, but it works!
>
> Cheers,
> Martin
>
> -- 
> martin.j.thompson@trw.com
> TRW Conekt, Solihull, UK
> http://www.trw.com/conekt 



Article: 73771
Subject: Chipscope Pro and VHDL
From: Vivek <>
Date: Wed, 29 Sep 2004 08:04:58 -0700
Links: << >>  << T >>  << A >>
I was reading the manuals for Chipscope Pro and I am a bit confused. Does ChipScope Pro generate some sort of VHDL block that you place in your design and connect the appropriate signals to?

Or does it generate some vhdl code which you paste into a block?

I am using chipscope pro 6.2i. If anyone has information in regards to this, pleas elet me know. Thanks

Vivek

Article: 73772
Subject: Re: MicroBlaze is now available as Open-Source!! (from independant
From: "E.S." <emu@ecubics.com>
Date: Wed, 29 Sep 2004 09:05:08 -0600
Links: << >>  << T >>  << A >>
Jon Beniston wrote:

> How long before Xilinx try to get them to remove it do we reckon?

Why do you think, they should ?



Article: 73773
Subject: Virtex-II : Architecture
From: "Cyrille Lambert" <eepgcrl@brunel.ac.uk.nospam>
Date: Wed, 29 Sep 2004 08:37:25 -0700
Links: << >>  << T >>  << A >>
Hi everybody,

I cannot find any paper or application note on the Virtex-II architecture. Do you know where could I find it?
In order to know more about the bitstream in the spirit of the xapp151 for example. By the way, if this application note reflects the architecture of the Virtex-II tell me please, I am a bit lost.

Thanks by advance,
/Cyrille Lambert

Article: 73774
Subject: Re: Clock Edge notation
From: Jim Lewis <Jim@SynthWorks.com>
Date: Wed, 29 Sep 2004 08:43:52 -0700
Links: << >>  << T >>  << A >>
ALuPin,
First read Allan's post.

Bottom line, if Clk is doing a normal 0-1 transition,
these two are equivalent.  Highlighting the differences:
   rising_edge(Clk) finds 0-1, L-1, 0-H, L-H transitions of Clk
   clk='1' and Clk'event finds all changes except 1-1.

If your problem only occurs at time 0, you have run into a
well known issue that is easy to avoid.  See below.
If this happens at times other than time 0, the clock
net is misbehaving and it probably needs to be fixed.
I would not consider an X-1 transition of clock a valid
functional clock.

 From a different point of view, how are you deciding
that your designs are different?  If you mask out
things that occur before reset is applied, are they
the same?


Avoiding time 0 Problems
--------------------------
To avoid time 0 problems, I start clock at the inactive
edge and I initialize it:

signal Clk : std_logic := '0' ;
. . .

Clk <= not Clk after tperiod_Clk/2 ;

-- or --

process begin
   Clk <= '0' ;
   wait for tperiod_Clk/2 ;
   Clk <= '1' ;
   wait for tperiod_Clk/2 ;
end process ;


Use the form that matches your current clock driving methodology.
Although I recommend the first form for new projects, I do
not recommend switching after you have built and run testbenches
because differences in execution of testbenches that can result.
To illuminate this, consider the code below (note Sel is driven
only so you can see the differences in the two clock setups).

Sel <= '0' after tpd ;        -- where tpd << tperiod_Clk
wait for 10 * tperiod_Clk ;   --
wait until Clk = '1' ;        -- align with clock
Sel <= '1' after tpd ;

Simulation differences here are due to differences in
delta cycle setup time of the clocks above.

Long term, when using wait for that is a function of
your clock period, I using the following:

wait for 10*tperiod_Clk - tpd ;
wait until Clk = '1' ;


Cheers,
Jim
-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


> Hi,
> 
> I have a question concerning the following phenomenon:
> 
> I have a signal which is registered by the following way:
> 
> 
> entity xy is
> port (...
>       DQS : inout std_logic_vector(15 downto 0);
>      );
> end xy;
> 
> architecture zy of xy is
> signal l_input_cell : std_logic_vector(15 downto 0);
> begin
> 
> process(Reset, Clk)
> begin
>   if Reset='1' then
>      l_input_cell <= (others => '0');
>   elsif rising_edge(Clk) then
>      l_input_cell <= DQS;
>   end if;
> end process;
> end zy;
> 
> When I simulated the design (I had changed a different design to my
> own
> VHDL style) I got different simulation results (functional simulation
> Modelsim) with respect to the signal "l_input_cell".
> 
> Then I changed "rising_edge(Clk)" back to "Clk'event and Clk='1'" and
> I got the same result as in the original design.
> 
> So why is there a difference at all?
> Does the use of an INOUT port play any role ?
> 
> I would appreciate your help.
> 
> Kind regards
> 
> André



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