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Messages from 73075

Article: 73075
Subject: Re: Altera Quartus FSM Simulation Delay?
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Mon, 13 Sep 2004 13:46:23 -0700
Links: << >>  << T >>  << A >>

Pino wrote:


>    I am currently using an example from a book which codes a simple
> FSM.  The code is seen below.  I simulate the following FSM obtained
> from a text book under Quartus 4.0 with the condition that "in1"
> signal is low for one clock-cycle commencing at the negative edge of
> the clock for an entire period.  During this time, the state machine
> is in the "START" state, and the output changes to sequence =
> "continue" and the output changes immediately given a small delay
> (less than 1/2 clock period).  
(snip)

I believe you are rising edge triggered, not falling edge.

That is, at least, what I see in my simulations.

-- glen


Article: 73076
Subject: Re: Need some help with some technical claims...
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Mon, 13 Sep 2004 14:07:30 -0700
Links: << >>  << T >>  << A >>


Austin Franklin wrote:

> I need some help with something.  Someone made some technical
 > claims that I am questioning are correct or not ;-),
 > and would like to see what you guys think about these claims:

> #1> Programming FPGAs doesn't actually change or rewire those logic gates
> #1> in the silicon wafer. It changes bits of non-volatile memory that is
> #1> used as inputs to these gates. (These are not the gates you see when
> #1> you write the FPGA code, those are emulated by a combination of
> #1> hardwired gates and your code.)

Well, the LUT's do emulate logic gates.  The interconnect, though,
is programmable rewiring, at least traditionally done with pass
transistors, though now maybe more often with multiplexers.
Close enough to rewiring for me.

> #2>Software is defined as the part of a digital circuit that can be
> #2>changed without mechanical modifications, as opposed to hardware,
> #2>which is HARDwired. So FPGA code is software

So?   Where is the question?

Is verilog code for an ASIC software or hardware?

> #3> OTP EPROM data ... has always been regarded as software.

Well, OTP EPROM is already a contradiction.  Most people call
it firmware, though.

> #4> A LUT is not a device soldered onto the circuit board. It's not even
> #4> implemented in silicon (at least during the development stages). It's
> #4> programmed into an FPGA or suchlike and therefore software because you
> #4> can change it without any mechanical changes on the board.

An SRAM chip can be soldered into a board, and is usually implemented
in Silicon, though SiGe, or GaAs could also be used, does that matter?

Is this supposed to change the argument that FPGA code
is or isn't software?

> #5> Using a sufficiently parallelized, a LUT done in a
 > #5> DSP can be just as efficient as using an FPGA or ASIC.

Look up tables have been part of software design for as far
back as I know it.   Sometimes an address will be loaded from
a table as a branch targer, which makes the table darn close to
executable code.   In others, a table of branch instructions is
used as a target of an indexed branch, which definitely makes the
table executable.

Much software is table driven, where the code in the table is
interpreted in some way by directly executable code.

Many machines are microprogrammed, so that what you think of
as hardware is really software.

Trying to make fine distinctions between hardware and software
is a losing proposition.  Don't do it.

-- glen


Article: 73077
Subject: Re: Need some help with some technical claims...
From: Jim Granville <no.spam@designtools.co.nz>
Date: Tue, 14 Sep 2004 09:14:17 +1200
Links: << >>  << T >>  << A >>
Austin Franklin wrote:

> "Jim Granville" <no.spam@designtools.co.nz> wrote in message
> news:s791d.3289$mZ2.305623@news02.tsnz.net...
> 
>>Austin Franklin wrote:
>>
>>>One more claim from our "candidate":
>>>
>>>"And none of the professionals I've talked to referred to ASICs being
>>>hardware. You can't buy an ASIC, you have to design it, which makes
>>>
>>>its function software."
>>>
>>>And being a professional EE for over 25 years, having designed a few
> 
> dozen
> 
>>>ASICs, and worked with hundreds of ASIC designers, I've never heard
> 
> anyone
> 
>>>refere to ASICs as anything but hardware.  So, I can't imagine what
>>>professionals he is referring to that would think an ASIC was software!
>>
>>  Until it is sitting there, gleaming at you on the wafer, it is 100%
>>software.
> 
> 
> By your understanding, any design, what so ever, is software?  

Until it is constructed, and thus gets the 'Hard' in hardware, yes.

> Even a schematic?  So, a board level schematic is software as well?  
Yes.

 > VHDL and Verilog code is software?

As Hardware Description language, yes.
Software has two portions, the Data or your idea itself, and the 
programs you buy, that Compile/Change that data.

If one argues that Software is only commercial compilers, then
one must introduce a third category - Dataware/Ideaware ?


> 
>>So it is one of those semantics arguments, that depends on where you
>>are in the design life cycle.
> 
> 
> I very much disagree that it is a semantics argument.  It is an argument of
> understanding or not understanding concepts IMO.

Consider where the 'Hard' in hardware comes from ?
If you can hit it with a hammer, it is hardware, if it is an idea,
in whatever form, and does not need power, it is software.
( ie can you save it onto a CD ROM ? - then it is not hardware )

This can get even more semantic content, if one argues that a Printed 
Schematic is tangible, can be burnt, uses ink, and is thus hardware.
Or that the physical storage on a CD Rom uses physical phase change,
so that too is physical/hard in nature.... :)

-jg



Article: 73078
Subject: Re: why systemc?
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Mon, 13 Sep 2004 14:14:52 -0700
Links: << >>  << T >>  << A >>


Alexander Gnusin wrote:

> I do believe, that it is possible to write design in SystemC. There
> may be some advantages of this approach for people with strong C
> background. There are obviously drawbacks too, and I would like to
> outline some of them.

Personally, I am against HDL's that are more C like than verilog.

To me, they make people believe that one can think serially, as
when writing in a programming language.  In hardware, everything
at least has the possibility of being active all the time, and the
language should emphasize that.

Consider the ability to port a serial algorithm written in C to a
hardware implementation of that algorithm.

-- glen


Article: 73079
Subject: Re: Virtex 4 released today
From: Jim Granville <no.spam@designtools.co.nz>
Date: Tue, 14 Sep 2004 09:15:47 +1200
Links: << >>  << T >>  << A >>
Austin Lesea wrote:

> All,
> 
> As Peter would say, the teasing is over:  V4 is ALIVE.
> 
> http://www.xilinx.com for all of the details.
> 
> Now I can finally talk about it.

.. and one of Austin's shortest posts ever ... ;)

-jg


Article: 73080
Subject: Re: Virtex 4 released today
From: Austin Lesea <austin@xilinx.com>
Date: Mon, 13 Sep 2004 14:59:24 -0700
Links: << >>  << T >>  << A >>
Jim,

Thanks for the encouragement,

(long-winded, who me?)

Austin

Jim Granville wrote:
> Austin Lesea wrote:
> 
>> All,
>>
>> As Peter would say, the teasing is over:  V4 is ALIVE.
>>
>> http://www.xilinx.com for all of the details.
>>
>> Now I can finally talk about it.
> 
> 
> .. and one of Austin's shortest posts ever ... ;)
> 
> -jg
> 

Article: 73081
Subject: Re: Virtex 4 released today
From: Jim Granville <no.spam@designtools.co.nz>
Date: Tue, 14 Sep 2004 11:06:37 +1200
Links: << >>  << T >>  << A >>
Austin Lesea wrote:
> Jim,
> 
> Thanks for the encouragement,
> 
> (long-winded, who me?)

You're welcome  :)

To give you a chance to wind up on Virtex-4, here are a
couple of questions :

Virtex-4 does not seem to be supported in WebPACK
- when is this planned ?

Virtex-4 seems only available in large, BGA packages. When
do we expect to see Spartan-4? in TQFP and anything < 360 pins ?.

Xilinx has a nice Spartan-3 Eval PCB for $99, what is the
Virtex-4 EvalPCB status ? ( $99 ? :)

-jg


Article: 73082
Subject: Re: Need some help with some technical claims...
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Mon, 13 Sep 2004 16:11:01 -0700
Links: << >>  << T >>  << A >>


Jim Granville wrote:

(snip)

> Consider where the 'Hard' in hardware comes from ?
> If you can hit it with a hammer, it is hardware, if it is an idea,
> in whatever form, and does not need power, it is software.
> ( ie can you save it onto a CD ROM ? - then it is not hardware )

It is that you can save "it" on the CDROM.  Being able to save
an image of something, say a picture of a computer, doesn't count.

> This can get even more semantic content, if one argues that a Printed 
> Schematic is tangible, can be burnt, uses ink, and is thus hardware.
> Or that the physical storage on a CD Rom uses physical phase change,
> so that too is physical/hard in nature.... :)

A printed source listing or hex dump?

Anyway, the word firmware has been used, usually for microcode
that is changable but normally doesn't change in everyday use.

It is then often used for ROMs in microprocessor controlled
devices, again it is not changed in ordinary use, even though
it might be EPROM, EEPROM, or Flash RAM, or even battery
backed SRAM.

Now, how about the wiring plugboards that used to control
many IBM machines in the pre-computer days?  The wire itself
is hardware, but the positioning of the wires is software.
(It could be stored in netlist form, for example.)

-- glen


Article: 73083
Subject: Re: ML300 Ethernet question.
From: Paul Hartke <phartke@Stanford.EDU>
Date: Mon, 13 Sep 2004 18:18:41 -0700
Links: << >>  << T >>  << A >>
SysKonnect SK9-D41

Nicholas Weaver wrote:
> 
> Has anyone on here used the ML300 with the Gigabit ethernet (1000-SX)
> multimode connectors?
> 
> If so, what PCI/PCI-X/PCI-E NICs have you used on the PC side?
> 
> Thanks.
> 
> --
> Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 73084
Subject: Would flash/antifuse-based vendors be more likely to disclose
From: Adam Megacz <adam@megacz.com>
Date: Mon, 13 Sep 2004 18:29:33 -0700
Links: << >>  << T >>  << A >>

Of course this is purely hypothetical since -- right now -- none of
them do.

But it occurred to me that vendors like Actel could disclose their
bitstream format without scaring their customers and admitting that
the emperor has no clothes when it comes to bitstream
security-as-obscurity.

Getting the bitstream out of a flash/antifuse device that isn't
designed to emit it is probably harder than reverse engineering
Xilinx/Altera's bitstream formats.  And if you already know how to
disassemble chips and get a mask image out of them, well, the
so-called bitstream "encryption-but-you're-shipping-the-decryption-key
to-all-your-customers-in-this-little-black-package" is worthless
anyways.

Supposing somebody was able to present one of these vendors with a
tangible justification (ie way they would make more money) for
publicizing their bitstream format, does anybody think they would
publish it?

  - a




Article: 73085
Subject: spartan-3 I/O timing
From: "Robert Sefton" <rsefton@abc.net>
Date: Mon, 13 Sep 2004 19:19:38 -0700
Links: << >>  << T >>  << A >>
Can someone explain this to me?

Here's the LVTTL I/O timing for Virtex-2 -4 and Spartan-3 -4 (Fast 12mA 
drive for the outputs):

                Virtex-2    Spartan-3
                --------     ----------
TIOPI       0.88ns        2.15ns   (pad to IOB .I output)
TIOOP     1.74ns         0.48ns  (IOB ,O input to pad)

According to these numbers the Spartan-3 input buffer got 1.27ns slower and 
the output buffer got 1.26ns faster. Is this possible?

I have a Virtex-2 1000 design that fits perfectly in a Spartan-3 1000, but I 
just routed it and got a ton of input path timing errors. So much for saving 
$125 per chip with S3.

Thanks,
Rob
(email is bogus, please reply to group) 



Article: 73086
Subject: Re: Would flash/antifuse-based vendors be more likely to disclose
From: nweaver@soda.csua.berkeley.edu (Nicholas Weaver)
Date: Tue, 14 Sep 2004 02:40:00 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <x1wtyxmyde.fsf@nowhere.com>, Adam Megacz  <adam@megacz.com> wrote:
>
>Of course this is purely hypothetical since -- right now -- none of
>them do.
>
>But it occurred to me that vendors like Actel could disclose their
>bitstream format without scaring their customers and admitting that
>the emperor has no clothes when it comes to bitstream
>security-as-obscurity.

Thus you have the encrypted bitfile loading on the Virtex lines.
Personally, I think the V4 version is easily good enough for
protecting a $10,000 secret, and I could probably be OK comfort wise
protecting a $100,000 secret.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 73087
Subject: Re: Altera Quartus FSM Simulation Delay?
From: pinod01@sympatico.ca (Pino)
Date: 13 Sep 2004 20:00:39 -0700
Links: << >>  << T >>  << A >>
vbetz@altera.com (Vaughn Betz) wrote in message news:<48761f7f.0409122123.5cac9605@posting.google.com>...
> pinod01@sympatico.ca (Pino) wrote in message news:<b7ed9648.0409061419.32cb8013@posting.google.com>...
> > To all,
> > 
> >    I am currently using an example from a book which codes a simple
> > FSM.  The code is seen below.  I simulate the following FSM obtained
> > from a text book under Quartus 4.0 with the condition that "in1"
> > signal is low for one clock-cycle commencing at the negative edge of
> > the clock for an entire period.  During this time, the state machine
> > is in the "START" state, and the output changes to sequence =
> > "continue" and the output changes immediately given a small delay
> > (less than 1/2 clock period).  I have sketched out the timing diagram
> > as it appears in the simulation from the text book.  For some reason,
> > when I simulate this same state machine in Quartus with the same 10 ns
> > clock period, I end up getting "out1" delayed by more than half the
> > clock period.  I'm simulating using a stratix chipset speed grade -6. 
> > Unbelievably long time of a propagation delay, so does this sound
> > right to anyone?
> > 
> > ----     -----     -----
> >     |    |    |    |    |                  <= clock
> >     |    |    |    |    |
> >      ----      ----     ----
> > 
> > ----          --------------
> >     |         |                            <= in1 
> >     |         |
> >      ---------
> > 
> >             ---------
> >            |         |                      <= out1
> >            |         |
> > -----------           ---------
> > 
> >                       ---------
> >                      |         |            <= out2
> >                      |         |
> > ---------------------           ---------
> > 
> > ENTITY Test IS
> > PORT(
> >    clk, in1	:IN  STD_LOGIC;
> >    out1, out2	:OUT STD_LOGIC
> >      );
> > END ENTITY Test;
> > 
> > ARCHITECTURE a OF Test IS
> >    TYPE PULSER IS (start, continue);
> >    SIGNAL sequence: PULSER;
> > BEGIN
> > 
> >    PROCESS(clk)
> >    BEGIN
> > 	IF clk'EVENT AND clk = '1' THEN
> > 
> >           CASE sequence IS
> > 		when start=> 
> > 	           IF in1 = '1' THEN
> > 			sequence <= start;
> > 			out1 <= '0';
> > 			out2 <= '0';
> > 		   ELSE
> > 			sequence <= continue;
> > 			out1 <= '1';
> > 			out2 <= '0';
> > 		   END IF;
> > 		when continue=>
> > 			sequence <= start;
> > 			out1 <= '0';
> > 			out2 <= '1';
> > 
> > 		END CASE;
> > 	  	END IF;
> >    END PROCESS;
> > 
> > END ARCHITECTURE a;
> 
> 
> Hi,
> 
> It looks like out1 is a top-level output of your design.  That means
> it is being implemented in an IO pad, and the delay you are getting
> includes the output pad delay driving the default load (10 pF for
> Stratix LVTTL IOs).  That will be a significant delay.  Also, there is
> a significant delay in getting the clock from the clock input pad
> (where the simulator monitors it) to the clock input of the various
> flip flops (unless you use a PLL).
> 
> So a ~5 ns delay (Tco) is not unreasonable.
> 
> Vaughn
> Altera

Vaughn,

   I gather then that to decrease this delay I would need to use the
output of a PLL to feed the above process statement sensitivty list?  
If so, how could the PLL routing to the various flip flops be any
different then going from the input pad? Would there be that much of a
difference?   Incidentally, this significantly dampers the overall
speed at which the state-machine can operate.

Cheers,
Pino

Article: 73088
Subject: Re: Virtex 4 released today
From: "Kevin Neilson" <kevin_neilson@removethiscomcast.net>
Date: Tue, 14 Sep 2004 03:12:23 GMT
Links: << >>  << T >>  << A >>

"Jim Granville" <no.spam@designtools.co.nz> wrote in message
news:dKp1d.3374$mZ2.316373@news02.tsnz.net...
> Austin Lesea wrote:
> > Jim,
> >
> > Thanks for the encouragement,
> >
> > (long-winded, who me?)
>
> You're welcome  :)
>
> To give you a chance to wind up on Virtex-4, here are a
> couple of questions :
>
> Virtex-4 does not seem to be supported in WebPACK
> - when is this planned ?
>
> Virtex-4 seems only available in large, BGA packages. When
> do we expect to see Spartan-4? in TQFP and anything < 360 pins ?.
>
> Xilinx has a nice Spartan-3 Eval PCB for $99, what is the
> Virtex-4 EvalPCB status ? ( $99 ? :)
>
> -jg

Whoa; you can't expect the paperback to come out at the same time as the
hardcover.  -Kevin



Article: 73089
Subject: Re: New to FpGa ; At configuring the device error cmes
From: bhuvasen@hotmail.com (senthil)
Date: 13 Sep 2004 21:07:43 -0700
Links: << >>  << T >>  << A >>
If the LED is NOT green on your 4 then you have not 
> powered it correctly.
> 

Hi ..
I plugged the cable correctly. . the led also blown ie., power came up
from the usb port.. all things i made perfectly. but i didn't detect
the fpga..

give some suggestion..

Regards
Senthil.R

Article: 73090
Subject: Re: why systemc?
From: anamax@earthlink.net (Andy Freeman)
Date: 13 Sep 2004 21:30:52 -0700
Links: << >>  << T >>  << A >>
glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote in message news:<ci52f3$14o$1@gnus01.u.washington.edu>...
>                                             In hardware, everything
> at least has the possibility of being active all the time, and the
> language should emphasize that.

Nope.  A language should emphasize writing demonstrably correct programs.

> Consider the ability to port a serial algorithm written in C to a
> hardware implementation of that algorithm.

Yes, consider that.  Assuming that you're using multiple cycles, you're
reusing clocked storage, pipelining, or both.  Between said storage,
you've got acyclic or converging logic, and the correctness of the
latter, not to mention its timing, is very hard to verify.

Note that expressing clocked storage correctly in Verilog is not
straightforward.  (Disagree?  Explain why folks have problems with
storage they didn't intend or don't get storage they do intend.)
It's hard to do worse with C, and easy to do better.  (No, the
resulting C doesn't look much like sequential C, but so what?)

With the exception of don't cares, acyclic logic between storage elements
is just as easy to express in C as any HDL.  The only possible advantage
for HDLs is converging cyclic logic without control signals.

I don't think that HDLs are going to make up ground with better ways to
designate clock signals.

-andy

Article: 73091
Subject: Re: Newbie question systemc
From: Javier Castillo <jcastillo@opensocdesign.com>
Date: Tue, 14 Sep 2004 06:39:06 +0000 (UTC)
Links: << >>  << T >>  << A >>
aaruljain@gmail.com (Aarul Jain) wrote in
news:15891236.0409130014.5e7a0662@posting.google.com: 

> Hello
> 
> I am trying to learn systemc. Systemc was already installed in one of
> the servers and I am using Solaris 2.8 with gcc 3.3
> 
> I am trying to run example programs from the installation directory.
> However when I run make i get error message
> 
> -------compiles the code and generates .o --------
> ----
> g++  -I. -I..
> -I/_TOOLS_/dist/systemc-2.0.1/sparc-sun-solaris2.8/include -L. -L..
> -L/_TOOLS_/dist/systemc-2.0.1/sparc-sun-solaris2.8/libS/gcc-3.2.2 -o
> run.x source.o sink.o fft.o main.o  -lsystemc -lm  2>&1 | c++filt 
> Undefined                       first referenced 
>  symbol                             in file
> CoolLog::CoolLog[in-charge](char const*, char*,
> bool)/_TOOLS_/dist/systemc-2.0.1/sparc-sun-solaris2.8/libS/gcc-3.2.2/li
> bsystemc.a(sc_main.o) ld: fatal: Symbol referencing errors. No output
> written to run.x collect2: ld returned 1 exit status
> 
> I tried to do everything I could but it seems there is some problem in
> makefiles.
> 
> Following are the makefiles I used.
> 
> Makefile
> 
> TARGET_ARCH = gccsparcOS5
> 
> CC     = g++
> OPT    = -O3
> DEBUG  = -g
> OTHER  = -Wall
> EXTRA_CFLAGS = $(OPT) $(OTHER)
> # EXTRA_CFLAGS = $(DEBUG) $(OTHER)
> 
> MODULE = run
> SRCS = source.cpp sink.cpp fft.cpp main.cpp 
> OBJS = $(SRCS:.cpp=.o)
> 
> include ../Makefile.defs
> 
> 
> Makefile.defs
> 
> ## Variable that points to SystemC installation path
> SYSTEMC = /_TOOLS_/dist/systemc-2.0.1/sparc-sun-solaris2.8
> 
> 
> INCDIR = -I. -I.. -I$(SYSTEMC)/include
> LIBDIR = -L. -L.. -L$(SYSTEMC)/libS/gcc-3.2.2
Hello:

Try to use gcc 3.2 instead 3.3

Regards

Javier Castillo
jcastillo@opensocdesign.com
www.opensocdesign.com


> 
> LIBS   =  -lsystemc -lm $(EXTRA_LIBS)
> 
> 
> EXE    = $(MODULE).x
> 
> .SUFFIXES: .cc .cpp .o .x
> 
> $(EXE): $(OBJS) $(SYSTEMC)/libS/gcc-3.2.2/libsystemc.a 
>      $(CC) $(CFLAGS) $(INCDIR) $(LIBDIR) -o $@ $(OBJS) $(LIBS) 2>&1 |
> c++filt
> 
> .cpp.o:
>      $(CC) $(CFLAGS) $(INCDIR) -c $<
> 
> .cc.o:
>      $(CC) $(CFLAGS) $(INCDIR) -c $<
> 
> clean::
>      rm -f $(OBJS) *~ $(EXE) core
> 
> ultraclean: clean
>      rm -f Makefile.deps
> 
> Makefile.deps:
> #     $(CC) $(CFLAGS) $(INCDIR) -M $(SRCS) >> Makefile.deps
> 
> #include Makefile.deps
> 
> 
> Please help somebody, bu mailing me a running code or suggesting any
> modifications to this code.
> 


Article: 73092
Subject: Can ACEX work well in high EMI environment?
From: "Wenhui Pan" <panwenhui_shiji@163.com>
Date: Tue, 14 Sep 2004 15:06:00 +0800
Links: << >>  << T >>  << A >>
I want use ACEX to take place of MAX7000 in motion control systems. As ACEX
is based on SRAM technology, I wonder if It can work well as MAX7000, which
is used in my previous hardware version and have stable performance.



Article: 73093
Subject: Re: Would flash/antifuse-based vendors be more likely to disclose
From: Adam Megacz <megacz@cs.berkeley.edu>
Date: Tue, 14 Sep 2004 00:07:02 -0700
Links: << >>  << T >>  << A >>

Hey Nick, 441 Soda Hall just isn't the same without you.... =(

> Thus you have the encrypted bitfile loading on the Virtex lines.

Well, IMHO it doesn't qualify as encryption when the chip itself --
which you're giving to your customers -- contains the decryption key.

> Personally, I think the V4 version is easily good enough for
> protecting a $10,000 secret, and I could probably be OK comfort wise
> protecting a $100,000 secret.

$10k (loaded cost) will buy you about half a month of a mediocre
hardware engineer's time.  I doubt many of Xilinx's customers' designs
are that simple.  Even <$100k designs probably constitutes an
unimportant fraction of their market.

But I agree with your estimate.  I could envision the task of
extracting the decryption key from a Xilinx part as being a feasible
project with around $300k of funding and the right team to pull it
off.

So, basically, I wouldn't trust the security of any serious commercial
design to Xilinx's obfuscation.  Now lawyers, on the other hand... =)

  - a

Article: 73094
Subject: AHB-Slave
From: mmkumar@gmail.com (mack)
Date: 14 Sep 2004 00:12:47 -0700
Links: << >>  << T >>  << A >>
Hi,
  When the current AHB slave is busy (hready low) servicing the
Master,but if the master drives IDLE transfer in the next cycle , then
according to the protocol slave should give a zero wait state OKAY
response,but by seeing the hready high for this IDLE response ,master
will drive it's address and data.Later the slave will drive hready for
the pending(previous transfer) service.This is malfuntion the current
transfer...so it is alwayas nessacary to give a zero wait state OKAY
response for an IDLE transfer??

Regards,
M.M.Kumar

Article: 73095
Subject: Unwanted shift in multiplier
From: prasunp@csufresno.edu (Prasunp)
Date: 14 Sep 2004 00:12:56 -0700
Links: << >>  << T >>  << A >>
Hello:

I am building a add-shift multiplier in Quartus and i seem to end up
having a product that is multiplied by two or in other words is
shifted one place.  I look at my wiring and it seems right.  What
could i have messed up?

Thank You
Prasun

Article: 73096
Subject: is there a way to convert ALTERA MAXPLUS GDF file to LATTICE file?
From: "Wenhui Pan" <panwenhui_shiji@163.com>
Date: Tue, 14 Sep 2004 15:14:59 +0800
Links: << >>  << T >>  << A >>
My board is designed with ALTERA device, so my project is based on GDF files
and HDL files. now for some reasons, i must implement same funtion with
LATTICE device.  is there a tool to convert ALTERA MAXPLUS GDF file to
LATTICE graphic design file?



Article: 73097
Subject: Re: Would flash/antifuse-based vendors be more likely to disclose bitstream formats?
From: hmurray@suespammers.org (Hal Murray)
Date: Tue, 14 Sep 2004 03:05:14 -0500
Links: << >>  << T >>  << A >>
>But I agree with your estimate.  I could envision the task of
>extracting the decryption key from a Xilinx part as being a feasible
>project with around $300k of funding and the right team to pull it
>off.

How many boards would you need?

For a non high volume board, would that be enough so the vendor
would notice?

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 73098
Subject: Re: Need some help with some technical claims...
From: Mark McDougall <msmcdoug@no.spam.iinet>
Date: Tue, 14 Sep 2004 18:43:23 +1000
Links: << >>  << T >>  << A >>
glen herrmannsfeldt wrote:

> Trying to make fine distinctions between hardware and software is a
> losing proposition.  Don't do it.

Isn't that why they coined the term 'firmware'? ;)


-- 
|              Mark McDougall                | "Electrical Engineers do it
|         <http://to be announced>           |   with less resistance!"

Article: 73099
Subject: clock divider
From: "Rune Christensen" <rune.christensen@adslhome.dk>
Date: Tue, 14 Sep 2004 11:08:35 +0200
Links: << >>  << T >>  << A >>
Hello

I'm looking for information about clock dividers.

I need information about clock dividers that can divide an 100MHz clock with
for example 7812.50 (fixed point number) that gives an output of 12800Hz.

Thanks
Rune Christensen




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