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Messages from 74175

Article: 74175
Subject: Re: Altera Quartus II 4.1 double-click on QPF-File doesn't work
From: sdatta@altera.com (Subroto Datta)
Date: 5 Oct 2004 10:43:41 -0700
Links: << >>  << T >>  << A >>
hpa@terminus.zytor.com (H. Peter Anvin) wrote in message news:<cjs0ai$bom$1@terminus.zytor.com>...
> Followup to:  <ca4d800d.0408251537.2cf96975@posting.google.com>
> By author:    sdatta@altera.com (Subroto Datta)
> In newsgroup: comp.arch.fpga
> > 
> > Hi Manfred,
> > 
> >   Can you elaborate some more. When you say there is a Link, where is
> > the link and how did your create it? I have the following entries for
> > my environment variables
> > 
> > PATH %QUARTUS_ROOTDIR%\bin;
> > QUARTUS_ROOTDIR D:\quartus41
> > 
> > I have been double clicking on qpf's and launching Quartus II 4.1
> > without any problems. Also the Quartus II shortcut on my desktop
> > points to D:\quartus41\bin\quartus.exe.
> > 
> 
> I've seen this same problem.  If I clock on the .qpf file it tries to
> open the wrong application; trying to change which application is
> bound to this extension shows a list of applications which doesn't
> include Quartus; specifying the Quartus path directly via the browse
> interface doesn't work either.
> 
> This is with WinXP SP2 (spit.)
> 
> 	-hpa


Hi Peter, 

  Manfred did help us in identifying this problem. It had to do with
the usage of forward slashes in paths being used to register the
association of extensions. This problem has been fixed in the next
version of Quartus which will be released later this year.

Hope this helps,
Subroto Datta
Altera Corp.

Article: 74176
Subject: Re: Altera SDRAM controller - Only 2 words burst???
From: pinod01@sympatico.ca (Pino)
Date: 5 Oct 2004 12:25:29 -0700
Links: << >>  << T >>  << A >>
"Kenneth Land" <kland_not_this@neuralog_not_this.com> wrote in message news:<10lrfijae32bme9@news.supernews.com>...
> Hi,
> 
> No config that I'm aware of other than in the SOPC builder wizard.  I looked
> in the .ptf file and didn't see any additional settings that looked
> interesting.
> 
> Ken
> 
> "Markus Meng" <meng.engineering@bluewin.ch> wrote in message
> news:aaaee51b.0410010914.3916acce@posting.google.com...
> > Hi,
> >
> > I expected that you can initialize the burst
> > lenght after SDRAM startup. I just wonder what happens
> > in case you have a nios-II cache miss.
> > However I will have to spend some time simulating the whole bunch ...
> >
> > Configuration of SDRAM burst length is a normal step in
> > using SDRAM's, isn't it?
> >
> > Best Regards
> > Markus
> >
> > zohargolan@hotmail.com (zg) wrote in message
>  news:<e24ecb44.0409301615.7b8bccaf@posting.google.com>...
> > > Hi Ken,
> > >
> > > Thank you for your response.
> > > What frequncy are you running the NIOS? I tried simulating at 72MHz
> > > and I got only 2 words bursts.
> > > Are you using NIOS II?
> > >
> > > Regards,
> > > Zohar
> > >
> > > "Kenneth Land" <kland_not_this@neuralog_not_this.com> wrote in message
>  news:<10lg0aca67jseaa@news.supernews.com>...
> > > > "zg" <zohargolan@hotmail.com> wrote in message
> > > > news:e24ecb44.0409241455.340ba130@posting.google.com...
> > > > > Hi All,
> > > > >
> > > > > I am trying to use the SDR SDRAM controller that is comming with the
> > > > > NIOS II development package. In the simulation it looks like this
>  core
> > > > > supports only 2 words bursts. I couldn't find anything in the
> > > > > documentations.
> > > > > Am I correct?
> > > > > If this core supports bigger bursts then 2 words, any ideas what am
>  I
> > > > > doing wrong?
> > > > >
> > > > > Thank you all
> > > > > Zohar
> > > >
> > > > Zohar,
> > > >
> > > > I'm working on a design that uses one 16MB sdram chip for most of its
> > > > instruction and data memory.  I rely heavily on dma and other burst
>  reads
> > > > and writes (ie cache) to get the performance I need.
> > > >
> > > > The sdram controller you're talking about is good enough to burst 480
>  32 bit
> > > > words in under 485 cpu clocks.  It's a beautiful thing to watch in
>  Signal
> > > > Tap as I get this performance.  (Haven't explored the lenght limits
>  above
> > > > 480 - my external fifo's AlmostFull level)
> > > >
> > > > I'm hammering that sdram (through the Altera sdram controller) nines
>  ways to
> > > > Sunday and it performs flawlessly.
> > > >
> > > > I have some serious issues with the whole NiosI/II chain, but the
>  sdram
> > > > controller has been a champ.
> > > >
> > > > Ken

It is nice to hear of some progress using the Altera SDRAM controller.
 However, I must say I have not been so fortunate.   I have been
trying for some time to develop my own Master peripheral in SOPC
builder to allow reads and writes to the SDRAM on my evaluation board.
 However, there isn't any proper documentation on how to do so.  The
NIOS makes a perfect master, but I do not want the overhead cost of a
processor in my application.  Just can't afford it.  If anyone has an
example of using SignalTap and more specifically viewing the interface
of the Avalon Bus, that would help me tremendously in debugging the
interface.

Pino

Article: 74177
Subject: Re: question on interfacing FPGA with a sensor
From: John Smith <user@example.net>
Date: Tue, 05 Oct 2004 23:43:11 +0300
Links: << >>  << T >>  << A >>
Viswan wrote:
> hi,
> 
> I have a doubt on using inout ports in FPGA design. I am implementing
> an application on FPGA, that should be interfaced to SHT71(Sensirion
> humidity and temperature sensor). My FPGA gets the value of
> temperature and humidity from the sensor and calculates
> moisture(output) using certain equations.
> 
> I have designed the arithmetic unit required to calculate the moisture
> value in VHDL, and synthesized on to FPGA.  But now I have to
> interface this unit to the sensor(SHT71), and the sensor needs to have
> a controller(any microcontroller as specified in the SHT71 datasheet)
> to control its operations and get the values of temperature and
> humidity. The sensor has a bidirectional data signal as one of the
> ports, and that should be connected to the controller to send and
> receive data.  I want to implement the controller also on the same
> FPGA itself.  But is it possible?  Is it possible to handle a
> bidirectional port from an FPGA to send and receive data? I am using
> Virtex XCV800 HQ240I. Or is it suggestible to use any standard
> microcontroller as an interface between sensor and FPGA?
> 
> Any suggestion on this is highly appreciated.

Do you really need an FPGA to do the job? Wouldn't a simple uC do the 
trick cheaper and easier? Unless you need the FPGA anyway for some other 
stuff. (or if this is homework for an FPGA class ;)

Anyway, this is certainly doable in FPGA (it's an overkill, actually) 
and bi-directional I/O is not an issue. As John mentioned, the interface 
can be done easily with a simple FSM.

J.S.

> Thanks


Article: 74178
Subject: Hash algorithm for hardware?
From: statepenn99@yahoo.com (John M)
Date: 5 Oct 2004 13:57:07 -0700
Links: << >>  << T >>  << A >>
All,

I am looking for an efficient hashing algorithm that can be easily
translated to an FPGA.  The hash does not have to be cryptographically
secure, as I am just using it for a hash table lookup.  Instead, I
need it to run very fast (~25 Million hashes per second).  Does anyone
know of any resources where I could find such an algorithm?  I have
found a couple CRC-based algorithms, but I am concerned they will
result in too many collisions.  Thanks for your help.

John

Article: 74179
Subject: Re: Hash algorithm for hardware?
From: "valentin tihomirov" <spam@abelectron.com>
Date: Wed, 6 Oct 2004 00:12:24 +0300
Links: << >>  << T >>  << A >>
> Instead, I need it to run very fast (~25 Million hashes per second).

I think the speed will depend on the stream size.




Article: 74180
Subject: Re: Hash algorithm for hardware?
From: ben@ben.com (Ben Jackson)
Date: Tue, 05 Oct 2004 21:12:28 GMT
Links: << >>  << T >>  << A >>
In article <bf59e739.0410051257.67b63d89@posting.google.com>,
John M <statepenn99@yahoo.com> wrote:
>
>I am looking for an efficient hashing algorithm that can be easily
>translated to an FPGA.

Hash over what data?  A 32 bit word?  A variable length string of data?

-- 
Ben Jackson
<ben@ben.com>
http://www.ben.com/

Article: 74181
Subject: Xilinx Multiple Clock Domains
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Tue, 5 Oct 2004 14:23:03 -0700
Links: << >>  << T >>  << A >>
Is there any "how to" documents on how to negotiate a two clock domain?  I
want to run an SRAM with a 3X clock and have everything else run slower.
One of my issues is how the slower clock domain knows the phase of the
faster domain, such that data can come across the clock domain, from fast to
slow, at the right time. If I have a clock divider, such issues can be
resolved in the logic, but I am using a DCM, and the internal workings don't
seem to be as available, that is you just have two outputs, one fast, one
slow.

I also need to simulate this in ModelSim.  I haven't yet even seen the fast
clock signal appear in the signals or waveform generator.  Do I need an
upgrade?  Barring this, I suppose I could develop a component with the core
design and then drive it with a VHDL module with a fast clock and another
clock divided by three. Is this a good plan?





Article: 74182
Subject: 8-bit word to 4-digit, 7-segment display
From: mwiesbock@gmail.com (weizbox)
Date: 5 Oct 2004 14:24:30 -0700
Links: << >>  << T >>  << A >>
Hello,

Im pretty new to FPGAs in general and so far have gotten some basic
things down such as get data from my ADC and be able to hardwire
certin values into my 4 digit 7-segment display, but now I need to
combine the two and Im not sure how. Basicly I get an 8-bit binary
number from my ADC, from there how would I turn that number into
usable values to display on my 4-digit 7-segment display? Im using a
refence voltage value of 2.55 V just to make it easier for the time
being, but how do I turn "11111111" into "2.550" on ym display?

Thank you much for your time,
Mark

Article: 74183
Subject: Re: 8-bit word to 4-digit, 7-segment display
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 5 Oct 2004 14:34:57 -0700
Links: << >>  << T >>  << A >>
Mark,
How about this? If you're using a Xilinx part with 18 kbit BlockRAMs, use
one as a 512x36 bit ROM. Stick your ADC value into the address pins, use the
data pins to drive the LEDS. All(!) you need to do is initialise the ROM
with the right data and away you go. Don't forget to clock the ROM, it's
synchronous.
Cheers, Syms.
"weizbox" <mwiesbock@gmail.com> wrote in message
news:335c6753.0410051324.57cf0ea8@posting.google.com...
> Hello,
>
> Im pretty new to FPGAs in general and so far have gotten some basic
> things down such as get data from my ADC and be able to hardwire
> certin values into my 4 digit 7-segment display, but now I need to
> combine the two and Im not sure how. Basicly I get an 8-bit binary
> number from my ADC, from there how would I turn that number into
> usable values to display on my 4-digit 7-segment display? Im using a
> refence voltage value of 2.55 V just to make it easier for the time
> being, but how do I turn "11111111" into "2.550" on ym display?
>
> Thank you much for your time,
> Mark



Article: 74184
Subject: Re: Xilinx Multiple Clock Domains
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 5 Oct 2004 14:40:18 -0700
Links: << >>  << T >>  << A >>
Brad,
Have you considered having just one fast 3X clock for all your design? Just
use a clock enable to enable the slower stuff every third cycle. This make
fixing all the problems you mention a breeze! Also, you might like to read
the Xilinx documentation on Multi-cycle paths.
Cheers, Syms.
"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message
news:10m6469iorejaa9@corp.supernews.com...
> Is there any "how to" documents on how to negotiate a two clock domain?  I
> want to run an SRAM with a 3X clock and have everything else run slower.
> One of my issues is how the slower clock domain knows the phase of the
> faster domain, such that data can come across the clock domain, from fast
to
> slow, at the right time. If I have a clock divider, such issues can be
> resolved in the logic, but I am using a DCM, and the internal workings
don't
> seem to be as available, that is you just have two outputs, one fast, one
> slow.
>
> I also need to simulate this in ModelSim.  I haven't yet even seen the
fast
> clock signal appear in the signals or waveform generator.  Do I need an
> upgrade?  Barring this, I suppose I could develop a component with the
core
> design and then drive it with a VHDL module with a fast clock and another
> clock divided by three. Is this a good plan?



Article: 74185
Subject: Sine function implementation in FPGA??
From: sourabh.dhir@gmail.com (SD)
Date: 5 Oct 2004 15:30:26 -0700
Links: << >>  << T >>  << A >>
Hi,
I am trying to implement a DSP algorithm in a FPGA. My algorithm has
sine and cosine functions in it. Can somebody help me in implementing
sine and cosine functions in MATLAB fixed point (using fixed point
toolbox) or VHDL.
Thanks,
SD

Article: 74186
Subject: Re: Xilinx Multiple Clock Domains
From: Austin Lesea <austin@xilinx.com>
Date: Tue, 05 Oct 2004 15:47:58 -0700
Links: << >>  << T >>  << A >>
Brad,

All DCM outputs are phase aligned.

So, for example, if you use the CLK0 output, and the CLKFX output with 
M=3/D=1, every time CLK0 has a rising edge, there will be a rising edge 
for the CLKFX +/- the jitter of the DCM.

Or saying it differently, every third edge of the CLKFX corresponds to a 
CLK0 edge.

That is why the DCM is useful, is that it phase aligns everything to 
known phases and known phase alignments.

This accuracy in alignment is covered in the DCM specifications, as the 
skew between DCM outputs, in the datasheet.

Austin

Brad Smallridge wrote:
> Is there any "how to" documents on how to negotiate a two clock domain?  I
> want to run an SRAM with a 3X clock and have everything else run slower.
> One of my issues is how the slower clock domain knows the phase of the
> faster domain, such that data can come across the clock domain, from fast to
> slow, at the right time. If I have a clock divider, such issues can be
> resolved in the logic, but I am using a DCM, and the internal workings don't
> seem to be as available, that is you just have two outputs, one fast, one
> slow.
> 
> I also need to simulate this in ModelSim.  I haven't yet even seen the fast
> clock signal appear in the signals or waveform generator.  Do I need an
> upgrade?  Barring this, I suppose I could develop a component with the core
> design and then drive it with a VHDL module with a fast clock and another
> clock divided by three. Is this a good plan?
> 
> 
> 
> 

Article: 74187
Subject: Re: Sine function implementation in FPGA??
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 5 Oct 2004 16:03:16 -0700
Links: << >>  << T >>  << A >>
Dear SD,
Try http://www.google.com/grphp
Put this in the search box :-
sine generation group:comp.arch.fpga
Isn't the internet great?
Cheers, Syms.
"SD" <sourabh.dhir@gmail.com> wrote in message
news:cb01307e.0410051430.7ab8037e@posting.google.com...
> Hi,
> I am trying to implement a DSP algorithm in a FPGA. My algorithm has
> sine and cosine functions in it. Can somebody help me in implementing
> sine and cosine functions in MATLAB fixed point (using fixed point
> toolbox) or VHDL.
> Thanks,
> SD



Article: 74188
Subject: Re: Sine function implementation in FPGA??
From: Ray Andraka <ray@andraka.com>
Date: Tue, 05 Oct 2004 19:14:29 -0400
Links: << >>  << T >>  << A >>
How many bits precision do you need?  How many angles, or what is the
angular resolution you need?  How about the angular range if less than
+/-pi?  There are several ways of obtaining the sine.  For lower angular
resolution, a look up table works fine if you have the on-chip memory
available.  There are also several approximations (one that I've used is
a two step linear approximation with a correction that uses two fairly
small look-ups).  You can also compute the sign algorithmically using a
CORDIC rotation at the expense of more latency.  If your design needs to
multiply some signal by a sine, say a mixer and local oscillator, then
CORDIC might be advantageous as it can accomplish both the sine and the
multiply in one operation.  I have papers on my website on CORDIC and a
Xilinx XCELL article I wrote on using CORDIC as a mixer in a digital
radio app.  For behavioral VHDL, you can use the sine and cosine
functions in ieee.math_real...those are computed using CORDIC in that
package, by the way.

SD wrote:

> Hi,
> I am trying to implement a DSP algorithm in a FPGA. My algorithm has
> sine and cosine functions in it. Can somebody help me in implementing
> sine and cosine functions in MATLAB fixed point (using fixed point
> toolbox) or VHDL.
> Thanks,
> SD

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 74189
Subject: Re: Xilinx Multiple Clock Domains
From: Ray Andraka <ray@andraka.com>
Date: Tue, 05 Oct 2004 19:22:35 -0400
Links: << >>  << T >>  << A >>
Austin,

Has the possibility of skew between the 1x and Nx clock due to loading and input
jitter been eliminated then?  I had a problem back when SpartanII was first
released with a design where the incoming clock had enough jitter on it
(introduced apparently by switching of outputs on the same bank as the clock pin)
and vastly different loading on the 1x and 2x clocks so that I had problems
crossing clock domains where I had a flip flop in one domain driving the direct
input of a flip-flop in the other domain via the direct slice to slice connect
inside a clb.  Ever since then, I have been very careful about crossing domains
even if they are generated by the same DLL/DCM.

One way to do it is to make a copy of the slower clock in the faster clock domain,
and then use that for clock enables to make sure the signal is sensed away from
the edge where it changes.



Austin Lesea wrote:

> Brad,
>
> All DCM outputs are phase aligned.
>
> So, for example, if you use the CLK0 output, and the CLKFX output with
> M=3/D=1, every time CLK0 has a rising edge, there will be a rising edge
> for the CLKFX +/- the jitter of the DCM.
>
> Or saying it differently, every third edge of the CLKFX corresponds to a
> CLK0 edge.
>
> That is why the DCM is useful, is that it phase aligns everything to
> known phases and known phase alignments.
>
> This accuracy in alignment is covered in the DCM specifications, as the
> skew between DCM outputs, in the datasheet.
>
> Austin
>
> Brad Smallridge wrote:
> > Is there any "how to" documents on how to negotiate a two clock domain?  I
> > want to run an SRAM with a 3X clock and have everything else run slower.
> > One of my issues is how the slower clock domain knows the phase of the
> > faster domain, such that data can come across the clock domain, from fast to
> > slow, at the right time. If I have a clock divider, such issues can be
> > resolved in the logic, but I am using a DCM, and the internal workings don't
> > seem to be as available, that is you just have two outputs, one fast, one
> > slow.
> >
> > I also need to simulate this in ModelSim.  I haven't yet even seen the fast
> > clock signal appear in the signals or waveform generator.  Do I need an
> > upgrade?  Barring this, I suppose I could develop a component with the core
> > design and then drive it with a VHDL module with a fast clock and another
> > clock divided by three. Is this a good plan?
> >
> >
> >
> >

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 74190
Subject: Re: Xilinx Multiple Clock Domains
From: Philip Freidin <philip@fliptronics.com>
Date: Wed, 06 Oct 2004 00:07:30 GMT
Links: << >>  << T >>  << A >>
On Tue, 5 Oct 2004 14:23:03 -0700, "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote:
>Is there any "how to" documents on how to negotiate a two clock domain?

You may find the following useful.

   http://www.fpga-faq.com/FAQ_Pages/0017_Tell_me_about_metastables.htm

Crossing clock domains is also discussed in several documents linked at
the bottom of the above referenced page.

Philip

===================
Philip Freidin
philip.freidin@fpga-faq.com
Host for WWW.FPGA-FAQ.COM

Article: 74191
Subject: PCI Transactor
From: "fabble" <no@no.com>
Date: Wed, 06 Oct 2004 00:34:35 GMT
Links: << >>  << T >>  << A >>
Hi,
    I'm looking for information on these. Has anyone here used one? What 
experiences have you had? We are looking into how feasible it would be to 
build a System C platform using a PCI bus.

Thanks 



Article: 74192
Subject: Re: 8-bit word to 4-digit, 7-segment display
From: hpa@terminus.zytor.com (H. Peter Anvin)
Date: Wed, 6 Oct 2004 01:18:01 +0000 (UTC)
Links: << >>  << T >>  << A >>
Followup to:  <335c6753.0410051324.57cf0ea8@posting.google.com>
By author:    mwiesbock@gmail.com (weizbox)
In newsgroup: comp.arch.fpga
>
> Hello,
> 
> Im pretty new to FPGAs in general and so far have gotten some basic
> things down such as get data from my ADC and be able to hardwire
> certin values into my 4 digit 7-segment display, but now I need to
> combine the two and Im not sure how. Basicly I get an 8-bit binary
> number from my ADC, from there how would I turn that number into
> usable values to display on my 4-digit 7-segment display? Im using a
> refence voltage value of 2.55 V just to make it easier for the time
> being, but how do I turn "11111111" into "2.550" on ym display?
> 

Since you only have 256 possible input values, you're probably best
off munching up a 4Kbit blockram (in 256x16 configuration) outputting
4-digit BCD.  Then convert to 7's segment; a LUT per segment handles
that using the obvious Verilog or VHDL model (remove ~ if your display
isn't inverted.)

module hexled (
               value,
               s7
               );

   input [3:0]   value;
   output [6:0]  s7;
   reg [6:0]     s7;

   always @( value )
     begin
        case ( value )
          4'h0: s7 = ~7'b0111111;
          4'h1: s7 = ~7'b0000110;
          4'h2: s7 = ~7'b1011011;
          4'h3: s7 = ~7'b1001111;
          4'h4: s7 = ~7'b1100110;
          4'h5: s7 = ~7'b1101101;
          4'h6: s7 = ~7'b1111101;
          4'h7: s7 = ~7'b0000111;
          4'h8: s7 = ~7'b1111111;
          4'h9: s7 = ~7'b1101111;
          4'hA: s7 = ~7'b1110111;
          4'hB: s7 = ~7'b1111100;
          4'hC: s7 = ~7'b0111001;
          4'hD: s7 = ~7'b1011110;
          4'hE: s7 = ~7'b1111001;
          4'hF: s7 = ~7'b1110001;
        endcase
     end
endmodule // hexled

Article: 74193
Subject: Re: Hash algorithm for hardware?
From: hpa@terminus.zytor.com (H. Peter Anvin)
Date: Wed, 6 Oct 2004 01:22:17 +0000 (UTC)
Links: << >>  << T >>  << A >>
Followup to:  <bf59e739.0410051257.67b63d89@posting.google.com>
By author:    statepenn99@yahoo.com (John M)
In newsgroup: comp.arch.fpga
> 
> I am looking for an efficient hashing algorithm that can be easily
> translated to an FPGA.  The hash does not have to be cryptographically
> secure, as I am just using it for a hash table lookup.  Instead, I
> need it to run very fast (~25 Million hashes per second).  Does anyone
> know of any resources where I could find such an algorithm?  I have
> found a couple CRC-based algorithms, but I am concerned they will
> result in too many collisions.  Thanks for your help.
> 

Use a wider CRC?  What is your collision metric?  For statistically
collisionless hashing, you need to keep in mind the birthday paradox,
which states that if you have N items, you have ~50% chance of
collision with N^2 hash values; this is functionally equivalent to
saying that if you have 2^n items you want >> 2n bits of hash.

	-hpa

Article: 74194
Subject: Xilinx ISE WebPACK vs. Altera's Quartus II Web Edition.
From: "Antti Karttunen (remove the trailing .do from the address)" <Antti.Karttunen@iki.fi.do>
Date: Wed, 06 Oct 2004 04:25:24 +0300
Links: << >>  << T >>  << A >>

OK, now I did some homework, and can ask more
sensible questions.

Especially, I found the page
http://www.fpga-faq.com/FAQ_Pages/0024_Schematics_vs_Verilog_VHDL.htm
and there it says:
"You have 4 basic options (for implementing designs): HDL,
state machine, schematic, or FPGA editor. These roughly
correspond to decreasing levels of abstraction."
And from http://www.xilinx.com/ise/devsys_feature_guide.pdf
it seems to be clear that only the first three options
are supported by ISE WebPack.

How about the "CORE Generator System", which refers to 
http://toolbox.xilinx.com/docsan/xilinx6/help/iseguide/html/fd_core_intro.htm 
and is also missing from WebPACK.
Can I find similar macros/modules (?) for "adders, accumulators and 
multipliers, filters, transforms and memories" from some Open source,
or create my own reusable macro/module library if I eventually have to 
design some of them by myself?


Then to Altera's Quartus II (Free) Web Edition.
Is its software license TIME-LIMITED or not?
Which of those four levels of design,
"HDL, state machine, schematic, or FPGA editor"
it does support?

Can I run it under WINE in Linux, as WebPACK can be run?
(see 
http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&threadm=pan.2004.08.24.15.31.25.34232%40polybus.com&rnum=1&prev=/groups%3Fq%3D%2522Xilinx%2Bon%2Blinux%2522%26hl%3Den%26lr%3D%26ie%3DUTF-8%26group%3Dcomp.arch.fpga%26sa%3DG%26scoring%3Dd 
)


Martin Schoeberl kindly answered to my previous questions:
> 
> The very nice feature of both solution is that they are free! The
> simplest way to get your questions answered is just download both and try
> out your design. 

After reading some horror stories of Xilinx development software
license-related uninstallation/reinstallation troubles (see
http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&threadm=9juddd%24357%241%40slb6.atl.mindspring.net&rnum=3&prev=/groups%3Fq%3DXilinx%2Breinstall%2Blicense%26hl%3Den%26lr%3D%26ie%3DUTF-8%26group%3Dcomp.arch.fpga%26sa%3DG%26scoring%3Dd
on this newsgroup), I want to be sure that I can install the ISE 
Foundation Evaluation version (that comes with Spartan-3 Starter Kit)
any time at _future_, even although I would _already_ have ISE WebPACK
installed on my disk, even although it would be older version (than
ISE Foundation). Is that kind of separate installation
of ISE WebPACK and ISE Foundation (Evaluation version) possible,
or are they bungled under the same installation
package/software on those CDs?


> After this experiment ask yourself if you really want to
> struggle with the placement of the cells. The P&R tools are pretty smart
> now.

I might do, eventually, after getting a few years of experience,
especially if I'll experiment with simple, homogeneous
CA-systems. Maybe then I will have $XXXX to invest to
the complete design systems.

> 
> Martin
> ----------------------------------------------
> JOP - a Java Processor core for FPGAs:
> http://www.jopdesign.com/
> 

Yours,

Antti

Article: 74195
Subject: Re: [NIOS-II SOPC] SDRAM Read Burst Cycle Length ...
From: "Kenneth Land" <kland_not_this@neuralog_not_this.com>
Date: Tue, 5 Oct 2004 20:36:08 -0500
Links: << >>  << T >>  << A >>

Hi David,

Sorry for the delay I've been out of town with no access.

I'm using the standared included dma peripheral to empty a standard single
clock fifo.  I did not modify any of the master priorities.vr

I can post a test project to the Nios Forum that runs on the Cyclone devkit
board, but I don't have time to document it very well.

If anyone is in a bind they can contact me through the forum and I will
email them a .zip of the project.  (~4MB)

The credit for this perfect performance goes mostly to an Engineer at Altera
who worked with me for over a week until we had it perfect.

One thing was that Read_Latency="1" had to be added to the Interface to User
Logic settings. (see below for the entire settings list)

Ken

         SYSTEM_BUILDER_INFO
         {
            Bus_Type = "avalon";
            Address_Alignment = "dynamic";
            Address_Width = "2";
            Data_Width = "32";
            Has_IRQ = "1";
            Base_Address = "0x010019A0";
            Has_Base_Address = "1";
            Read_Latency = "1";
            Read_Wait_States = "0.0cycles";
            Write_Wait_States = "0.0cycles";
            Setup_Time = "0.0cycles";
            Hold_Time = "0.0cycles";
            Is_Memory_Device = "1";
            Uses_Tri_State_Data_Bus = "0";
            Is_Enabled = "1";
            MASTERED_BY SCAN_IN_DMA/read_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "0";
            }
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
         }


"David Brown" <david@no.westcontrol.spam.com> wrote in message
news:cjrh8o$ck5$1@news.netpower.no...
>
> "Kenneth Land" <kland_not_this@neuralog_not_this.com> wrote in message
> news:10lnrtjlg7sff75@news.supernews.com...
> >
> > "Markus Meng" <meng.engineering@bluewin.ch> wrote in message
> > news:aaaee51b.0409290819.a6020e5@posting.google.com...
> > > Hi all [SOPC users],
> > >
> > > is there a way a can configure the read burst length of the
> > > standard SDRAM controller within SOPC 4.1?
> > >
> > > Best Regards
> > > Markus
> >
> > Hi Markus,
> >
> > You might try asking this over on the Nios Forum (www.niosforum.com).
I'd
> > like to know the answer as well.  I looked through the controller's
> > class.ptf file and even the verilog source and don't see anything.
> >
> > On writes however, I'm getting bursts of at least 480 long words at one
> > clock per word.  (my system is running at 75MHz)
> >
>
> Did you have to do anything special to achieve that?  I have a custom
> peripheral that is writing as fast as it can to the sdram, but I'm getting
> one 32-bit write every 3 clocks.  With the prototype system I have at the
> moment, that's good enough, but I'd like to improve on it when we start
> making the real thing.  When reading, I'm getting one read every 2
clocks -
> again, it's not ideal but it works.  I'd expect one read/write per clock
for
> most of the burst, with some waits while changing banks or refreshing.
>
> Also, my reader and writer peripherals are independant, so sometimes they
> coincide.  The Avalone bus arbitration apparently cannot take bursting
into
> account, and swaps between the two accesses.  Is there any way this can be
> improved upon, or do I have to implement my own mini-arbitrator to control
> the two peripherals?
>
>
>



Article: 74196
Subject: Re: Xilinx Multiple Clock Domains
From: "Kevin Neilson" <kevin_neilson@removethiscomcast.net>
Date: Wed, 06 Oct 2004 01:54:12 GMT
Links: << >>  << T >>  << A >>
I would answer that NO, the skew has not been eliminated.  The literature
gives the impression that all the DCM outputs are perfectly phase-aligned
when it appears to be just not true.  How can it be?  The DCM can only
account for the delay across the BUFG *in its feedback path*.  That means
only the CLK0 or CLK2X can be perfectly phase-aligned, and not even the
latter in the V2Pro because of the erratum disallowing the use of CLK2X for
the feedback.  The other outputs (CLKFX, CLKDV) have different loads and
should have different delays across their respective BUFGs.  I don't see how
they could possibly be aligned with the input.

I recently had a problem on a V2Pro trying to transfer data from a 2X domain
to a 1X domain, where both domains were driven by DCMs.  The transfers had
multiple errors indicating that the skew between the domains was too large.
I resolved the problem by transferring across domains away from the edge of
the receiving domain.  Everything I have read implies that this isn't
necessary.

Creating a copy of the slow clock in the fast domain is the method I use.
The slow clock has to be sampled; actually I think I sampled the CLK90 or
one of those to ensure I meet setup.  With the copied clock I can always do
the transfer in the middle of the slow clock cycle (or, in the poster's
case, on the first third of the slow clock's cycle).

The DCMs work very well; I just think that the caveats for their use are not
well-specified.  An app-note explaining the clock-copying method Ray
describes would be very helpful, if such a note does not yet exist.
-Kevin

"Ray Andraka" <ray@andraka.com> wrote in message
news:41632CBB.AD3368E0@andraka.com...
> Austin,
>
> Has the possibility of skew between the 1x and Nx clock due to loading and
input
> jitter been eliminated then?  I had a problem back when SpartanII was
first
> released with a design where the incoming clock had enough jitter on it
> (introduced apparently by switching of outputs on the same bank as the
clock pin)
> and vastly different loading on the 1x and 2x clocks so that I had
problems
> crossing clock domains where I had a flip flop in one domain driving the
direct
> input of a flip-flop in the other domain via the direct slice to slice
connect
> inside a clb.  Ever since then, I have been very careful about crossing
domains
> even if they are generated by the same DLL/DCM.
>
> One way to do it is to make a copy of the slower clock in the faster clock
domain,
> and then use that for clock enables to make sure the signal is sensed away
from
> the edge where it changes.
>
>
>
> Austin Lesea wrote:
>
> > Brad,
> >
> > All DCM outputs are phase aligned.
> >
> > So, for example, if you use the CLK0 output, and the CLKFX output with
> > M=3/D=1, every time CLK0 has a rising edge, there will be a rising edge
> > for the CLKFX +/- the jitter of the DCM.
> >
> > Or saying it differently, every third edge of the CLKFX corresponds to a
> > CLK0 edge.
> >
> > That is why the DCM is useful, is that it phase aligns everything to
> > known phases and known phase alignments.
> >
> > This accuracy in alignment is covered in the DCM specifications, as the
> > skew between DCM outputs, in the datasheet.
> >
> > Austin
> >
> > Brad Smallridge wrote:
> > > Is there any "how to" documents on how to negotiate a two clock
domain?  I
> > > want to run an SRAM with a 3X clock and have everything else run
slower.
> > > One of my issues is how the slower clock domain knows the phase of the
> > > faster domain, such that data can come across the clock domain, from
fast to
> > > slow, at the right time. If I have a clock divider, such issues can be
> > > resolved in the logic, but I am using a DCM, and the internal workings
don't
> > > seem to be as available, that is you just have two outputs, one fast,
one
> > > slow.
> > >
> > > I also need to simulate this in ModelSim.  I haven't yet even seen the
fast
> > > clock signal appear in the signals or waveform generator.  Do I need
an
> > > upgrade?  Barring this, I suppose I could develop a component with the
core
> > > design and then drive it with a VHDL module with a fast clock and
another
> > > clock divided by three. Is this a good plan?
> > >
> > >
> > >
> > >
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759
>
>



Article: 74197
Subject: Re: Hash algorithm for hardware?
From: "bh" <spam_not@nosuch.com>
Date: Wed, 06 Oct 2004 02:00:30 GMT
Links: << >>  << T >>  << A >>
The hardware implementation would be greatly simplified if
you can be sure there are no collisions. However, this is only
practical if you know a 'worst case table', for example
something like a word list. If you do, there are things called
"perfect hash function generators". These create a hash function
that is guaranteed to hit first time on each hash. You need to
give an input table, a hash table size, and lots-o-cpu to calculate
the function parameters. Take a look at the Gnu Perfect
Hash generator (gperf) as an example:

http://mirror.sit.wisc.edu/mirrors/gnu/Manuals/gperf-2.7/text/gperf.txt

-bh


"H. Peter Anvin" <hpa@terminus.zytor.com> wrote in message
news:cjvhc9$ven$1@terminus.zytor.com...
> Followup to:  <bf59e739.0410051257.67b63d89@posting.google.com>
> By author:    statepenn99@yahoo.com (John M)
> In newsgroup: comp.arch.fpga
> >
> > I am looking for an efficient hashing algorithm that can be easily
> > translated to an FPGA.  The hash does not have to be cryptographically
> > secure, as I am just using it for a hash table lookup.  Instead, I
> > need it to run very fast (~25 Million hashes per second).  Does anyone
> > know of any resources where I could find such an algorithm?  I have
> > found a couple CRC-based algorithms, but I am concerned they will
> > result in too many collisions.  Thanks for your help.
> >
>
> Use a wider CRC?  What is your collision metric?  For statistically
> collisionless hashing, you need to keep in mind the birthday paradox,
> which states that if you have N items, you have ~50% chance of
> collision with N^2 hash values; this is functionally equivalent to
> saying that if you have 2^n items you want >> 2n bits of hash.
>
> -hpa



Article: 74198
Subject: Re: Sine function implementation in FPGA??
From: "Kevin Neilson" <kevin_neilson@removethiscomcast.net>
Date: Wed, 06 Oct 2004 02:01:26 GMT
Links: << >>  << T >>  << A >>
If a BRAM lookup isn't precise enough, a method I've seen used is a 5- or
6-term Maclaurin series using the Horner method.  You need embedded
multipliers for this though.  You can use one multiplier, or one for each
term for a fully parallel implementation.  It all depends how fast you want
to do it.  The CORDIC probably uses a lot less hardware.  If you have extra
embedded multipliers, though, you can be lazy.

"SD" <sourabh.dhir@gmail.com> wrote in message
news:cb01307e.0410051430.7ab8037e@posting.google.com...
> Hi,
> I am trying to implement a DSP algorithm in a FPGA. My algorithm has
> sine and cosine functions in it. Can somebody help me in implementing
> sine and cosine functions in MATLAB fixed point (using fixed point
> toolbox) or VHDL.
> Thanks,
> SD



Article: 74199
Subject: Re: FPGA vs ASIC area
From: brimdavis@aol.com (Brian Davis)
Date: 5 Oct 2004 19:10:41 -0700
Links: << >>  << T >>  << A >>
John H wrote:
> >
> > That is right.  Did you make the same comment to Austin?
> 
> Honestly, no.  To me, you appear to be the one predisposed to
> being argumentative in the posts back and forth.
>

 I'd have to side with Rick on this one - Austin's 'bad hair day'
comment is what prompted Rick's response.

 Personally, I can easily ignore Austin's marketing spiels.

 My real beef with Austin is when he flames up an accurate technical
post with an insult-and-opinion laden response, for no apparent reason
other than to spread FUD when someone has taken the time and effort
to document tool or device problems about which Xilinx has been less
than forthcoming.

 He makes lots of noise when you point out the flaws in his reasoning,
yet when you pin him down by asking a detailed technical question, he
becomes strangely silent.

Brian



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