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Messages from 53675

Article: 53675
Subject: Using FPGAs as coprocessors in a PC
From: roy hansen <royhansen@removethis_norway.online.no>
Date: Wed, 19 Mar 2003 21:24:42 +0100
Links: << >>  << T >>  << A >>

Hi,

I am new to FPGAs.

Is it possible to buy a PCI card with one (or several) FPGAs,
such that the card works as a coprocessor running a single 
routine callable from other programs (i.e. matlab)?

If so, what is the typical speed increase I can hope for 
compared to a state-of-the-art 1 CPU PC (i.e. P4 3GHz).
I know this is heavily dependent on the routine (see below).

Which card should I look into?

How much work is it to program the FPGAs 
(by an expert - not me). 

My routine contains simple arithmetics in single precision
floating point (sines, cosines, square roots, multiplications 
and additions) and is extremely easy to parallelize (it's sonar 
beamforming). It could be made into fixed point if floating 
point is a large problem. The sines and cosines could also 
be replaced by table lookup. 

Sorry about all the stupid questions - I'm trying to figure
out whether FPGAs are the solution to all my problems in life :-) 

-Roy


Article: 53676
Subject: Re: Quartus2 : assigning I/O pins
From: creon100@yahoo.com (Sean)
Date: 19 Mar 2003 12:36:08 -0800
Links: << >>  << T >>  << A >>
I'm having the same problem.  I've edited my .csf file to include the
pin assignments, but Quartus-II still just does its own thing and puts
them anywhere it pleases.  This is really starting to annoy me.  I
never had this much trouble assigning Xilinx pins (not to start a X
vs. A thing, just that something this simple shouldn't be such a
headache to do.)

Rene Tschaggelar <tschaggelar@dplanet.ch> wrote in message news:<f2540360cc20015c63197654b369a513@news.teranews.com>...
> Is there a quick way to assign a lot of pins to signals ?
> Especially changing the pin say from input to output or
> bidirectional is tedious for dozends of them.
> Eg is there a file to be edited ?
> 
> Rene

Article: 53677
Subject: Re: FPGA specs
From: "Graeme" <graeme@spamoff.fsnet.co.uk>
Date: Wed, 19 Mar 2003 21:22:25 -0000
Links: << >>  << T >>  << A >>
"geeko" <jibin@ushustech.com> wrote in message
news:b59525$26k0i5$1@ID-159027.news.dfncis.de...
> hi all
> What is the difference between he Typical gates and Maximum System gates
> specifications
> For Altera EPXA1 these ratings are 100K and 263K respectively  what may be
> the available gates for programming
> regards
> geeko
>

The other groups that you've cross-posted to should certainly have the info
you need. As would Altera if you ask them!




Article: 53678
Subject: Re: Using FPGAs as coprocessors in a PC
From: Ray Andraka <ray@andraka.com>
Date: Wed, 19 Mar 2003 21:37:06 GMT
Links: << >>  << T >>  << A >>
It is possible to buy a PCI card and use it as a sonar beamformer
coprocessor, just like you are suggesting (for one such coprocessor,
see the sonar design in the floorplan gallery on my website at
http://www.andraka.com/sonar_processor.htm).  You'll want to do that
in fixed point to keep the logic less gnarly.  The bottleneck may be
the transfer speeds getting the data in and out of the coprocessor
rather than the coprocessor's speed.  You'll want to use a board that
has sufficient memory on the card for you to write the raw data to
the card and then fetch the processed data when done.  You can get to
a working design using vendor supplied macros (if you are going that
route, I'd recommend using the Xilinx system generator to make your
job easier), however unless you are very familiar with hardware DSP
design and FPGA design you may be somewhat dissappointed by the
resulting performance and density.  The website design is a
VirtexII-6000.  The beamformer is the logic in the lower right
corner.  The large part of the design is doing voxel interpolation to
get 400 sub-voxels per voxel.


roy hansen wrote:

> Hi,
>
> I am new to FPGAs.
>
> Is it possible to buy a PCI card with one (or several) FPGAs,
> such that the card works as a coprocessor running a single
> routine callable from other programs (i.e. matlab)?
>
> If so, what is the typical speed increase I can hope for
> compared to a state-of-the-art 1 CPU PC (i.e. P4 3GHz).
> I know this is heavily dependent on the routine (see below).
>
> Which card should I look into?
>
> How much work is it to program the FPGAs
> (by an expert - not me).
>
> My routine contains simple arithmetics in single precision
> floating point (sines, cosines, square roots, multiplications
> and additions) and is extremely easy to parallelize (it's sonar
> beamforming). It could be made into fixed point if floating
> point is a large problem. The sines and cosines could also
> be replaced by table lookup.
>
> Sorry about all the stupid questions - I'm trying to figure
> out whether FPGAs are the solution to all my problems in life :-)
>
> -Roy

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 53679
Subject: Re: Bit patching of Xilinx VIRTEX-II devicex?
From: Ray Andraka <ray@andraka.com>
Date: Wed, 19 Mar 2003 21:41:14 GMT
Links: << >>  << T >>  << A >>
We try to avoid bitstream mods in our designs.  If you replace CLB ROMs
with SRL16's you can serially shift new ROM contents into the LUT.  When
not shifting, the SRL16 behaves exactly like a LUT.  For larger ROM
implemented in BRAM, you can use the second BRAM port to reload the ROM.
The advantage of doing it this way is that it is simulatable with the
mainstream tools, and it doesn't require any bitstream manipulation (which
can be a pain).  The disadvantage is a small overhead in the logic to
support the program path.

Koen Van Renterghem wrote:

> Hello,
>
> I'am currently working on a project that will be implemented in a
> Xilinx Virtex-II device. I've previously used 'bit patching' on a
> Virtex component (patching an existing configuration file with a
> microcontroller so you can alter the the contents of ROMs and other
> components - see Xilinx Application note 151). I cannot find any
> information about bit patching Virtex-II configuration files. Has
> anybody attempted this before? Will Xilinx release such information as
> it did with the Virtex?

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 53680
Subject: Re: Quartus2 : assigning I/O pins
From: "jonno" <jjacox@NULLpmdi.com>
Date: Wed, 19 Mar 2003 21:48:52 GMT
Links: << >>  << T >>  << A >>
I read the link that was posted and the third message explains what I do. I
create a .tcl file (text editor) and then run it in the Quartus TCL Console
window. Works great, especially for busses because you can put the pin
assignments in a loop.

  jon

"Sean" <creon100@yahoo.com> wrote in message
news:b97bab2f.0303191236.587c1bd0@posting.google.com...
> I'm having the same problem.  I've edited my .csf file to include the
> pin assignments, but Quartus-II still just does its own thing and puts
> them anywhere it pleases.  This is really starting to annoy me.  I
> never had this much trouble assigning Xilinx pins (not to start a X
> vs. A thing, just that something this simple shouldn't be such a
> headache to do.)
>
> Rene Tschaggelar <tschaggelar@dplanet.ch> wrote in message
news:<f2540360cc20015c63197654b369a513@news.teranews.com>...
> > Is there a quick way to assign a lot of pins to signals ?
> > Especially changing the pin say from input to output or
> > bidirectional is tedious for dozends of them.
> > Eg is there a file to be edited ?
> >
> > Rene



Article: 53681
Subject: Re: Quartus2 : assigning I/O pins
From: Prager Roman <rprager@frequentis.com>
Date: Wed, 19 Mar 2003 21:49:46 GMT
Links: << >>  << T >>  << A >>
Sean <creon100@yahoo.com> wrote:
> I'm having the same problem.  I've edited my .csf file to include the
> pin assignments, but Quartus-II still just does its own thing and puts
> them anywhere it pleases.  This is really starting to annoy me.  I
> never had this much trouble assigning Xilinx pins (not to start a X
> vs. A thing, just that something this simple shouldn't be such a
> headache to do.)
This sounds strange, I never had such a problem.
If you look in the window "pin assignment" in Quartus, do you see your
assignments from the csf- file there?

Roman

Article: 53682
Subject: Re: Quartus2 : assigning I/O pins
From: "gallenm" <gallenm@ic24.net>
Date: Wed, 19 Mar 2003 22:01:09 -0000
Links: << >>  << T >>  << A >>
Hi Rene

Let Quartus assign all the pins automatically by itself first.
Then open up the .csf file using Quartus and edit it to whatever
you want the pin assignments to be. Save the .csf file and then
close your project. Re-open the project again, and Quartus will
pick up the new settings. That should work.

I've been through all that pain before, but once you get used
to it, Quartus is a good P&R application.

Regards
Michael Gallen
Tyder Ltd
www.tyder.com

"Rene Tschaggelar" <tschaggelar@dplanet.ch> wrote in message
news:f2540360cc20015c63197654b369a513@news.teranews.com...
> Is there a quick way to assign a lot of pins to signals ?
> Especially changing the pin say from input to output or
> bidirectional is tedious for dozends of them.
> Eg is there a file to be edited ?
>
> Rene
> --
> Ing.Buero R.Tschaggelar - http://www.ibrtses.com
> & commercial newsgroups - http://www.talkto.net
>



Article: 53683
Subject: Re: unsupported switches of PAR
From: Steve Lass <lass@xilinx.com>
Date: Wed, 19 Mar 2003 15:33:00 -0700
Links: << >>  << T >>  << A >>
Petter Gustad wrote:

>I hope that the -m option will be supported in the rumored native
>Linux version 
>
The good news is that native Linux is not a rumor.  It will be delivered 
in our 6.1 release in September.

However, the -m option will not be supported  in the first release. 
 It's on our roadmap, but did not
make the cut because there is a workaround (write a script that sends 
each job separately to each
machine using a different cost table).

Steve

>(i.e. not a Windows version using Wine). Or even better
>yet, a more fine grained parallel version of PaR for clusters where
>also a single iteration will be distributed.
>


Article: 53684
Subject: Re: About automatically programming my FPGA
From: running_prince@hotmail.com (Turgut Abacioglu)
Date: 19 Mar 2003 15:10:32 -0800
Links: << >>  << T >>  << A >>
hmurray@suespammers.org (Hal Murray) wrote in message news:<v58hsg4uo6fl91@corp.supernews.com>...
> >Also, TCP may be hairy and complicated, but the MINIMUM isn't that
> >nasty.  If you keep window size at 0, ack packets one at a time, you
> >get cruddy throughput, but you get all the reliability and
> >compatability you need.
> 
> Just a heads up...
> 
> It's important to distinguish between one-time hacks and code that
> gets widely distributed.  Users have a tendency to do things
> that designers never thought considered and testers didn't try.
> 
> The classic example in the networking field is somebody hardwiring
> a retransmit timer that's reasonable for LANs and then the code
> gets used over a WAN.
> 
> If you are going to ship some networking code, please get some
> network geeks to sanity check things and/or test it on broken nets
> to see if it contributes to meltdown.

Have you ever considered teh following method by Intellitech
(http://www.intellitech.com).

Intellitech offers a unique solution for configuring programmable
logic devices.  It is called SystemBIST embedded test and
configuration processor. The SystemBIST processor enables in-the-field
self-testable and reconfigurable products. It will replace the
existing method of configuring your FPGAs and give you an easy way to
upgrade the boards in the field.  The embedded self-test capabilities
of SystemBIST are gained for free, giving you and your customers the
ability to apply all boundary-scan tests throughout the product's life
cycle. You may find more information on our Web site here:
(http://www.intellitech.com).

Article: 53685
Subject: Re: Quartus2 : assigning I/O pins
From: "James Srinivasan" <James_Srinivasan@yahoo.com>
Date: Thu, 20 Mar 2003 00:04:38 -0000
Links: << >>  << T >>  << A >>
> Let Quartus assign all the pins automatically by itself first.
> Then open up the .csf file using Quartus and edit it to whatever
> you want the pin assignments to be. Save the .csf file and then
> close your project. Re-open the project again, and Quartus will
> pick up the new settings. That should work.

One point to note is that you should have the project closed when editing
the csf file otherwise Quartus will overwrite it,

James



Article: 53686
Subject: Generic SoundCard Driver/API for FPGA Device
From: "Verilog USER" <tkirkeNospamxxx@pacbell.net>
Date: Thu, 20 Mar 2003 00:34:24 GMT
Links: << >>  << T >>  << A >>
Is there a standard way of using a PCI card for a Audio Soundcard as far as
routing audio data to/from PCI bus?
I'd like to be able to use a current Windows Soundcard driver and modify a
FPGA board to work with it rather than the other way around (assuming that I
put the right Vendor/Device ID into the FPGA to "fool" Windows into thinking
that it is actually a particular soundcard). Is this possible or practical?




Article: 53687
Subject: Re: Using FPGAs as coprocessors in a PC
From: tom@arithlogic.com (Tom Hawkins)
Date: 19 Mar 2003 20:12:25 -0800
Links: << >>  << T >>  << A >>
Hi Roy,

There are few companies making PCI FPGA boards; both Catalina Research
and Annapolis Micro Systems are fairly popular.

  http://www.catalinaresearch.com/
  http://www.annapmicro.com/

In terms of speedup, it depends highly on the quality of architecture.
 I worked on a 2D FFT project that replaced ~100 PowerPCs with just 2
large Virtex-IIs.  Of course the logic, memory, and board was highly
optimized for the application.  (I also have a feeling the system we
replaced was fairly inefficient. :-) )

For math, fixed point is the only way to go.  We have built up some
floating point modules, but the logic floating point consumes doesn't
justify its use for ultra-fast DSP.

A lot of people new to DSP on FPGAs at first tend to believe they need
floating point precision.  In our development process we usually hand
off a C math model early on to let our clients experiment with various
levels of fixed-point precision.  Often this convinces them that fixed
point works just as well, and sometimes even better, than floating
point.  Also, don't forget Cordics for fixed-point sines and cosines. 
They may be a better alternative than consuming memory for lookup
tables.

However, the main difficulty with FPGA programming isn't how to
perform the arithmetic, but rather how to handle the throughput and
dataflow, i.e., getting the data on and off the chip and how to
buffer, reorder, and distribute the data internally.

-Tom

--
Tom Hawkins
tom@arithlogic.com

Arithlogic -- FPGA Consulting -- http://www.arithlogic.com/

Translating Data Intensive Algorithms to Digital Logic


roy hansen <royhansen@removethis_norway.online.no> wrote in message news:<em4ea.41692$Rc7.614451@news2.e.nsc.no>...
> Hi,
> 
> I am new to FPGAs.
> 
> Is it possible to buy a PCI card with one (or several) FPGAs,
> such that the card works as a coprocessor running a single 
> routine callable from other programs (i.e. matlab)?
> 
> If so, what is the typical speed increase I can hope for 
> compared to a state-of-the-art 1 CPU PC (i.e. P4 3GHz).
> I know this is heavily dependent on the routine (see below).
> 
> Which card should I look into?
> 
> How much work is it to program the FPGAs 
> (by an expert - not me). 
> 
> My routine contains simple arithmetics in single precision
> floating point (sines, cosines, square roots, multiplications 
> and additions) and is extremely easy to parallelize (it's sonar 
> beamforming). It could be made into fixed point if floating 
> point is a large problem. The sines and cosines could also 
> be replaced by table lookup. 
> 
> Sorry about all the stupid questions - I'm trying to figure
> out whether FPGAs are the solution to all my problems in life :-) 
> 
> -Roy

Article: 53688
Subject: Re: Cheapest Spartan II/IIE configuration flash EEPROM!
From: Peter Wallace <pcw@karpy.com>
Date: Wed, 19 Mar 2003 20:15:14 -0800
Links: << >>  << T >>  << A >>
On Wed, 19 Mar 2003 07:57:58 -0800, Tobias Stumber wrote:

> Wouldn't
> FLASH /RESET = FPGA /INIT
> FLASH /CE = FPGA DONE
> work without an inverter (and a /sysreset) or will the FLASH CE/ falling
> edge ignored while FLASH /RST is asserted ?
> 
> Regards, Tobias

	Possibly but I happened to have /reset and reset available...

	As someone else mentioned, it is possible to use the larger
(up to 8 and maybe 16 mbit) 25 series SST serial flash chips but you then
need a GAL or something to generate the initial 03 read command that 
those chips require. The GAL could also function as the ISP interface. If
you wanted the smallest helper chip, a sop8 PIC  (~$.80) will do...

PCW

Article: 53689
Subject: Re: Generic SoundCard Driver/API for FPGA Device
From: hmurray@suespammers.org (Hal Murray)
Date: Thu, 20 Mar 2003 05:02:08 -0000
Links: << >>  << T >>  << A >>
>Is there a standard way of using a PCI card for a Audio Soundcard as far as
>routing audio data to/from PCI bus?
>I'd like to be able to use a current Windows Soundcard driver and modify a
>FPGA board to work with it rather than the other way around (assuming that I
>put the right Vendor/Device ID into the FPGA to "fool" Windows into thinking
>that it is actually a particular soundcard). Is this possible or practical?

It should be possible.  I don't think there is a single official
sound card, but rather a few supported chips.  Find a chip you like
and emulate it.

You might have to setup a logic analyzer to find out what the driver
does in case the documentation isn't good enough (or you can't get it),
or the chip has lots of options the driver doesn't use and you don't
want to bother implementing.

You could also look at the open source drivers: Linux, *BSD, ...

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 53690
Subject: Re: Help understanding 7408 and gate chip
From: nidar@rediffmail.com (Niranjandas)
Date: 19 Mar 2003 21:19:22 -0800
Links: << >>  << T >>  << A >>
hi rosen,
 i am looking for tetsting that age old product thru a letest low cost
ATE. so for tetsting opens test i req to know if they have ESD thats
it.
any way can u suggest better Group who discusses elated areas
Questions?


Niranjandas



"B. Joshua Rosen" <bjrosen@polybus.com> wrote in message news:<pan.2003.03.17.21.03.37.306278.2313@polybus.com>...
> On Mon, 17 Mar 2003 14:18:11 -0500, John Eaton wrote:
> 
>   
> I don't think that the OP was talking about an old system, why would he
> have been interested in ESD protection if all he was doing was repairing
> an antique system.

Article: 53691
Subject: Re: write a single byte in to DRAM
From: "Stan Lackey" <stanlackey@hotmail.com>
Date: Thu, 20 Mar 2003 01:16:06 -0500
Links: << >>  << T >>  << A >>
> > single write to the memory. But is it possible to write it byte by byte,
> > instead all at once.  Assuming 32 bit memory bus width.
>
> On many systems the cache will handle this.
>
> Some have byte addressable (byte enable) memory, so it would take two
> cycles.
>
> Some have only word addressable memory, so the word is fetched, modified,
> and rewritten.  It could do this twice, or realize that both were the same
> word and read or write once.

You're using the term "byte adressable" wrong.  -Stan




Article: 53692
Subject: Re: fpga implementation problems
From: anjanr@yahoo.com (Anjan)
Date: 19 Mar 2003 23:20:56 -0800
Links: << >>  << T >>  << A >>
Hi
Did you check the PR simulation. Any design works if the simulation
runs sucessfully. Are you crossing clock domains.
Anjan

Article: 53693
Subject: Using DDR placed on the PCB with a Virted II...
From: "Austin Franklin" <austin@dark88room.com>
Date: Thu, 20 Mar 2003 02:51:21 -0500
Links: << >>  << T >>  << A >>
Hi,

I am migrating an embedded application from regular SDRAM to DDR memory, and
I don't want to use DDR DIMMs.  I'll be using a V2 FPGA.  What my question
is, is does anyone know of any resources for board level termination
information/SI (Signal Integrity) issues for using on-board DDR?

We're going to be running at 166 (333).

The Xilinx app notes don't talk one bit about external issues, like
termination and clock feedback...  We are using only one bank (3 x16 chips,
48 bits wide), so we can keep the traces pretty short.

My thoughts were to use the SSTL_2_I I/O for address and control, using the
DCI for source termination which would provide a 25 ohm series resistor.
Use SSTL_2_II for the D/DQS signals for source and receiver termination, as
they are bidirectional, which would provide 25 ohm source termination for
writes, as well as a pseudo second "VTT" termination for the reads.

Externally, I was going to use 22 ohm source termination resistors on the
D/DQS pins at the DDR, and use 50 ohm VTT termination.

I'm not sure if the DCI/V2 can handle the clock termination using I/O
options though...so I was going to use external 33 ohm source termination
resistors, with 120 ohm impedance matching resistors just after the source
resistors, and then another 120 just before the DDR, between DQ/DQ#.  And
for feedback, just use a second differential pair, same topology, same
resistors, and match the clock length, and the loading, by using two
additional 1.5pf caps (as there are three DDRs, so the clock goes to three
places after the end 120 ohm resistor) to equal the same loading.

I'm curious if anyone has done an on-board DDR implementation (not using
DIMMs), and what they found works for them when interfaced to a V2.

Thanks!

Austin



Article: 53694
Subject: Re: Using FPGAs as coprocessors in a PC
From: newb <n/a@n/a.com>
Date: Thu, 20 Mar 2003 00:31:30 -0800
Links: << >>  << T >>  << A >>
Hello,

Tom I just read your post and was interested in the last 
part of it regarding getting the data off the chip. Is it 
possible to direct me to some resources/docs/urls or even 
explaination as to how to learn about this process. I am 
particularly interested in learning how to interface the 
fpga with an application to send queries of data and 
receive the calculated results. Im doing it for fun 
so any info would be great! Thanks .



Article: 53695
Subject: Re: unsupported switches of PAR
From: Petter Gustad <newsmailcomp4@gustad.com>
Date: 20 Mar 2003 09:32:20 +0100
Links: << >>  << T >>  << A >>
Steve Lass <lass@xilinx.com> writes:

> Petter Gustad wrote:
> 
> >I hope that the -m option will be supported in the rumored native
> > Linux version
> The good news is that native Linux is not a rumor.  It will be
> delivered in our 6.1 release in September.

This is good news.

> However, the -m option will not be supported  in the first release.
> It's on our roadmap, but did not
> make the cut because there is a workaround (write a script that sends
> each job separately to each
> machine using a different cost table).

True. It should be fairly easy to make a script to do this. 

Petter
-- 
________________________________________________________________________
Petter Gustad         8'h2B | ~8'h2B        http://www.gustad.com/petter

Article: 53696
Subject: Re: spartan-2 clocking problem
From: "Maxx" <bla@bla.com>
Date: Thu, 20 Mar 2003 09:39:34 +0100
Links: << >>  << T >>  << A >>
> > I've written some VHDL code that synchronises 2 clocks, one being the
> normal
> > "clk", that drives all logic, coming from GCK0, and one "spiclk", used
in
> > only one process, coming from GCK1.
> >
> > Synthesis is fine, but when mapping, I get a warning, and then an error
> > (using xilinx ISE5.2.01i):
> >
> > WARNING:NgdBuild:477 - clock net 'clk_bufgp' has non-clock connections.
> > These
> >    problematic connections include: pin i0 on block spi_slave_clkout1
with
> > type
> >    LUT1
>
> This sounds like you dont use spiclk as a pure clock. I guess you do some
> kind of clock gating or so.
> This is not good in two ways.
> 1st (very important) you will run into ugly porblems with clock gating.
> 2nd the synthesizer realize that spiclk is NOT directly used as a clock
> signal, so it inserts just a normal input buffer (ibuf). But since you
> constraint this input to a GCK input, you MUST use a ibufg. You can do
this
> by manually instanciating the ibufg, BUT I strongly recommend that you
think
> about you synchronization in general. Gated clocks are no good in FPGAs.
> (Yes, there area always exceptintion to every rule ;-)

Well I guess it shows I'm a newby... yes I assigned that clock signal to a
GCK, but how do I assign it to an IBUFG? Up till now, ISE did it for me
automagically (with the normal clock it did atleast). The xilinx website
says I need to instantiate one.. sure. but how? :)
also, what would be the definition of a "pure" clock? -> one where I check
for 'event ?

thanks again



Article: 53697
Subject: Re: Help understanding 7408 and gate chip
From: "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu>
Date: Thu, 20 Mar 2003 08:48:49 GMT
Links: << >>  << T >>  << A >>

"Niranjandas" <nidar@rediffmail.com> wrote in message
news:4f155288.0303192119.1770abb6@posting.google.com...
> hi rosen,
>  i am looking for tetsting that age old product thru a letest low cost
> ATE. so for tetsting opens test i req to know if they have ESD thats
> it.
> any way can u suggest better Group who discusses elated areas
> Questions?

alt.folklore.computers



Article: 53698
Subject: PCI target design
From: praveenkumar1979@rediffmail.com (praveen)
Date: 20 Mar 2003 00:55:15 -0800
Links: << >>  << T >>  << A >>
Hello Sir,
I am designing a PCI target in an FPGA. The module i am going to
implement include
1.Configuration Multiplexer Block.
This block implements the PCI Target configuration registers, and the
PCI data output
MUX.
2.Retry Counter Block:
If the PCI Target acknowledges a Read or Write cycle it must provide
or accept data
within 16 clock cycles of asserting DEV_SEL.
3.Miscellaneous Glue Logic Block:
This module contains the miscellaneous glue logic required for the
design. It contains the
PCI address registers, CBE registers, and the IDSEL register.
4.Base Address Check Block
5.State Machine
It controls the bus
cycle timing of all data flow paths to and from the PCI Bus and Back
End Bus.
6.Parity Generation Block
Parity is generated on Configuration read, and Memory-I/O reads
cycles.

Is this much module enough. Where to include FIFO for burst
write.Which FPGA to go whether Altera or Xilinx

Waiting for your reply
praveen

Article: 53699
Subject: Re: write a single byte in to DRAM
From: "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu>
Date: Thu, 20 Mar 2003 08:57:14 GMT
Links: << >>  << T >>  << A >>

"Stan Lackey" <stanlackey@hotmail.com> wrote in message
news:v7in55gkhqelcc@corp.supernews.com...
> > > single write to the memory. But is it possible to write it byte by
byte,
> > > instead all at once.  Assuming 32 bit memory bus width.
> >
> > On many systems the cache will handle this.
> >
> > Some have byte addressable (byte enable) memory, so it would take two
> > cycles.
> >
> > Some have only word addressable memory, so the word is fetched,
modified,
> > and rewritten.  It could do this twice, or realize that both were the
same
> > word and read or write once.
>
> You're using the term "byte adressable" wrong.  -Stan

Maybe, but you didn't say what was wrong with it.

Pentium series machines usually use 64 bit wide memory.   A write to memory
(not counting caching)  is done by enabling only the bytes needed.

The Alpha, which still uses byte addressing, only allows (in most versions)
32 bit or 64 bit memory cycles.   The only way to change a byte was to load
a word, change the byte in a register, then store the word.  This was true
even though the addressable unit was the 8 bit byte.

-- glen





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