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Messages from 52700

Article: 52700
Subject: Re: PCB Design for a Xilinx Spartan-II FPGA
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 19 Feb 2003 11:09:55 -0800
Links: << >>  << T >>  << A >>
I agree with Hal's comments. 
And let me ask: Is a 2-layer board really any cheaper than a 4-layer
board? I know it was in the past century, but is there really a
significant price difference nowadays ?
Is your volume high enough to justify the risk?
Peter Alfke
====================================
Hal Murray wrote:
> 
> >    Thank you for your answer. I am using a TQFP-144 package and the clock
> >frequency will be 8 Mhz. Do you think that a 2-layer PCB will work, or 4
> >layers are necessary for correct circuit operation?
> 
> The clock frequency isn't the critical parameter.  It's the edge rate.
> 
> Of course, the edge rate must be fast for a high speed clock, but it
> can also be fast when the clock is running slowly, and often is with
> modern chips.
> 
> I'd expect it would be interesting/challenging to get a solid design
> on two layers.  I'm sure it's been done.  Do you have any big busses?
> (Lots of outputs changing at the same time.)  Are all your outputs
> using low drive?  How many long wires?
> 
> I'd probably do a trial layout and start by filling the bottom layer
> under the chip with a ground pad.  Can you get the bypass caps near
> the power pins?  What else is on the board?  Can you use most of the
> bottom layer as a ground plane?
> 
> The other consideration is how important is it that it work the first time?
> Do you have a software team waiting?  How much time are you willing to
> spend chashing obscure bugs?  Are the extra layers cheap insurance?
> 
> --
> The suespammers.org mail server is located in California.  So are all my
> other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
> commercial e-mail to my suespammers.org address or any of my other addresses.
> These are my opinions, not necessarily my employer's.  I hate spam.

Article: 52701
Subject: Re: PCB Design for a Xilinx Spartan-II FPGA
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Wed, 19 Feb 2003 19:46:29 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <3E53D682.FDC2F186@xilinx.com>,
Peter Alfke  <peter@xilinx.com> wrote:
>I agree with Hal's comments. 
>And let me ask: Is a 2-layer board really any cheaper than a 4-layer
>board? I know it was in the past century, but is there really a
>significant price difference nowadays ?

Yes.  By a fair amount.

A 2 layer board is really, REALLY cheap, with prototype to production
techniques for 1-3 day turnaround and quick rampup to large volumes.

The price difference between 2 and 4 layer is over 50% for something
like PCBpro (2x3" board, 100 pieces, 1 week turnaround).  Its $448 for
a 2 layer board and $783 for a 4 layer board.

However, given the cost of designer time and all, unless you really
NEED the 1 day board-fabrication turnaround time you can get with a 2
layer board, or that the part cost on the board really REALLY matters,
4 layers seem like cheap insurance.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 52702
Subject: Re: PCB Design for a Xilinx Spartan-II FPGA
From: hmurray@suespammers.org (Hal Murray)
Date: Wed, 19 Feb 2003 20:00:23 -0000
Links: << >>  << T >>  << A >>
>A 2 layer board is really, REALLY cheap, with prototype to production
>techniques for 1-3 day turnaround and quick rampup to large volumes.

1 layer is even cheaper. :)


> And let me ask: Is a 2-layer board really any cheaper than a 4-layer
> board? I know it was in the past century, but is there really a
> significant price difference nowadays ?

Showing how to make things to work (well) on 2 layers might be an
interesting opportunity for an FAE group.  Opens up another corner
of the low price market.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 52703
Subject: Re: WebPack 4.2i and Block RAM instantiation
From: "Jim Wu" <jimwu88NOOOSPAM@yahoo.com>
Date: Wed, 19 Feb 2003 20:24:15 GMT
Links: << >>  << T >>  << A >>
> When my Block RAM exceeds 128 bits, the XST synthesizer seems to not

Did you mean 128K bits block RAM?



Article: 52704
Subject: Re: Quick FPGA PCI I/O in Spartan-IIE for single peripheral
From: Lasse Langwadt Christensen <langwadt@ieee.org>
Date: Wed, 19 Feb 2003 21:53:20 +0100
Links: << >>  << T >>  << A >>
Steve T Shannon wrote:
> Hello!
>    I'm trying to interface my project to a gigabit ethernet
> transceiver (DP83820) but alas, the interface is only PCI. Has anyone
> ever tried doing this sort of quick-hack PCI interface, just to talk
> to a single PCI peripheral? What timing constraints become less of an
> issue in this situation? Might anyone know of any example code for
> this sort of thing? Any general suggestions?
> 
> Thanks,
> 
> Steve

One of of the guys I work with did a quick PCI hack for a test system 
bit banging all the signals with a standard micro, everything is 
synchronous to the PCI clk so it's was pretty simple.

but of course, the resulting pci clk was very slow so setup and hold
wasn't an issue, if you want/need to run at normal PCI speed you'll
probably have to think about it.

-Lasse


Article: 52705
Subject: Re: crc implementation
From: "Jim Wu" <jimwu88NOOOSPAM@yahoo.com>
Date: Wed, 19 Feb 2003 21:05:36 GMT
Links: << >>  << T >>  << A >>
"A PAINLESS GUIDE TO CRC ERROR DETECTION ALGORITHMS" by Ross Williams is a
very good paper on CRC. Check it out.

http://www.geocities.com/SiliconValley/Pines/8659/crc.htm

HTH,
Jim

"Dominique" <dominique_luong@mentor.com> wrote in message
news:ee7bf3c.-1@WebX.sUN8CHnE...
Hi
I have downloaded the file xapp209.zip from your web site about an hardware
crc implementation.
Could someone can explain me how the xor equations are generated ?
I compare the crc results with some soft crc, and i don't have the same crc.
Your help will be very appreciated.
Cheers
Dominique



Article: 52706
Subject: Messaging Unit + Dorbells etc ..
From: asel_montreal@yahoo.com (Was)
Date: 19 Feb 2003 13:27:35 -0800
Links: << >>  << T >>  << A >>
Hi Guys,
I'm working on an FPGA design which is going to do an interface to the
Intel XScale IOP321 processor. I was reading the datasheet for this
iop321, and there's something that I can't undestand.

It talks about a Messaging Unit.. I read it couple of times, but I
think I need to get familiar with the basic stuff about this before I
continue. "Doorbell", "circular queues", etc are all confusing me A
LOT. This is the first time that I'm dealing with this type of a
thing.

Could anybody explain me what is a Messaging Unit and why/how is it
used? Also please let me know, if any of you know any good
"educational" links (NOT data sheets)..

Thanks,
Was

Article: 52707
Subject: Re: Messaging Unit + Dorbells etc ..
From: Richard Iachetta <iachetta@us.ibm.com>
Date: Wed, 19 Feb 2003 15:53:01 -0600
Links: << >>  << T >>  << A >>
In article <b01453f.0302191327.378a6ba4@posting.google.com>, 
asel_montreal@yahoo.com says...
> Hi Guys,
> I'm working on an FPGA design which is going to do an interface to the
> Intel XScale IOP321 processor. I was reading the datasheet for this
> iop321, and there's something that I can't undestand.
> 
> It talks about a Messaging Unit.. I read it couple of times, but I
> think I need to get familiar with the basic stuff about this before I
> continue. "Doorbell", "circular queues", etc are all confusing me A
> LOT. This is the first time that I'm dealing with this type of a
> thing.
> 
> Could anybody explain me what is a Messaging Unit and why/how is it
> used? Also please let me know, if any of you know any good
> "educational" links (NOT data sheets)..
> 
> Thanks,
> Was
> 


That part is probably an I2O device.  Get the I2O spec. and it will explain 
all about the messaging queues (post and free), doorbells, etc.

-- 
Rich Iachetta
iachetta@us.ibm.com
I do not speak for IBM.

Article: 52708
Subject: Re: PCB Design for a Xilinx Spartan-II FPGA
From: Andras Tantos <andras_tantos@yahoo.com>
Date: Wed, 19 Feb 2003 14:50:25 -0800
Links: << >>  << T >>  << A >>
>>A 2 layer board is really, REALLY cheap, with prototype to production
>>techniques for 1-3 day turnaround and quick rampup to large volumes.
>
>1 layer is even cheaper. :)
>
>
>> And let me ask: Is a 2-layer board really any cheaper than a 4-layer
>> board? I know it was in the past century, but is there really a
>> significant price difference nowadays ?
>
>Showing how to make things to work (well) on 2 layers might be an
>interesting opportunity for an FAE group.  Opens up another corner
>of the low price market.

Hi!

I've done that on my FPGA board. So far I had no problems though I
haven't tested it at really high speeds. I've created a small webpage
where I've put images of the layout:
http://tantos.homelinux.org/~tantos/ 
Please anyone interested, take a look and comment. Both positive and
negative feedback are extreamly welcome.

Thanks,
Andras Tantos

Article: 52709
Subject: Re: Quick FPGA PCI I/O in Spartan-IIE for single peripheral
From: kevinbraceusenet@hotmail.com (Kevin Brace)
Date: 19 Feb 2003 15:26:19 -0800
Links: << >>  << T >>  << A >>
Steve,

You will need to provide more details, but from what you wrote, it
sounds to me what you are trying to do is to convert some kind of bus
protocol to PCI's protocol.
If someone has already developed such a bridge chip (an ASSP), you
should use that instead of developing one from scratch.
If no such bridge chip exists, you will likely have to develop one
from scratch, and that's not going to be easy.
Although some might argue that PCI isn't that hard, I will say from my
own experience of developing my own PCI IP core that developing one
can take somewhere from three months to a year depending on how
thoroughly you want to verify the behavior of the PCI interface, how
much do you want to develop in-house (i.e., Whether or not you will
develop the PCI testbench code in-house, or buy it from someone
else.), and how many people will be working on this project (It's nice
to let someone else do the testbench because the circuit designer
won't want to work on the testbench.).
        Since your PCI bridge is going to have a point-to-point
connection to the PCI gigabit ethernet chip, you might be able to
relax the standard setup time of 7ns for 33MHz PCI and 3ns for 66MHz
PCI to 10ns and 5ns, respectively, although no such timing parameters
are officially defined by the PCI specification.
Since you will be using Spartan-IIE, meeting 33MHz PCI's setup time
should not really be difficult, although when I first tried it, I did
have some hard time meeting the 7ns setup time.
You will need to have a good understanding of how the synthesis tool
generates logic and the device architecture to meet the required
timings.
        Considering the complexity of PCI, and the trouble of writing
the testbench code, anyone smart enough to develop a PCI interface has
turned into a business (I am thinking of doing that, too.).
Other than Opencores.org PCI IP core
(http://www.opencores.org/projects/pci/), there aren't too many free
or open source designs related to PCI.
Still, Xilinx, Lattice, and Quicklogic have some PCI related reference
designs, but I don't find them useful.
Opencores.org PCI IP core will let you see their RTL code, but
understanding what goes on inside and modifying it isn't going to be
easy.
If you have to develop a PCI bridge from scratch, obtain a copy of the
PCI specification, and take a look at Appendix B of it.
Appendix B has an example target and initiator state machine, and that
should be your starting point.
You should never try to copy the entire Appendix B because if you do
so, you will see signal glitches coming out of the chip, and several
protocol rules aren't being followed in the Appendix B example.
Other than the PCI specification's Appendix B, this posting about PCI
I posted a few months ago should be somewhat helpful.

http://groups.google.com/groups?selm=cc7b0b5f.0210172126.2db7758%40posting.google.com


        Steve, does your project have to deal with 5V PCI?
If that's the case, you will have to use the older Spartan-II instead
because Spartan-IIE doesn't support 5V PCI, although 3.3V PCI is still
supported.


Kevin Brace (If someone wants to respond to what I wrote, I prefer if
you will do so within the newsgroup.)



stevetshannon@yahoo.com (Steve T Shannon) wrote in message news:<c5e9863d.0302190255.70d8e2ec@posting.google.com>...
> Hello!
>    I'm trying to interface my project to a gigabit ethernet
> transceiver (DP83820) but alas, the interface is only PCI. Has anyone
> ever tried doing this sort of quick-hack PCI interface, just to talk
> to a single PCI peripheral? What timing constraints become less of an
> issue in this situation? Might anyone know of any example code for
> this sort of thing? Any general suggestions?
> 
> Thanks,
> 
> Steve

Article: 52710
Subject: Re: Generating a sin wave with vhdl
From: Bassman59a@yahoo.com (Andy Peters)
Date: 19 Feb 2003 16:41:20 -0800
Links: << >>  << T >>  << A >>
akshaymishra@rediffmail.com (Akshay) wrote in message news:<937606cb.0302170535.2347978a@posting.google.com>...
> Hello,
>       We are trying to generate a sine wave using the dsp iir filter
> method but not able to get a sine wave. The vhdl code simulates a
> correct sine wave output but the synthesized code does not give any
> output on the fpga (xilinx virtex 2, xv2000).

1) Does the synthesis tool give you any errors or warnings?

2) The multiplier may be eating up a lot of area, and you may not be
meeting timing. What's your clock speed? Have you set any timing
constraints?  Are you meeting the constraints?

-ap

Article: 52711
Subject: New Pacman in an FPGA released
From: "MikeJ" <support@fpgaarcade.com>
Date: Thu, 20 Feb 2003 00:41:23 -0000
Links: << >>  << T >>  << A >>
Finally got around to releasing the new Pacman code on www.fpgaarcade.com.

This is a VHDL model of the original arcade game, and the new version
contains software to convert Rom binaries into VHDL.
This release also contains an embedded audio multiplier for volume control,
an optional scan doubler to allow standard VGA monitors to be used, and some
more documentation.

(Note, the distribution does not contain the original rom images, but
binaries for a Pong demo game.)

Cheers,

MikeJ



Article: 52712
Subject: hold violation error
From: rathanon99@yahoo.com (ron)
Date: 19 Feb 2003 17:07:12 -0800
Links: << >>  << T >>  << A >>
I got this message from the static timing analyzer of xilinx ISE.
Apparently, I have 3 hold violations. One of them has the following
information. How do you solve this? Thank you and hope to hear from
you soon.

 Hold Violations: Default period analysis

--------------------------------------------------------------------------------
Hold Violation:         -8.816ns (data path - positive clock skew)
  Source:               inst_id_ex_inst_block_im8_out_2
  Destination:          u_shift_mux_reg_out_sig_2
  Data Path Delay:      8.315ns (Levels of Logic = 4)
  Positive Clock Skew:  17.131ns
  Source Clock:         inst_clk_out_inst_block_I_cp15clk_11 falling
  Destination Clock:    inst_clk_out_inst_block_I_cp15clk_13 falling
  Timing Improvement Wizard
  Data Path: inst_id_ex_inst_block_im8_out_2 to
u_shift_mux_reg_out_sig_2
    Delay type         Delay(ns)  Logical Resource(s)
    ----------------------------  -------------------
    Tcko                  0.772   inst_id_ex_inst_block_im8_out_2
    net (fanout=1)        0.357   inst_id_ex_inst_block_im8_out_2
    Tilo                  0.398   u_bmux_Mmux_b_out_sig_inst_lut3_225
    net (fanout=3)        0.658  
u_bmux_Mmux_b_out_sig_xstmacro_int_tempname303
    Tif5                  0.752  
u_bmux_Mmux_b_out_sig_xstmacro_int_tempname303_rt
                                 
u_bmux_Mmux_b_out_sig_inst_mux_f5_100
    net (fanout=20)       4.781  
u_bmux_Mmux_b_out_sig_xstmacro_int_tempname304
    Tcki         (-Th)   -0.597   u_shift_mux_I_shift_sig_2_1
                                  u_shift_mux_reg_out_sig_2
    ----------------------------  ------------------------------
    Total                 8.315ns (2.519ns logic, 5.796ns route)

Article: 52713
Subject: FPGA's at High Temperatures
From: m_kochar@yahoo.com (makmorbi)
Date: 19 Feb 2003 18:41:47 -0800
Links: << >>  << T >>  << A >>
Hi All,

I am about to write a paper on effects on FPGA's at high temperatures.
One application maybe an oil well where the temperatures are very
high. Can somebody point me to some references or have any thoughts on
that. Would apprectiate it.

Thanks

Article: 52714
Subject: Re: About automatically programming my FPGA
From: hmurray@suespammers.org (Hal Murray)
Date: Thu, 20 Feb 2003 03:12:16 -0000
Links: << >>  << T >>  << A >>
>Also, TCP may be hairy and complicated, but the MINIMUM isn't that
>nasty.  If you keep window size at 0, ack packets one at a time, you
>get cruddy throughput, but you get all the reliability and
>compatability you need.

Just a heads up...

It's important to distinguish between one-time hacks and code that
gets widely distributed.  Users have a tendency to do things
that designers never thought considered and testers didn't try.

The classic example in the networking field is somebody hardwiring
a retransmit timer that's reasonable for LANs and then the code
gets used over a WAN.

If you are going to ship some networking code, please get some
network geeks to sanity check things and/or test it on broken nets
to see if it contributes to meltdown.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 52715
Subject: Re: PCMCIA + FPGA/CPLD
From: hmurray@suespammers.org (Hal Murray)
Date: Thu, 20 Feb 2003 03:15:30 -0000
Links: << >>  << T >>  << A >>
>Do you know of any interface chips for Cardbus? The usual
>suspects (National/Zilog/etc) have all discontinued what
>they had.All I can find are ASICS for Ethernet and the like.
>
>Is this a global conspiracy against Cardbus developers? ;^)

My guess would be economics rather than conspiracy.  When were
those chips designed?  When did that fab line get turned off?
Is the market (now) big enough to redesign the chip for modern
fab lines?

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 52716
Subject: Re: crc implementation
From: chopra_vikram@excite.com (Vikram)
Date: 19 Feb 2003 19:33:57 -0800
Links: << >>  << T >>  << A >>
"Jim Wu" <jimwu88NOOOSPAM@yahoo.com> wrote in message news:<AkS4a.13829$_k4.2673@nwrddc03.gnilink.net>...
> "A PAINLESS GUIDE TO CRC ERROR DETECTION ALGORITHMS" by Ross Williams is a
> very good paper on CRC. Check it out.
> 
> http://www.geocities.com/SiliconValley/Pines/8659/crc.htm
> 
> HTH,
> Jim
> 
> "Dominique" <dominique_luong@mentor.com> wrote in message
> news:ee7bf3c.-1@WebX.sUN8CHnE...
> Hi
> I have downloaded the file xapp209.zip from your web site about an hardware
> crc implementation.
> Could someone can explain me how the xor equations are generated ?
> I compare the crc results with some soft crc, and i don't have the same crc.
> Your help will be very appreciated.
> Cheers
> Dominique

There are online tools available for generating synthesisable CRC
functions in VHDL / Verilog -

http://www.easics.be/webtools/crctool
http://www.nobugconsulting.ro/crc.php

-Vikram.

Article: 52717
Subject: Re: Quick FPGA PCI I/O in Spartan-IIE for single peripheral
From: hmurray@suespammers.org (Hal Murray)
Date: Thu, 20 Feb 2003 03:43:29 -0000
Links: << >>  << T >>  << A >>
>   I'm trying to interface my project to a gigabit ethernet
>transceiver (DP83820) but alas, the interface is only PCI. Has anyone
>ever tried doing this sort of quick-hack PCI interface, just to talk
>to a single PCI peripheral? What timing constraints become less of an
>issue in this situation? Might anyone know of any example code for
>this sort of thing? Any general suggestions?

That chip is a packet processor, not a transceiver.

What are you really looking for?  Do you just want to use
ethernet to get some data from your chip to someplace else?
(Just a fast RS-232.)

If so, I suggest looking for MAC chips.  GMII is a good keyword
to search on: Gigabit Media Independent Interface, or something
like that.  It's 8 bits with clock and a few control bits.
Repeat that for the other direction.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 52718
Subject: Bus Attributes in Xilinx 2.1i Schematic Editor
From: Kload <aperson@somewhere.com>
Date: Thu, 20 Feb 2003 14:21:34 +1000
Links: << >>  << T >>  << A >>
Hello all,

Just wondering how I can put attributes onto a bus (e.g. MAXDELAY).  Its 
easy enough to do for a simple wire (double click, then click on 
attributes), but I can't see how to add an attribute to a bus.

Thanks in advance


Article: 52719
Subject: Re: PCB Design for a Xilinx Spartan-II FPGA
From: hmurray@suespammers.org (Hal Murray)
Date: Thu, 20 Feb 2003 04:44:04 -0000
Links: << >>  << T >>  << A >>
[2 layer discussion]

>I've done that on my FPGA board. So far I had no problems though I
>haven't tested it at really high speeds. I've created a small webpage
>where I've put images of the layout:
>http://tantos.homelinux.org/~tantos/ 
>Please anyone interested, take a look and comment. Both positive and
>negative feedback are extreamly welcome.

Thanks.

What is your FPGA doing?  How many outputs switching at the same time?
(Looks like a bus going off to the right on the blue layer.)  Are they
all low/slow drive?

As far as I can see, there is only 1 bypass cap on each power rail,
and one of them goes around the bottom of the chip so the end of
it is a long way from the cap.

I'd be nervous about using a structure like that, but that's just
my quick eyeball analysis.  Might be interesting to feed it to
some signal integrity tools.  (I tend to be conservative in this
area, left over from getting burned many years ago.)

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 52720
Subject: Re: hold violation error
From: "Bob" <nimby1_not_spmmm@earthlink.net>
Date: Thu, 20 Feb 2003 04:56:17 GMT
Links: << >>  << T >>  << A >>
You must not be using the global clock nets to route your clock.

Use the global clock nets (i.e., output of the BUFG).

Bob

"ron" <rathanon99@yahoo.com> wrote in message
news:c661162.0302191707.260209f1@posting.google.com...
> I got this message from the static timing analyzer of xilinx ISE.
> Apparently, I have 3 hold violations. One of them has the following
> information. How do you solve this? Thank you and hope to hear from
> you soon.
>
>  Hold Violations: Default period analysis
>
> --------------------------------------------------------------------------
------
> Hold Violation:         -8.816ns (data path - positive clock skew)
>   Source:               inst_id_ex_inst_block_im8_out_2
>   Destination:          u_shift_mux_reg_out_sig_2
>   Data Path Delay:      8.315ns (Levels of Logic = 4)
>   Positive Clock Skew:  17.131ns
>   Source Clock:         inst_clk_out_inst_block_I_cp15clk_11 falling
>   Destination Clock:    inst_clk_out_inst_block_I_cp15clk_13 falling
>   Timing Improvement Wizard
>   Data Path: inst_id_ex_inst_block_im8_out_2 to
> u_shift_mux_reg_out_sig_2
>     Delay type         Delay(ns)  Logical Resource(s)
>     ----------------------------  -------------------
>     Tcko                  0.772   inst_id_ex_inst_block_im8_out_2
>     net (fanout=1)        0.357   inst_id_ex_inst_block_im8_out_2
>     Tilo                  0.398   u_bmux_Mmux_b_out_sig_inst_lut3_225
>     net (fanout=3)        0.658
> u_bmux_Mmux_b_out_sig_xstmacro_int_tempname303
>     Tif5                  0.752
> u_bmux_Mmux_b_out_sig_xstmacro_int_tempname303_rt
>
> u_bmux_Mmux_b_out_sig_inst_mux_f5_100
>     net (fanout=20)       4.781
> u_bmux_Mmux_b_out_sig_xstmacro_int_tempname304
>     Tcki         (-Th)   -0.597   u_shift_mux_I_shift_sig_2_1
>                                   u_shift_mux_reg_out_sig_2
>     ----------------------------  ------------------------------
>     Total                 8.315ns (2.519ns logic, 5.796ns route)
>



Article: 52721
Subject: Re: PCB Design for a Xilinx Spartan-II FPGA
From: Andras Tantos <andras_tantos@yahoo.com>
Date: Thu, 20 Feb 2003 05:21:21 GMT
Links: << >>  << T >>  << A >>
Hi!

> What is your FPGA doing?  How many outputs switching at the same time?
> (Looks like a bus going off to the right on the blue layer.)  Are they
> all low/slow drive?
> 
> As far as I can see, there is only 1 bypass cap on each power rail,
> and one of them goes around the bottom of the chip so the end of
> it is a long way from the cap.

Thanks for the comments. Yes, I do have a bus comming out from this chip 
however it's a relatively slow asycnronous 16-bit one. Average number of 
switching signals in each cycle should be around 15.

I have one bypass caps on each power rail but I also have one for each chip 
power pin also.

You probably right about the core VCC: it's long. However I wanted to avoid 
another via let alone a loop in the layout.

> I'd be nervous about using a structure like that, but that's just
> my quick eyeball analysis.  Might be interesting to feed it to
> some signal integrity tools.  (I tend to be conservative in this
> area, left over from getting burned many years ago.)

Yeah, I've tried to do that but my CAD pacakge kept crashing on each and 
every trial. :-(

Andras Tantos


Article: 52722
Subject: Re: PCB Design for a Xilinx Spartan-II FPGA
From: hmurray@suespammers.org (Hal Murray)
Date: Thu, 20 Feb 2003 06:39:16 -0000
Links: << >>  << T >>  << A >>
>You probably right about the core VCC: it's long. However I wanted to avoid 
>another via let alone a loop in the layout.

Ahh.  I see them now that I look in the right place.

That's probably (close to?) as good as you can get with only 2 layers.

Another layout possibility is to put a ring on the bottom layer
directly under the pads.  With only 2 layers, that will block
routes from vias in the inside of the pad ring.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 52723
Subject: Re: WebPack 4.2i and Block RAM instantiation
From: "Dr. Jones" <#?!@tin.it>
Date: Thu, 20 Feb 2003 06:57:32 GMT
Links: << >>  << T >>  << A >>
Jim Wu <jimwu88NOOOSPAM@yahoo.com> wrote in message
PJR4a.13695$_k4.3071@nwrddc03.gnilink.net...
> > When my Block RAM exceeds 128 bits, the XST synthesizer seems to not
>
> Did you mean 128K bits block RAM?
>

No, no, 128 bits!!!
[the device I use has a total of 64Kbits of block RAM]




Article: 52724
Subject: Re: Should I choose Xilink or Altera for a small project
From: Petter Gustad <newsmailcomp4@gustad.com>
Date: 20 Feb 2003 08:43:03 +0100
Links: << >>  << T >>  << A >>
Peter Alfke <peter@xilinx.com> writes:

> when I read "highest temperature" and "Norway", I assume this is for a

High temperature and Norway - to me it sounds like a contradiction :-)

Petter
-- 
________________________________________________________________________
Petter Gustad         8'h2B | ~8'h2B        http://www.gustad.com/petter



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