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Messages from 142925

Article: 142925
Subject: bidirectional bus
From: nobody <cydrollinger@gmail.com>
Date: Tue, 8 Sep 2009 11:07:26 -0700 (PDT)
Links: << >>  << T >>  << A >>
An eight bit bus on the PCB is used for both programming an FPGA,
XC3S250EVQ100, as a slave parallel configuration from a CPLD,
XC2C64AVQ100, and secondarily carry information back to the CPLD after
programming. This programming configuration releases the done pin,
however unable to drive an external set of LEDs from the bus,
mentioned above. Code is published in a message" Bidirectional Bus"
9/7/09. I am wondering about driving the pins, CPLD, into a high "Z"
state and therefore unable to read from them as well. I would
appreciate some insight into driving this bus as a programmer and then
as a data out from the FPGA.

Thankyou

Cy Drollinger

Article: 142926
Subject: Re: Traversing hierarchy in UCF works for OBUF, but not IOBUF, please
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Tue, 8 Sep 2009 11:53:35 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 8, 9:13=A0am, Telenochek <elet.mir...@gmail.com> wrote:
> Hi all,
>
> I have an SDRAM interface buried deep inside the hierarchy.
> I was able to instantiate OBUF for the control & address signals and
> traverse the hierarchy from the UCF file to tie the signals to the
> FPGA pins.
>
> However, when I try to do something similar for the =A0IOBUFs, I get an
> error of the type
>
> INFO:NgdBuild:889 - Pad net 'eight_chan_gen/u1/external_sdram/U1/
> DQ<0>' is not connected to an external port in this design. =A0A new
> port 'DQ<0>' has been added and is connected to this signal.
>
> Example of a successful OBUF:
>
> --VHDL file (inside the submodule)
>
> obuf_sdram_a0: =A0 =A0OBUF port map (O =3D> sdram_a0, I =3D> A(0));
>
> --.UCF file
>
> NET "eight_chan_gen/u1/external_sdram/U1/A<0>" LOC=3D"D14";
>
> Example of a failing IOBUF:
>
> --VHDL file (inside the submodule)
>
> =A0 =A0IOBUF_inst0 : IOBUF
> =A0 =A0generic map (
> =A0 =A0 =A0 DRIVE =3D> 12,
> =A0 =A0 =A0 IOSTANDARD =3D> "LVCMOS25",
> =A0 =A0 =A0 SLEW =3D> "SLOW")
> =A0 =A0port map (
> =A0 =A0 =A0 =A0 O =3D> DQ_OUT(0),
> =A0 =A0 =A0 IO =3D> DQ(0),
> =A0 =A0 =A0 I =3D> DQ_IN(0),
> =A0 =A0 =A0 T =3D> nDQ_OE);
>
> --UCF file
>
> NET "eight_chan_gen/u1/external_sdram/U1/DQ<0>" =A0 LOC =3D "A4";
>
> Any suggestions?
>
> Thanks in advance!

If the net had been succesfully brought all the way to a port at the
top level of the design the name should not include hierarchy.

Ed McGettigan
--
Xilinx Inc.

Article: 142927
Subject: Re: Mac OS X support for Sigasi HDT
From: Andy Peters <google@latke.net>
Date: Tue, 8 Sep 2009 13:36:03 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 7, 1:13=A0am, Hendrik <hendrik.eeckh...@gmail.com> wrote:
> Today, Sigasi proudly announces Mac OS X support for Sigasi HDT, an
> Intelligent Development Environment (IDE) for VHDL.
>
> Sigasi HDT is built upon the widely accepted Eclipse platform and
> contains an ultra-fast VHDL parser and compiler. As a result, the tool
> fully understands a design in terms of VHDL concepts.
>
> The tool is currently available in a public beta program. From user
> feedback, we learned that there is a significant interest in Mac OS X
> support.
>
> Sigasi HDT for Mac OS X is immediately available for download, please
> visithttp://www.sigasi.com/start.

Drat. I had hopes that Sigasi was a VHDL simulator that ran on OS X.
Nope, just another IDE. I'll keep emacs and its vhdl-mode, thanks.

-a

Article: 142928
Subject: Re: IMPACT-Xilinx Platform Cable USB II
From: Alex Freed <alex_news@mirrow.com>
Date: Tue, 08 Sep 2009 14:06:21 -0700
Links: << >>  << T >>  << A >>
Serkan wrote:
> 
>> I don't understand what you want to say with the last sentence.
> 
> 
> Even though I cant program the fpga most of the times, I found a weird
> solution to program it sometimes. It is like this:
>  I just unplug Xilinx platform cable USB II from my computer and and
> plug to another usb port, (after 10 tries it works)
>  I cant understand the reason behind this.
> 

I had a similar problem when another USB device also using an FTDI chip
was connected. Do you have say a USB to serial cable? Unplug it. If it 
helps get a new one using a different chip.


-Alex.


Article: 142929
Subject: Re: Bidirectional Bus
From: "Antti.Lukats@googlemail.com" <antti.lukats@googlemail.com>
Date: Tue, 8 Sep 2009 14:30:59 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 8, 4:34=A0am, nobody <cydrollin...@gmail.com> wrote:
> After programming an FPGA, XC3S250EVQ100, via Slave Parallel through
> an FTDI USB translator and a CPLD, XC2C64AVQ100, which synchronize
> data and fpga_cclk into the FPGA the done pin goes high. The problem I
> am having is the bidirectional does not release and allow the FPGA to
> drive the data bus to CPLD and then finally into an external 8 LED
> bank. I am fairly confident that the FPGA is loaded correctly with the
> bin file, by accident I reprogrammed the CPLD releasing the bus the
> FPGA, having been programmed, drove the bidirectional data bus and the
> lit the 8 LED bank appropriately. Any help on this issues would be
> apprciated, thank you. CODE:
>
> -------------------------------------------------------------------------=
---------
> -- Company: =A0 =A0 =A0 =A0 =A0 =A0 Electronic Realization L.L.C.
> -- Engineer: =A0 =A0 =A0 =A0 =A0 =A0Cy Drollinger
> -- Create Date: =A0 =A0 =A0 =A0 10:44:37 07/08/2009
> -- Design Name: =A0 =A0 =A0 =A0 USB/FPGA Spartan3E Develpoement
> -- Module Name: =A0 =A0 =A0 =A0 CPLD - Behavioral
> -- Project Name:
> -- Target Devices: =A0 =A0 =A0XC2C64A VQ100
> -- Tool versions:
> -- Description:
> -- Dependencies:
> -- Revision:
> -- Revision 0.01 - File Created
> -- Additional Comments:
> -------------------------------------------------------------------------=
---------
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> ---- Uncomment the following library declaration if instantiating
> ---- any Xilinx primitives in this code.
> library UNISIM;
> use UNISIM.VComponents.all;
>
> entity CPLD is
> =A0 =A0 Port ( =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--C=
PLD LOCATIONS
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --Master clock oscillator=
 50 MHz CTS - CB3
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 mclk : in =A0STD_LOGIC; =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 --pin 22
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 mclk_ce : out =A0STD_LOGIC; =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 --pin 70 Logic
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --Xilinx Spartan 3E VQ100=
 mode and variant
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Variant : out =A0STD_LOGIC_VECTOR (2 down=
to 0); =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --pin 34, 33, 30
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Mode : out =A0STD_LOGIC_VECTOR (2 downto =
0); =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--pin 42, 39=
, 36
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --Xilinx Spartan 3E VQ100
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_MOSI : out =A0STD_LOGIC; =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 --pin 90 this is also CSI_B
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_BUSY : in =A0STD_LOGIC; =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0--pin 91 if clk is less than 50 MHz
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_INITB : in =A0STD_LOGIC; =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 --pin 92
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_CSO_B : inout STD_LOGIC; =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --=
pin 94
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_cclk =A0 =A0 =A0 : out =A0 STD_LOGIC=
:=3D'0'; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --=
pin 27
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_done : inout =A0STD_LOGIC; =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 --pin 28
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_prog_B: inout STD_LOGIC; =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --=
pin 99
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_HSWAP: out STD_LOGIC; =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0--pin 24
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_D: inout STD_LOGIC_VECTOR(7 downto 0=
); =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --pin 89 81 79 78 77
> 41 40 35
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --Numonyx M25P16
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 SPI_flash_HOLD : out =A0STD_LOGIC; =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0--pin 76 SPI '1'
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 SPI_flash_W : out =A0STD_LOGIC; =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 --pin 97 =A0 =A0 =A0 =A0SPI '1'
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --FTDI FT245RL USB to par=
allel output
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 usb_pwren : inout =A0STD_LOGIC; =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 --pin 43
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 usb_wr : in =A0STD_LOGIC; =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 --pin 49
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 usb_rd : inout STD_LOGIC; =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --pin 50
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 data : inout =A0STD_LOGIC_VECTOR (7 downt=
o 0); =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--pin 56 53 55=
 61 52
> 60 58 64
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 usb_tx : in =A0STD_LOGIC; =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 --pin 67
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 usb_rx : in =A0STD_LOGIC; =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 --pin 68 when low data ready
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 usb_rst : inout =A0STD_LOGIC; =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 --pin 14
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --User I/O
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 LEDs : out =A0STD_LOGIC_VECTOR (8 downto =
1); =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--pin 1-4 an=
d 6-9
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 SW : inout =A0STD_LOGIC_VECTOR (2 downto =
0)); =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --pin 71, 72, =
74 need
> to be
>
> end CPLD;
>
> architecture Behavioral of CPLD is
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --FPGA Configuration
>
> signal SW_0_hi =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0:std_logic; =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --CPLD is in a all I/O pullups
> signal SW_1_hi =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0:std_logic; =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --CPLD is in a all I/O pullups
> signal SW_2_hi =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0:std_logic; =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --CPLD is in a all I/O pullups
> Signal fpga_timing =A0 =A0 =A0 =A0 =A0 =A0 =A0: integer range 0 to 256 =
=A0 =A0 =A0 =A0:=3D0;
> Signal bidir_bus =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0:std_logi=
c_vector (7 downto 0);
> Signal bidir_reg =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0:std_logi=
c_vector (7 downto 0);
> Signal done =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 :std_logic;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --FTDI USB chip overhead
>
> signal usb_dry =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0:std_lo=
gic; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --signal is a synchroni=
zed
> signal previous_usb_dry =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 :std_logic; =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --signal is the value of
> signal previous =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 :std_logic;
> Signal usb_timing =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : integer r=
ange 0 to 256 =A0 =A0 =A0 =A0:=3D4;
>
> BEGIN
>
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> -- Author =A0 =A0 =A0 =A0 =A0 =A0 =A0 : Cy Drollinger
> -- Date =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : 7-16-09
> -- Description =A0: synchronizing asynchronous inpoputs usb data ready
> line(sub_rx), =A0SW(0), SW(1), and SW(2)
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> --SIGNAL ASSIGNMENT
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 --HARDWARE SYSTEM ON PCB =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--TECHNICAL COMMENTS
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> Synchronize_inputs: process(mclk)
> begin
> =A0 =A0 if rising_edge(mclk) then
> =A0 =A0 =A0 if usb_rx =3D '0' then =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0-- RXF# =A0 =A0 =A0 =A0 is an active
> usb_dry <=3D '1';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else
> usb_dry <=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> previous <=3D usb_dry;
> previous_usb_dry <=3D previous;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if SW(0) =3D '1' then
> SW_0_hi <=3D '1';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else
> SW_0_hi <=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if SW(1) =3D '1' then
> SW_1_hi <=3D '1';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else
> SW_1_hi <=3D '0';
> =A0 =A0 =A0 =A0 =A0end if;
> =A0 =A0 =A0 =A0 =A0if SW(2) <=3D '1' then
> SW_2_hi <=3D '1';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else
> SW_2_hi <=3D '0';
> =A0 =A0 =A0 =A0 =A0end if;
> =A0 =A0 =A0 =A0 end if;
> end process;
>
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> -- Author =A0 =A0 =A0 =A0 =A0 =A0 =A0 : Cy Drollinger
> -- Date =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : 7-16-09
> -- Description =A0: Upon SW(1) going low the FGPA_prog_b pulses (ONE
> SHOT) high for two mclks.
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> --SIGNAL ASSIGNMENT
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 --HARDWARE SYSTEM ON PCB =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--TECHNICAL COMMENTS
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> Pulse_Prog_B: process (mclk) =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--
> begin
> =A0 =A0 =A0 =A0 if rising_edge(mclk) then
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if SW_1_hi =3D '0' and FPGA_timing < 22 t=
hen
> FPGA_timing <=3D FPGA_timing + 1;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if fpga_timing > 0 and fp=
ga_timing < 21 then
> fpga_prog_b <=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else
> fpga_prog_b <=3D '1'; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0-- fpga_prog_b held =
low for
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else =A0 =A0if SW_1_hi =3D '1' then
> fpga_timing <=3D 0;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 =A0 end if;
>
> end process;
>
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> -- Author =A0 =A0 =A0 =A0 =A0 =A0 =A0 : Cy Drollinger
> -- Date =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : 7-16-09
> -- Description =A0: providing timing for usb_rd through usb_data_rdy Data
> sheet DSFT245R1 pg. 12 fifo read
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> --SIGNAL ASSIGNMENT
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 --HARDWARE SYSTEM ON PCB =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--TECHNICAL COMMENTS
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> Load_FPGA_Slave_Parallel: process(mclk) =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 --
> begin
> =A0 =A0 =A0 =A0 if rising_edge(mclk) then
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if usb_dry =3D '1' and pr=
evious_usb_dry =3D'0' and fpga_initb =3D '1'
> then
> usb_timing <=3D 0;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif usb_timing < 5 then
> usb_timing <=3D usb_timing + 1;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 =A0 case usb_timing is
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 when 0 =3D>
> usb_rd <=3D'0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 when 1 =3D>
> usb_rd <=3D'0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 when 2 =3D>
> usb_rd <=3D'0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 when 3 =3D>
> usb_rd <=3D'0';
> fpga_cclk <=3D '1';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 when 4 =3D>
> usb_rd <=3D'1';
> fpga_cclk <=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 when others =3D>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end case;
> =A0 =A0 =A0 =A0 end if;
> end process;
>
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> -- Author =A0 =A0 =A0 =A0 =A0 =A0 =A0 : unknown
> -- Date =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : 9-7-09
> -- Description =A0: LED MUX between initial programming of FPGA and data
> out of FPGA
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> --SIGNAL ASSIGNMENT
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 --HARDWARE SYSTEM ON PCB =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--TECHNICAL COMMENTS
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> Bidirectional_FF: =A0 =A0PROCESS(mclk)
> =A0 =A0 BEGIN
> =A0 =A0 IF rising_edge(mclk) THEN =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- Creates the flipflops
> =A0 =A0 =A0 =A0 bidir_reg <=3D data;
> =A0 =A0 =A0 =A0 LEDs <=3D not(bidir_bus);
> =A0 =A0 =A0 =A0 END IF;
> =A0 =A0 END PROCESS;
>
> Bidirectional_Bus =A0PROCESS (FPGA_done, FPGA_d) =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--
> Behavioral representation
> =A0 =A0 =A0 =A0 BEGIN =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 -- of tri-states.
> =A0 =A0 =A0 =A0 IF FPGA_done =3D '1' =A0THEN
> =A0 =A0 =A0 =A0 =A0 =A0 FPGA_d <=3D "ZZZZZZZZ";
> =A0 =A0 =A0 =A0 =A0 =A0 bidir_bus <=3D FPGA_d;
> =A0 =A0 =A0 =A0 ELSE
> =A0 =A0 =A0 =A0 =A0 =A0 FPGA_d <=3D bidir_reg;
> =A0 =A0 =A0 =A0 =A0 =A0 bidir_bus <=3D FPGA_d;
> =A0 =A0 =A0 =A0 END IF;
> =A0 =A0 END PROCESS;
>
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> -- Author =A0 =A0 =A0 =A0 =A0 =A0 =A0 : Cy Drollinger
> -- Date =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : 6-18-09
> -- Description =A0: Hardwiring the CPLD for the board configuration of
> the usb and fpga
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> --SIGNAL ASSIGNMENT
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 --HARDWARE SYSTEM ON PCB =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--TECHNICAL COMMENTS
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 --Master clock oscillator 50 MHz CTS - CB3
> mclk_ce <=3D '1'; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--enables the 50=
 MHz
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 -- Xilinx Spartan 3E VQ100 mode and variant
> Mode <=3D "110"; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --mode Slave Parallel
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 --Xilinx Spartan 3E Slave Parallel
> fpga_mosi <=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 --FTDI USB PARALLEL
> usb_rst <=3D SW_0_hi;
> end Behavioral;

dear nobody!

just a comment, why do you write it so complex?
just write

FPGA_d <=3D "ZZZZZZZZ" when FPGA_done =3D '1'  else bidir_bus;

outside of process of course

it will defenetly put FPGA_d pins to tristate if done is 1

Antti




Article: 142930
Subject: Re: Bidirectional Bus
From: nobody <cydrollinger@gmail.com>
Date: Tue, 8 Sep 2009 15:58:02 -0700 (PDT)
Links: << >>  << T >>  << A >>

> Antti

Thanks Antti,

Ive tried that.

Cy drollinger

Article: 142931
Subject: Re: IMPACT-Xilinx Platform Cable USB II
From: doug <xx@xx.com>
Date: Tue, 08 Sep 2009 15:49:07 -0800
Links: << >>  << T >>  << A >>


Uwe Bonnes wrote:

> Serkan <oktem@su.sabanciuniv.edu> wrote:
> ...
> 
> 
>>I have tested the adapter it programs the other boards.
> 
> 
>>What I cant understand is what happens when I unplug the board or
>>adapter from my computer and plug again? how can it start to work/
>>program again what is it got to with the chain?
> 
> 
> I don't understand what you want to say with the last sentence.
> 
> But broken hardware, e.g. a JTAG Pin not soldered right can give a lott of
> problems, especially work from time to time and don't work else...
> 
I have seen issues where the cable acted like it locked up and had
to be removed and reinserted before it was useable. This has happened
with both the parallel and usb cables. Not having the power on in
the target will also generate the multiple devices found message at
times.

Article: 142932
Subject: Re: Virtex5 DDR2 ref design failed at JTAG programming with CRC error
From: vcar <hitsx@163.com>
Date: Tue, 8 Sep 2009 19:48:20 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 9=D4=C28=C8=D5, =C9=CF=CE=E710=CA=B147=B7=D6, Ed McGettigan <ed.mcgetti.=
..@xilinx.com> wrote:
> On Sep 7, 6:33 pm, vcar <hi...@163.com> wrote:
>
>
>
>
>
> > On 9=D4=C27=C8=D5, =C9=CF=CE=E74=CA=B145=B7=D6, Sean Durkin <news_MO...=
@tuxroot.de> wrote:
>
> > > vcar wrote:
> > > > I have found something else.
> > > > I used 4 DDR2 components to make a 64bits wide memory width. If I o=
nly
> > > > add serveral DCI IOs, e.g. the dqs_p/dqs_n pair (16 DCI IOs), FPGA
> > > > works fine.
> > > > However if I add 64 bits wide DQ, the FPGA crashes.
> > > > if I add only half of the DQ bus (32 bits wide), the FPGA will work
> > > > for a while and then crashes. and the JTAG chain remains functional
> > > > after programming, and becomes unaccessable after dozens of seconds=
.
>
> > > > So does this means I could not have 64 SSTL18_II_DCI and 16
> > > > DIFF_SSTL18_II_DCI in a Virtex5 LXT50 FF665 package?
>
> > > Theoretically this should be possible. You might run into SSO problem=
s
> > > and active cooling might be neccessary, but there's no restriction on
> > > the number of IOs using DCI that I know of.
>
> > > Maybe you have a power supply problem. DCI uses quite a lot of power.
> > > Have you measured your supply voltages in the three cases you mention=
ed?
> > > Are they stable and at nominal value in all cases? Does maybe the
> > > IO-supply drop when all DCI are enabled?
>
> > > A drop in the IO supply voltage should not impact the internal
> > > functionality, though, neither should the JTAG interface be affected
> > > (unless the IO bank 0 with the configuration pins uses the same volta=
ge).
>
> > > cu,
> > > Sean
>
> > You are right.
> > My power supply has something wrong definitely.
>
> > Now even I can run the DDR2 example design without DCI on the DQ bus,
> > and DDR2 operation also turns out to be right, I found that the FPGA
> > will still crash after about five minitues or so. And then I found
> > that all my power supply DC/DC circuit is very hot. It is quite
> > abnormal because the system total powe disspation is 12V @ 0.5A at
> > that time. While my DC/DC circuit is designed to handle 3.3V @ 10A
> > (other power rails is similar).
>
> > If there is a problem in my DC/DC circuit, which one would it be more
> > likely? The VCCO1.8V or VCCINT or VCCAUX or VCC3.3V?
>
> > Since at every crash the JTAG is unaccessable, should VCCAUX be
> > suspected?
> > Since DCI is related to VCCO1.8V, should VCCO1.8V be suspected?- Hide q=
uoted text -
>
> > - Show quoted text -
>
> In order to debug this you will need to get a scope probe in on each
> of the power supplies to see what is going on.
>
> Ed McGettigan
> --
> Xilinx Inc.- =D2=FE=B2=D8=B1=BB=D2=FD=D3=C3=CE=C4=D7=D6 -
>
> - =CF=D4=CA=BE=D2=FD=D3=C3=B5=C4=CE=C4=D7=D6 -

I checked all the power rails and found that the voltage of 1.8V power
rail wil drop dramatically after more DCI enabled I/O is used, and
this explains all the scenarios I met before.

I am about to check again what is wrong about my DC/DC circuit.

Thanks all of you!

Article: 142933
Subject: Re: Bidirectional Bus
From: "Antti.Lukats@googlemail.com" <antti.lukats@googlemail.com>
Date: Tue, 8 Sep 2009 21:07:46 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 9, 1:58=A0am, nobody <cydrollin...@gmail.com> wrote:
> > Antti
>
> Thanks Antti,
>
> Ive tried that.
>
> Cy drollinger

and? problem solved or not?

Antti

Article: 142934
Subject: Re: Xilinx USB CABLE SCHEMATIC NOW OFFICIALLY PUBLISED !!!! ::)
From: "." <eecsman@gmail.com>
Date: Tue, 8 Sep 2009 22:49:17 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 1, 1:06=A0am, "Antti.Luk...@googlemail.com"
<Antti.Luk...@googlemail.com> wrote:
> On Jul 31, 3:48=A0pm, "markman" <mark...@163.com> wrote:
>
>
>
> > >On Jun 28, 12:59=3DA0pm, "maxascent" <maxasc...@yahoo.co.uk> wrote:
> > >> What about the software required for theUSBchip and CPLD? Is this
> > >> included with ISE?
>
> > >> Jon
>
> > >yes, if you JUST replicate the hardware
> > >ISE should be able to update the CPLD
> > >well you need to preprogram the eeprom of course
>
> > >Antti
>
> > The content of EEPROM can be read by a simple IC programmer, but there'=
s
> > two problem2,first, how ISE update the CPLD? When conncetcableto host?
> > Or I need to programm the CPLD in ISE?
> > =A0Second, the CypressUSBcontroller need programmed or not?
>
> just program the eeprom
> ISE does the rest :)
>
> some german guys have tested it already..
>
> Antti

I have 2 questions:

1) Where can I get the file to program into the EEPROM?

2) What is the easiest way to program this EEPROM without an EEPROM
programmer?  Or what is the cheapest EEPROM programmer that can be
used with the EEPROM for this circuit?

Aaron

Article: 142935
Subject: Re: Xilinx USB CABLE SCHEMATIC NOW OFFICIALLY PUBLISED !!!! ::)
From: "Antti.Lukats@googlemail.com" <antti.lukats@googlemail.com>
Date: Tue, 8 Sep 2009 23:16:27 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 9, 8:49=A0am, "." <eecs...@gmail.com> wrote:
> On Aug 1, 1:06=A0am, "Antti.Luk...@googlemail.com"
>
>
>
> <Antti.Luk...@googlemail.com> wrote:
> > On Jul 31, 3:48=A0pm, "markman" <mark...@163.com> wrote:
>
> > > >On Jun 28, 12:59=3DA0pm, "maxascent" <maxasc...@yahoo.co.uk> wrote:
> > > >> What about the software required for theUSBchip and CPLD? Is this
> > > >> included with ISE?
>
> > > >> Jon
>
> > > >yes, if you JUST replicate the hardware
> > > >ISE should be able to update the CPLD
> > > >well you need to preprogram the eeprom of course
>
> > > >Antti
>
> > > The content of EEPROM can be read by a simple IC programmer, but ther=
e's
> > > two problem2,first, how ISE update the CPLD? When conncetcableto host=
?
> > > Or I need to programm the CPLD in ISE?
> > > =A0Second, the CypressUSBcontroller need programmed or not?
>
> > just program the eeprom
> > ISE does the rest :)
>
> > some german guys have tested it already..
>
> > Antti
>
> I have 2 questions:
>
> 1) Where can I get the file to program into the EEPROM?
>
> 2) What is the easiest way to program this EEPROM without an EEPROM
> programmer? =A0Or what is the cheapest EEPROM programmer that can be
> used with the EEPROM for this circuit?
>
> Aaron

cypress tools should be able to write the eeprom if you connect an
empty one

you can also check out this thread at german fpga forums

http://www.mikrocontroller.net/topic/142358#new

Antti


Article: 142936
Subject: ANN: Coding style guidance for FPGA memory
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Wed, 09 Sep 2009 10:19:09 +0100
Links: << >>  << T >>  << A >>
As promised several weeks ago, I've written up a document
and code examples - in both Verilog and VHDL - summarizing 
ways to create synthesizable memory in FPGAs.  It's not
rocket science; all the information in it is already 
available from synthesis and FPGA vendor docs.  However,
it may be helpful to have an independent summary of it 
in one place.  There's also a discussion of some possible
pitfalls that may be useful.

The PDF document, and source code examples, are available
for free download at

  http://www.doulos.com/knowhow/fpga/technotes/

We ask for registration, but if you accept the cookie you
can then get any other related downloads from our site
without re-registering.

On the same page there's also a document, written by my
colleague Alan Fitch, outlining various ways to make 
FPGA designs generic and re-usable in VHDL.

As always, suggestions for correction and improvement
of the content will be warmly welcomed.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 142937
Subject: Re: Traversing hierarchy in UCF works for OBUF, but not IOBUF, please
From: Telenochek <elet.mirror@gmail.com>
Date: Wed, 9 Sep 2009 07:46:59 -0700 (PDT)
Links: << >>  << T >>  << A >>
I would prefer to avoid bringing all the ports to top level.

I should be able to LOC constrain any internal signal of choice?

Article: 142938
Subject: Re: Bidirectional Bus
From: nobody <cydrollinger@gmail.com>
Date: Wed, 9 Sep 2009 08:28:59 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 8, 10:07=A0pm, "Antti.Luk...@googlemail.com"
<antti.luk...@googlemail.com> wrote:
> On Sep 9, 1:58=A0am, nobody <cydrollin...@gmail.com> wrote:
>
> > > Antti
>
> > Thanks Antti,
>
> > Ive tried that.
>
> > Cy drollinger
>
> and? problem solved or not?
>
> Antti

Antti,

No, That has the same effect as the current VDHL Bidirectional bus
attempt. The FPGA is being programmed but the bus does not release. It
releases when the CPLD is reprogrammed via JTAG, this is not an
option. I am not to familiar with driving a common trace between two
programmable chips and maybe missing something conceptually. I have
been just reading examples of bidirectional buses and have used a
couple different solutions, which are quite similar. All have the same
effect not releasing after the slave parallel programming of the FPGA
is complete. I might not be explaining the problem thoroughly. Well,
back at it. I will let you know when I get the problem solved.

Cy Drollinger

Article: 142939
Subject: Re: ANN: Coding style guidance for FPGA memory
From: Matthieu <matthieu.michon@gmail.com>
Date: Wed, 9 Sep 2009 08:41:37 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi Jonathan


Thanks for producing these very interesting documents.

Since I prefer to avoid using primitives, having a slick template for
declaring DPRAMs with the different R/W priority is a great help.  The
discussion about reuse and portability is a also very nice read !


Regards

Article: 142940
Subject: Re: Bidirectional Bus
From: "Antti.Lukats@googlemail.com" <antti.lukats@googlemail.com>
Date: Wed, 9 Sep 2009 09:03:38 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 9, 6:28=A0pm, nobody <cydrollin...@gmail.com> wrote:
> On Sep 8, 10:07=A0pm, "Antti.Luk...@googlemail.com"
>
> <antti.luk...@googlemail.com> wrote:
> > On Sep 9, 1:58=A0am, nobody <cydrollin...@gmail.com> wrote:
>
> > > > Antti
>
> > > Thanks Antti,
>
> > > Ive tried that.
>
> > > Cy drollinger
>
> > and? problem solved or not?
>
> > Antti
>
> Antti,
>
> No, That has the same effect as the current VDHL Bidirectional bus
> attempt. The FPGA is being programmed but the bus does not release. It
> releases when the CPLD is reprogrammed via JTAG, this is not an
> option. I am not to familiar with driving a common trace between two
> programmable chips and maybe missing something conceptually. I have
> been just reading examples of bidirectional buses and have used a
> couple different solutions, which are quite similar. All have the same
> effect not releasing after the slave parallel programming of the FPGA
> is complete. I might not be explaining the problem thoroughly. Well,
> back at it. I will let you know when I get the problem solved.
>
> Cy Drollinger

connect done to JUMPER
bus to free IO
test

the code works, so if you dont see bus released problem is somewhere
else

Antti



Article: 142941
Subject: Re: ANN: Coding style guidance for FPGA memory
From: DJ Delorie <dj@delorie.com>
Date: 09 Sep 2009 12:48:18 -0400
Links: << >>  << T >>  << A >>

Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> writes:
> We ask for registration,

Er, your privacy policy says you can spam us and change your policy at
any time.  Can we get something a little more user-friendly than that?

Article: 142942
Subject: Re: Traversing hierarchy in UCF works for OBUF, but not IOBUF, please
From: gabor <gabor@alacron.com>
Date: Wed, 9 Sep 2009 10:14:55 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 9, 10:46=A0am, Telenochek <elet.mir...@gmail.com> wrote:
> I would prefer to avoid bringing all the ports to top level.
>
> I should be able to LOC constrain any internal signal of choice?

You should be able to, theoretically, but in the end it is useful
to have access to the board pins from the top level module as
it makes it much easier to attach them to the SDRAM simulation
model in your testbench.

Article: 142943
Subject: Re: Traversing hierarchy in UCF works for OBUF, but not IOBUF, please
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Wed, 9 Sep 2009 10:22:29 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 9, 7:46=A0am, Telenochek <elet.mir...@gmail.com> wrote:
> I would prefer to avoid bringing all the ports to top level.
>
> I should be able to LOC constrain any internal signal of choice?

IMHO not bring your IO to the level is a mistake for the following
reasons

- Signals that aren't used or driven are usually removed from the
design during synthesis
- Synthesis won't "know" to insert IO buffers on these nets requiring
the IO buffers to be instantiated in the HDL
- System level simulation won't be possible as the IOs are not
accessible

Ed McGettigan
--
Xilinx Inc.

Article: 142944
Subject: Re: ANN: Coding style guidance for FPGA memory
From: Mike Treseler <mtreseler@gmail.com>
Date: Wed, 09 Sep 2009 10:23:23 -0700
Links: << >>  << T >>  << A >>
DJ Delorie wrote:
> Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> writes:
>> We ask for registration,
> 
> Er, your privacy policy says you can spam us and change your policy at
> any time.  Can we get something a little more user-friendly than that?

I haven't been spammed yet.
There is a checkbox option to turn email off.

Note that tested vhdl synthesis examples that
that make use of vhdl's unfair adavantages
as well as standard libraries, are rare.

       -- Mike Treseler




Article: 142945
Subject: Re: Bidirectional Bus
From: nobody <cydrollinger@gmail.com>
Date: Wed, 9 Sep 2009 10:37:56 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 9, 10:03=A0am, "Antti.Luk...@googlemail.com"
<antti.luk...@googlemail.com> wrote:
> On Sep 9, 6:28=A0pm, nobody <cydrollin...@gmail.com> wrote:
>
>
>
> > On Sep 8, 10:07=A0pm, "Antti.Luk...@googlemail.com"
>
> > <antti.luk...@googlemail.com> wrote:
> > > On Sep 9, 1:58=A0am, nobody <cydrollin...@gmail.com> wrote:
>
> > > > > Antti
>
> > > > Thanks Antti,
>
> > > > Ive tried that.
>
> > > > Cy drollinger
>
> > > and? problem solved or not?
>
> > > Antti
>
> > Antti,
>
> > No, That has the same effect as the current VDHL Bidirectional bus
> > attempt. The FPGA is being programmed but the bus does not release. It
> > releases when the CPLD is reprogrammed via JTAG, this is not an
> > option. I am not to familiar with driving a common trace between two
> > programmable chips and maybe missing something conceptually. I have
> > been just reading examples of bidirectional buses and have used a
> > couple different solutions, which are quite similar. All have the same
> > effect not releasing after the slave parallel programming of the FPGA
> > is complete. I might not be explaining the problem thoroughly. Well,
> > back at it. I will let you know when I get the problem solved.
>
> > Cy Drollinger
>
> connect done to JUMPER
> bus to free IO
> test
>
> the code works, so if you dont see bus released problem is somewhere
> else
>
> Antti

Antti,

What about the synthesis tool not actually handling the the VHDL
statement:

the_bus <=3D "ZZZZZZZZ" when FPGA_done =3D'1' else bus_reg;

in the appropriate way. I asked a question about setting a pullup on a
few of the Switch pins of the CPLD and I learned that using a pullup
on one of the pin in the XC2C64A causes all pins to in a pullup state.
After talking with another individual their maybe some primitives that
need to be instantiated in order for the the high Z bus to be
implemented?
I know the CPLD programs the FPGA I know the FPGA_done pin goes high,
100 ns, I know the FPGA can drive the LEDs through the CPLD and the
pins that programmed the FPGA, but not immediately after the CPLD
programs the FPGA. The CPLD must be reprogrammed through the JTAG
leading me to believe there is something wrong with the above VHDL
statement either in timing, something hangs, or the synthesis tool is
not performing what I think I am asking it to do, Go to a high Z state
after the FPGA is programmed.

Antti, Thank you for taking time to give solutions and time thinking
about my problem, it is appreciated.

Cy Drollinger

Article: 142946
Subject: Re: Bidirectional Bus
From: "Antti.Lukats@googlemail.com" <antti.lukats@googlemail.com>
Date: Wed, 9 Sep 2009 11:19:02 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 9, 8:37=A0pm, nobody <cydrollin...@gmail.com> wrote:
> On Sep 9, 10:03=A0am, "Antti.Luk...@googlemail.com"
>
>
>
> <antti.luk...@googlemail.com> wrote:
> > On Sep 9, 6:28=A0pm, nobody <cydrollin...@gmail.com> wrote:
>
> > > On Sep 8, 10:07=A0pm, "Antti.Luk...@googlemail.com"
>
> > > <antti.luk...@googlemail.com> wrote:
> > > > On Sep 9, 1:58=A0am, nobody <cydrollin...@gmail.com> wrote:
>
> > > > > > Antti
>
> > > > > Thanks Antti,
>
> > > > > Ive tried that.
>
> > > > > Cy drollinger
>
> > > > and? problem solved or not?
>
> > > > Antti
>
> > > Antti,
>
> > > No, That has the same effect as the current VDHL Bidirectional bus
> > > attempt. The FPGA is being programmed but the bus does not release. I=
t
> > > releases when the CPLD is reprogrammed via JTAG, this is not an
> > > option. I am not to familiar with driving a common trace between two
> > > programmable chips and maybe missing something conceptually. I have
> > > been just reading examples of bidirectional buses and have used a
> > > couple different solutions, which are quite similar. All have the sam=
e
> > > effect not releasing after the slave parallel programming of the FPGA
> > > is complete. I might not be explaining the problem thoroughly. Well,
> > > back at it. I will let you know when I get the problem solved.
>
> > > Cy Drollinger
>
> > connect done to JUMPER
> > bus to free IO
> > test
>
> > the code works, so if you dont see bus released problem is somewhere
> > else
>
> > Antti
>
> Antti,
>
> What about the synthesis tool not actually handling the the VHDL
> statement:
>
> the_bus <=3D "ZZZZZZZZ" when FPGA_done =3D'1' else bus_reg;
>
> in the appropriate way. I asked a question about setting a pullup on a
> few of the Switch pins of the CPLD and I learned that using a pullup
> on one of the pin in the XC2C64A causes all pins to in a pullup state.
> After talking with another individual their maybe some primitives that
> need to be instantiated in order for the the high Z bus to be
> implemented?
> I know the CPLD programs the FPGA I know the FPGA_done pin goes high,
> 100 ns, I know the FPGA can drive the LEDs through the CPLD and the
> pins that programmed the FPGA, but not immediately after the CPLD
> programs the FPGA. The CPLD must be reprogrammed through the JTAG
> leading me to believe there is something wrong with the above VHDL
> statement either in timing, something hangs, or the synthesis tool is
> not performing what I think I am asking it to do, Go to a high Z state
> after the FPGA is programmed.
>
> Antti, Thank you for taking time to give solutions and time thinking
> about my problem, it is appreciated.
>
> Cy Drollinger


the_bus <=3D "ZZZZZZZZ" when FPGA_done =3D'1' else bus_reg;

this WILL RELEASE the pins.
even Xilinx tools cant be that bad to fail on this.

if this is what you have, and FPGA_done IS 1
then bus is tristated as well

if not take a break.
it helps

if you think the synthesis tools fail, DO AS I TOLD YOU
make the "Z" on spare pins of the CPLD and check with multimeter and
finger

what you are doing is SO simple.. its hard todo it wrong...

Antti









Article: 142947
Subject: Re: Bidirectional Bus
From: "Antti.Lukats@googlemail.com" <antti.lukats@googlemail.com>
Date: Wed, 9 Sep 2009 11:21:51 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 8, 4:34=A0am, nobody <cydrollin...@gmail.com> wrote:
> After programming an FPGA, XC3S250EVQ100, via Slave Parallel through
> an FTDI USB translator and a CPLD, XC2C64AVQ100, which synchronize
> data and fpga_cclk into the FPGA the done pin goes high. The problem I
> am having is the bidirectional does not release and allow the FPGA to
> drive the data bus to CPLD and then finally into an external 8 LED
> bank. I am fairly confident that the FPGA is loaded correctly with the
> bin file, by accident I reprogrammed the CPLD releasing the bus the
> FPGA, having been programmed, drove the bidirectional data bus and the
> lit the 8 LED bank appropriately. Any help on this issues would be
> apprciated, thank you. CODE:
>
> -------------------------------------------------------------------------=
---------
> -- Company: =A0 =A0 =A0 =A0 =A0 =A0 Electronic Realization L.L.C.
> -- Engineer: =A0 =A0 =A0 =A0 =A0 =A0Cy Drollinger
> -- Create Date: =A0 =A0 =A0 =A0 10:44:37 07/08/2009
> -- Design Name: =A0 =A0 =A0 =A0 USB/FPGA Spartan3E Develpoement
> -- Module Name: =A0 =A0 =A0 =A0 CPLD - Behavioral
> -- Project Name:
> -- Target Devices: =A0 =A0 =A0XC2C64A VQ100
> -- Tool versions:
> -- Description:
> -- Dependencies:
> -- Revision:
> -- Revision 0.01 - File Created
> -- Additional Comments:
> -------------------------------------------------------------------------=
---------
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> ---- Uncomment the following library declaration if instantiating
> ---- any Xilinx primitives in this code.
> library UNISIM;
> use UNISIM.VComponents.all;
>
> entity CPLD is
> =A0 =A0 Port ( =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--C=
PLD LOCATIONS
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --Master clock oscillator=
 50 MHz CTS - CB3
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 mclk : in =A0STD_LOGIC; =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 --pin 22
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 mclk_ce : out =A0STD_LOGIC; =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 --pin 70 Logic
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --Xilinx Spartan 3E VQ100=
 mode and variant
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Variant : out =A0STD_LOGIC_VECTOR (2 down=
to 0); =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --pin 34, 33, 30
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Mode : out =A0STD_LOGIC_VECTOR (2 downto =
0); =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--pin 42, 39=
, 36
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --Xilinx Spartan 3E VQ100
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_MOSI : out =A0STD_LOGIC; =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 --pin 90 this is also CSI_B
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_BUSY : in =A0STD_LOGIC; =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0--pin 91 if clk is less than 50 MHz
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_INITB : in =A0STD_LOGIC; =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 --pin 92
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_CSO_B : inout STD_LOGIC; =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --=
pin 94
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_cclk =A0 =A0 =A0 : out =A0 STD_LOGIC=
:=3D'0'; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --=
pin 27
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_done : inout =A0STD_LOGIC; =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 --pin 28
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_prog_B: inout STD_LOGIC; =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --=
pin 99
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_HSWAP: out STD_LOGIC; =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0--pin 24
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_D: inout STD_LOGIC_VECTOR(7 downto 0=
); =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --pin 89 81 79 78 77
> 41 40 35
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --Numonyx M25P16
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 SPI_flash_HOLD : out =A0STD_LOGIC; =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0--pin 76 SPI '1'
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 SPI_flash_W : out =A0STD_LOGIC; =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 --pin 97 =A0 =A0 =A0 =A0SPI '1'
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --FTDI FT245RL USB to par=
allel output
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 usb_pwren : inout =A0STD_LOGIC; =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 --pin 43
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 usb_wr : in =A0STD_LOGIC; =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 --pin 49
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 usb_rd : inout STD_LOGIC; =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --pin 50
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 data : inout =A0STD_LOGIC_VECTOR (7 downt=
o 0); =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--pin 56 53 55=
 61 52
> 60 58 64
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 usb_tx : in =A0STD_LOGIC; =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 --pin 67
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 usb_rx : in =A0STD_LOGIC; =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 --pin 68 when low data ready
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 usb_rst : inout =A0STD_LOGIC; =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 --pin 14
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --User I/O
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 LEDs : out =A0STD_LOGIC_VECTOR (8 downto =
1); =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--pin 1-4 an=
d 6-9
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 SW : inout =A0STD_LOGIC_VECTOR (2 downto =
0)); =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --pin 71, 72, =
74 need
> to be
>
> end CPLD;
>
> architecture Behavioral of CPLD is
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --FPGA Configuration
>
> signal SW_0_hi =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0:std_logic; =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --CPLD is in a all I/O pullups
> signal SW_1_hi =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0:std_logic; =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --CPLD is in a all I/O pullups
> signal SW_2_hi =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0:std_logic; =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --CPLD is in a all I/O pullups
> Signal fpga_timing =A0 =A0 =A0 =A0 =A0 =A0 =A0: integer range 0 to 256 =
=A0 =A0 =A0 =A0:=3D0;
> Signal bidir_bus =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0:std_logi=
c_vector (7 downto 0);
> Signal bidir_reg =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0:std_logi=
c_vector (7 downto 0);
> Signal done =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 :std_logic;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --FTDI USB chip overhead
>
> signal usb_dry =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0:std_lo=
gic; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --signal is a synchroni=
zed
> signal previous_usb_dry =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 :std_logic; =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --signal is the value of
> signal previous =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 :std_logic;
> Signal usb_timing =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : integer r=
ange 0 to 256 =A0 =A0 =A0 =A0:=3D4;
>
> BEGIN
>
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> -- Author =A0 =A0 =A0 =A0 =A0 =A0 =A0 : Cy Drollinger
> -- Date =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : 7-16-09
> -- Description =A0: synchronizing asynchronous inpoputs usb data ready
> line(sub_rx), =A0SW(0), SW(1), and SW(2)
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> --SIGNAL ASSIGNMENT
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 --HARDWARE SYSTEM ON PCB =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--TECHNICAL COMMENTS
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> Synchronize_inputs: process(mclk)
> begin
> =A0 =A0 if rising_edge(mclk) then
> =A0 =A0 =A0 if usb_rx =3D '0' then =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0-- RXF# =A0 =A0 =A0 =A0 is an active
> usb_dry <=3D '1';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else
> usb_dry <=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> previous <=3D usb_dry;
> previous_usb_dry <=3D previous;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if SW(0) =3D '1' then
> SW_0_hi <=3D '1';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else
> SW_0_hi <=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if SW(1) =3D '1' then
> SW_1_hi <=3D '1';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else
> SW_1_hi <=3D '0';
> =A0 =A0 =A0 =A0 =A0end if;
> =A0 =A0 =A0 =A0 =A0if SW(2) <=3D '1' then
> SW_2_hi <=3D '1';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else
> SW_2_hi <=3D '0';
> =A0 =A0 =A0 =A0 =A0end if;
> =A0 =A0 =A0 =A0 end if;
> end process;
>
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> -- Author =A0 =A0 =A0 =A0 =A0 =A0 =A0 : Cy Drollinger
> -- Date =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : 7-16-09
> -- Description =A0: Upon SW(1) going low the FGPA_prog_b pulses (ONE
> SHOT) high for two mclks.
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> --SIGNAL ASSIGNMENT
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 --HARDWARE SYSTEM ON PCB =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--TECHNICAL COMMENTS
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> Pulse_Prog_B: process (mclk) =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--
> begin
> =A0 =A0 =A0 =A0 if rising_edge(mclk) then
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if SW_1_hi =3D '0' and FPGA_timing < 22 t=
hen
> FPGA_timing <=3D FPGA_timing + 1;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if fpga_timing > 0 and fp=
ga_timing < 21 then
> fpga_prog_b <=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else
> fpga_prog_b <=3D '1'; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0-- fpga_prog_b held =
low for
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else =A0 =A0if SW_1_hi =3D '1' then
> fpga_timing <=3D 0;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 =A0 end if;
>
> end process;
>
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> -- Author =A0 =A0 =A0 =A0 =A0 =A0 =A0 : Cy Drollinger
> -- Date =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : 7-16-09
> -- Description =A0: providing timing for usb_rd through usb_data_rdy Data
> sheet DSFT245R1 pg. 12 fifo read
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> --SIGNAL ASSIGNMENT
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 --HARDWARE SYSTEM ON PCB =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--TECHNICAL COMMENTS
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> Load_FPGA_Slave_Parallel: process(mclk) =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 --
> begin
> =A0 =A0 =A0 =A0 if rising_edge(mclk) then
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if usb_dry =3D '1' and pr=
evious_usb_dry =3D'0' and fpga_initb =3D '1'
> then
> usb_timing <=3D 0;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif usb_timing < 5 then
> usb_timing <=3D usb_timing + 1;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 =A0 case usb_timing is
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 when 0 =3D>
> usb_rd <=3D'0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 when 1 =3D>
> usb_rd <=3D'0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 when 2 =3D>
> usb_rd <=3D'0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 when 3 =3D>
> usb_rd <=3D'0';
> fpga_cclk <=3D '1';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 when 4 =3D>
> usb_rd <=3D'1';
> fpga_cclk <=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 when others =3D>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end case;
> =A0 =A0 =A0 =A0 end if;
> end process;
>
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> -- Author =A0 =A0 =A0 =A0 =A0 =A0 =A0 : unknown
> -- Date =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : 9-7-09
> -- Description =A0: LED MUX between initial programming of FPGA and data
> out of FPGA
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> --SIGNAL ASSIGNMENT
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 --HARDWARE SYSTEM ON PCB =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--TECHNICAL COMMENTS
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> Bidirectional_FF: =A0 =A0PROCESS(mclk)
> =A0 =A0 BEGIN
> =A0 =A0 IF rising_edge(mclk) THEN =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- Creates the flipflops
> =A0 =A0 =A0 =A0 bidir_reg <=3D data;
> =A0 =A0 =A0 =A0 LEDs <=3D not(bidir_bus);
> =A0 =A0 =A0 =A0 END IF;
> =A0 =A0 END PROCESS;
>
> Bidirectional_Bus =A0PROCESS (FPGA_done, FPGA_d) =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--
> Behavioral representation
> =A0 =A0 =A0 =A0 BEGIN =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 -- of tri-states.
> =A0 =A0 =A0 =A0 IF FPGA_done =3D '1' =A0THEN
> =A0 =A0 =A0 =A0 =A0 =A0 FPGA_d <=3D "ZZZZZZZZ";
> =A0 =A0 =A0 =A0 =A0 =A0 bidir_bus <=3D FPGA_d;
> =A0 =A0 =A0 =A0 ELSE
> =A0 =A0 =A0 =A0 =A0 =A0 FPGA_d <=3D bidir_reg;
> =A0 =A0 =A0 =A0 =A0 =A0 bidir_bus <=3D FPGA_d;
> =A0 =A0 =A0 =A0 END IF;
> =A0 =A0 END PROCESS;
>
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> -- Author =A0 =A0 =A0 =A0 =A0 =A0 =A0 : Cy Drollinger
> -- Date =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : 6-18-09
> -- Description =A0: Hardwiring the CPLD for the board configuration of
> the usb and fpga
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> --SIGNAL ASSIGNMENT
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 --HARDWARE SYSTEM ON PCB =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--TECHNICAL COMMENTS
> -------------------------------------------------------------------------=
-------------------------------------------------------------
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 --Master clock oscillator 50 MHz CTS - CB3
> mclk_ce <=3D '1'; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--enables the 50=
 MHz
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 -- Xilinx Spartan 3E VQ100 mode and variant
> Mode <=3D "110"; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --mode Slave Parallel
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 --Xilinx Spartan 3E Slave Parallel
> fpga_mosi <=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 --FTDI USB PARALLEL
> usb_rst <=3D SW_0_hi;
> end Behavioral;

BTW why are you doing something like this?
to clone that
http://www.demandperipherals.com/

there is no reason todo that IMHO

Antti
PS there is no reason to connect data bus to the CPLD :)

the SPI flash can be programmed without that too..
so just DISCONNECT the data bus from the cpld
connect FT245 to FPGA directly






Article: 142948
Subject: Xilinx TCL and Cygwin
From: Rob Gaddi <rgaddi@technologyhighland.com>
Date: Wed, 9 Sep 2009 14:38:39 -0700
Links: << >>  << T >>  << A >>
I was just starting to try to do some playing with TCL, and ran into an
interesting problem.  If you're running bash through Cygwin:

A) Trying to run xtclsh just hangs entirely, forcing you to kill the
process.

B) The built-in Cygwin tclsh seems to work fine, but when you try to
execute the line >> source $env(XILINX)/bin/xilinx-init.tcl << you get
the response "The XILINX environment variable is not set or is empty."
with XILINX set to either C:/Xilinx/11.1/ISE or
to /cygdrive/c/Xilinx/11.1/ISE.

xtclsh runs fine when executed under the normal Windows XP cmd shell,
but if I've got to sit around hopping back and forth between shells its
going to make for a very complicated build process.

I figured CAF was about the only place where someone might know about
working with TCL scripts for Xilinx designs under Cygwin.  So...anyone?

Thanks,
Rob

-- 
Rob Gaddi, Highland Technology
Email address is currently out of order

Article: 142949
Subject: Re: Xilinx TCL and Cygwin
From: Muzaffer Kal <kal@dspia.com>
Date: Wed, 09 Sep 2009 15:14:50 -0700
Links: << >>  << T >>  << A >>
On Wed, 9 Sep 2009 14:38:39 -0700, Rob Gaddi
<rgaddi@technologyhighland.com> wrote:

>I was just starting to try to do some playing with TCL, and ran into an
>interesting problem.  If you're running bash through Cygwin:
>
>A) Trying to run xtclsh just hangs entirely, forcing you to kill the
>process.
>
>B) The built-in Cygwin tclsh seems to work fine, but when you try to
>execute the line >> source $env(XILINX)/bin/xilinx-init.tcl << you get
>the response "The XILINX environment variable is not set or is empty."
>with XILINX set to either C:/Xilinx/11.1/ISE or
>to /cygdrive/c/Xilinx/11.1/ISE.

Could be your version of windows or cygwin. Under Vista 64 SP2 and
cygwin 1.5.25-15 everything above works.
-- 
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com



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