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"Antti.Lukats@googlemail.com" <antti.lukats@googlemail.com> wrote:
>On Sep 27, 11:51=A0pm, n...@puntnl.niks (Nico Coesel) wrote:
>> "Antti.Luk...@googlemail.com" <antti.luk...@googlemail.com> wrote:
>> >On Sep 26, 8:39=3DA0pm, rickman <gnu...@gmail.com> wrote:
>> >> On Sep 23, 12:57=3DA0pm, "Antti.Luk...@googlemail.com"
>>
>> >> <antti.luk...@googlemail.com> wrote:
>> >> > On Sep 23, 7:38=3DA0pm, rickman <gnu...@gmail.com> wrote:
>>
>> >> > > On Sep 23, 11:58=3DA0am, nobody <cydrollin...@gmail.com> wrote:
>>
>> >> > > > Antti,
>>
>> >> > > > I enjoy your responses they are to the bone, but valid. The righ=
>t
>> >> > > > people are engineers who wish to pick this project up for their
>> that the standard S3 parts. You seem obsessed with flash. FYI none of
>> the designs I ever worked on used flash to store the FPGA
>> configuration. Flash isn't a big deal for everyone.
>>
>> --
>> Failure does not prove something is impossible, failure simply
>> indicates you are not using the right tools...
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"If it doesn't fit, use a bigg=
>er hammer!"
>> --------------------------------------------------------------
>
>I very seldom call others people comments "load of crap"
Me too.
>sure S3e is useful chip, and i have said there could
>be valid reasons to use it also (if you did read my postings)
>as of S3AN <> S3A, it doesnt have to be S3AN, S3A
>is pretty much useable too (or S3ADSP even better),
>so if you Nico do not like Flash you could use S3A right?
>
>"none of the designs you worked did ever use flash to store
>FPGA configuration" - Nico is it really so? You never
>used a desgin with Parallel Flash conf?
>never a design with Serial flash conf?
>xilinx platform flash is flash too, ever used?
Never.
>did you only use OTP in ALL your designs?
Nope. In my world there is always a microcontroller or SoC which has
very convenient ways to update firmware and other data (including the
FPGA configuration). On one design I worked on there can be several
different I/O modules connected to an FPGA. The microcontroller first
loads a small default config and after that the FPHA config for the
particular module is loaded.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 143276Can we program a bitstream in the Daughter Board Spartan 3 of the Altium nanoboard with Xilinx impact instead of Altium Designer ? If yes, which JTAG must be used with which connectors ? I have read interesting stuff on that subject here : http://wiki.altium.com/display/ADOH/Updating+the+Firmware+on+the+Desktop+NanoBoard+NB2DSK01 I copy/paste : If you have an older, Altium Universal JTAG Interface, use this to connect from the parallel port on your PC to the 'SYSTEM JTAG' header. Note that the selector switch on the Universal JTAG Interface is used only when programming a JTAG device from Altera Quartus II or Xilinx ISE tools directly, and via their associated parallel cabling. The switch position has no relevance when programming the Configuration PROM from Altium Designer. and there : http://www.altium.com/files/pdfs/Connecting-the-Universal-JTAG-Interface-to-the-Altium-NanoBoard-NB1.pdf But I need more informations ... Thanks in advance, CyrilleArticle: 143277
On Sep 29, 1:47=A0pm, Uwe Bonnes <b...@elektron.ikp.physik.tu- darmstadt.de> wrote: > Hello, > > in quest for the HDL source files for the Spartan 6 SP601 Demo board and > application, all I find ishttp://forums.xilinx.com/xlnx/board/message?boa= rd.id=3DSpartan&thread.i... > > > BTW, the design files are 'Coming Soon'.... > > Some zip files are available at > > http://www.xilinx.com/products/boards/sp601/reference_designs.htm > > but they contain very few .v files. > > This seems not enough to rebuild (and later adapt) the Ethernet/DSP > application delivered with the board. Even not to bebuild the build-in se= lf > test... > > Any news about those HDL files? > > Thanks > -- > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar= mstadt.de > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- rdf0015.zip includes all files needed for the rebuild, but you need EDK of course AnttiArticle: 143278
On Sep 29, 1:47=A0pm, Uwe Bonnes <b...@elektron.ikp.physik.tu- darmstadt.de> wrote: > Hello, > > in quest for the HDL source files for the Spartan 6 SP601 Demo board and > application, all I find ishttp://forums.xilinx.com/xlnx/board/message?boa= rd.id=3DSpartan&thread.i... > > > BTW, the design files are 'Coming Soon'.... > > Some zip files are available at > > http://www.xilinx.com/products/boards/sp601/reference_designs.htm > > but they contain very few .v files. > > This seems not enough to rebuild (and later adapt) the Ethernet/DSP > application delivered with the board. Even not to bebuild the build-in se= lf > test... > > Any news about those HDL files? > > Thanks > -- > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar= mstadt.de > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- hm i guess you did mean rdf0003.zip Xilinx is bullshitting again, i would say, there is documentation how to use the BSRD BIT file, but no source code. to Xilinx: NO ONE who is buying SP601 or any other Xilinx board is interested to check out if Xilinx supplied BIT files work or not. Xilinx has todo in house testing, clients can expect it has done, so there is no need the customers verify that using the BIT files. the customers NEED the reference desing SOURCE files, if those are not available, may as well take the SP601 and try its flying capabilities. probably its just a small delay, but hey the boards are out, so should be refernece designs as well? AnttiArticle: 143279
On Sep 29, 7:41=A0am, rickman <gnu...@gmail.com> wrote: > On Sep 28, 8:05=A0pm, emeb <ebromba...@gmail.com> wrote: > > > On Sep 28, 10:00=A0am, Andy Peters <goo...@latke.net> wrote: > > > > Another thing is that S3E appears to be available in more packages > > > than S3A so you might be able to find a better fit for a particular > > > design. > > > That's my principle objection to the S3A family. I buy my parts from > > Digi-Key, and the only non-BGA packages for S3A are the 50K devices. I > > have fairly limited assembly resources so BGA / QFN parts aren't > > possible, but I want larger devices. What to do? > > This is one of my complaints about FPGA vendors. =A0Of course, they are > responding to the market and the profit figure. =A0But my designs > typically use small, cramped boards and BGAs are typically not an > improvement over the right size leaded package. =A0Yes, the BGA looks > smaller on the data sheet, but they typically require a board with > more layers and they use real estate on *both* sides of the board > unless you want to use some pretty exotic technology such as blind > vias. =A0I did a calculation yesterday and found that one of the two low > pin count leadless packages for the S6 parts uses less real estate > than a 100 TQFP by going to a 0.5 mm ball pitch. =A0The other one is > "smaller" but after counting the other side of the board as being > used, actually is 30% larger with a 0.8 mm ball pitch. > > And that doesn't consider that these parts are all moe expensive > because of the higher I/O count making higher testing costs. > > I'm just not a fan of BGA and CS technology for my designs. > > Rick I'm with you on this. I'm doing hobby stuff, so I want small-ish boards and inexpensive, readily available parts. I ended up using an S3E250 in a VQ100 package. I use slave serial mode and load it up from an ARM processor, with the bitfile stored in a micro SD card. Here's more on the design: http://members.cox.net/ebrombaugh1/synth/armfpga/index.html It's a fun little board and it came up without any major hitches. Just two layers too. EricArticle: 143280
On Sep 28, 12:32=A0pm, "sheva25" <gilberto2...@gmail.com> wrote: > Hi everyone, > > First of all im a noob in VHDL, i only know the basic. But I have a proje= ct > that its really hard for me. > > I hope that you guys could help me, im going to explain the project: > > We have to use a keyboard to input any data on a spartan 3E and show that > info on the LCD display, then send that info to another spartan 3E, we > should see the received data on the LCD display too. > > Then we have to input any data on the second spartan and send it back to > the first one, all the info need to be display on boths LCD. > > The communication between the two Spartans should be wireless but if you > think that is too hard then i think that we can use a wired communication= . > > I have read that we have to use something abouts sockets and microblaze b= ut > im not sure at all. > > Thank You for your time!! ouah that 's cool google have a category to put in this author when you report is profile to be abusive: "According to the laws of my country, this profile is illegal." >> that's fit pretty well as it is forbidden to try make others people do y= our own homework in my country and as it seems to have no use of his head w= e should us as sanction a guillotine ;)Article: 143281
I like the site and the board, nice work! what is your intention for the board looks like everything is available for another to reproduce it. I dont get it whats the deal with only two layers, four is only two more? Sincerely, CyArticle: 143282
On Sep 29, 10:22=A0pm, nobody <cydrollin...@gmail.com> wrote: > I like the site and the board, nice work! what is your intention for > the board looks like everything is available for another to reproduce > it. I dont get it whats the deal with only two layers, four is only > two more? > > Sincerely, > > Cy it is a nice board! something even i may want to have, i have one spare 100E maybe i just order this PCB :) what with 2 layers? some can do on 2, some cant. thats the difference. sure 4 is only 2 more than 2 and 6 is only 2 more than 4 so why not start with 12 layers? AnttiArticle: 143283
On Sep 29, 12:29=A0pm, "Antti.Luk...@googlemail.com" <antti.luk...@googlemail.com> wrote: > On Sep 29, 10:22=A0pm, nobody <cydrollin...@gmail.com> wrote: > > > I like the site and the board, nice work! what is your intention for > > the board looks like everything is available for another to reproduce > > it. I dont get it whats the deal with only two layers, four is only > > two more? > > > Sincerely, > > > Cy > > it is a nice board! > something even i may want to have, i have one spare 100E > maybe i just order this PCB :) > > what with 2 layers? > > some can do on 2, some cant. > thats the difference. > > sure 4 is only 2 more than 2 > and 6 is only 2 more than 4 > so why not start with 12 layers? > > Antti @Cy - Thanks for the compliments. The board fab I use charges significantly more for 4 layers than 2, so I try to do 2 layers only. My original intention was to make the design available for some of the folks on a mail list devoted to using FPGAs for electronic music. After I built & tested it no one else ever followed though. @Antti - Thanks. All the design materials are free for any use, although I haven't included any specific copyright claims/releases. I should probably do that. FWIW, you can buy the boards directly from the fab I use. Cost is about $32.50/ea plus ~$15 setup/shipping. Lead time is about 3wks. Here's a link to their site with the details: http://www.batchpcb.com/product_info.php?products_id=3D19296&check=3D609ea2= 9581046016e0079ea8cd47a059 (BTW - I don't get anything out of this except a warm glow of achievement) Let me know if you have questions about it. Email addr is on my webpage. EricArticle: 143284
nobody <cydrollinger@gmail.com> wrote:
>I like the site and the board, nice work! what is your intention for
>the board looks like everything is available for another to reproduce
>it. I dont get it whats the deal with only two layers, four is only
>two more?
When using really cheap pcb makers like makepcb.com a 4 layer board is
twice as expensive as a 2 layer board. Besides, a 4 layer board isn't
a requirement. I recenty did an FPGA design on a 2 layer board. Used
the bottom layer as a ground plane and put 2 rings and a plane
underneath the FPGA on the top layer. And ofcourse a size 0402
decoupling capacitor on each power supply pin.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 143285We have an Altera variant of our existing X1 PCIe core coming. At the moment I don't have an exact timescale as we have yet to build the first target development board that will be used to test this version. If it's not an immediate need then I will be happy to take this offline for further discussion on what need and what we can do. John Adair Enterpoint Ltd. - Home of Drigmorn3. The Spartan-6 Starter Board. On 29 Sep, 08:24, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote: > ..using Altera Stratix3 and TI's XIO1011B PHY. > > Altera/PLDA's core is too expensive to use with a yearly fee. > Axcon.dk have a nicer price, but I want to look for even better. > > A one off cost with available source code is preferred.Article: 143286
Cyrille_ wrote: > Can we program a bitstream in the Daughter Board Spartan 3 of the Altium > nanoboard with Xilinx impact instead of Altium Designer ? > If yes, which JTAG must be used with which connectors ? Use a flat ribbon cable to connect the NanoBoard to a printer port. It will look like a parallel cable III to the PC. Then you can use iMPACT to program the Daughter Board. The "system JTAG" connector is intended for reprogramming the FPGA on the main board, not the Daughter Board. -Alex.Article: 143287
On Sep 29, 2:00=A0pm, n...@puntnl.niks (Nico Coesel) wrote: > I recenty did an FPGA design on a 2 layer board. Used > the bottom layer as a ground plane and put 2 rings and a plane > underneath the FPGA on the top layer. And of course a size 0402 > decoupling capacitor on each power supply pin. That's similar to what I did: on the backside I had ground plane plus a 'snail-shell' of 3 concentric supply traces with vias through to the top where the VQ100 package sits. I used 0603 caps on every supply pin - some on the back, some on the front. Didn't have any supply problems. FWIW - I'm impressed that you used 0402 parts. I haven't tried to handle parts that small yet, but I'm getting pretty good at the 0603s. EricArticle: 143288
Hi all, I wonder if I can asume that burst operations on the PLB always start with an address that is a multiple of the datawidth of the bus? I searched the PLB documentation hi and low but could not find any information. TIA MarkusArticle: 143289
Hi Morten, I'd consider the Lattice core to be one of the most cost effective solutions. It's targetted at their ECP2M / ECP3 FPGA series or hard wired in their SCM series, Their licensing is very friendly towards sensitive budgets and most important of all of course, the core works. If your are just doing a prototype, it has the advantage that you can test as long as you like without a license. It stops working after 5 to 9 hours (random time out) but can be restarted immediately. Cost is once off (as far as I know, somewhere below ¤ 1K, but better ask a Lattice disti for real figures). You get 'obfuscated verilog' which cannot really be modified by the user. Their configure tool should be good enough though for setting it up the way you need it.Article: 143290
On Sep 29, 2:15=A0am, Bert_Paris <do_not_s...@me.com> wrote: > Hello all, > > I was wondering about the current status of IP protection for Xilinx > targets, and in general. > > * I guess ISE version 11 is going to provide solutions based on Flexlm > (with _timed_ licenses, floating or non floating, single family or > multi-family, with or without bitstream generation, with or without > simulation netlist generation, etc). > But is this available now ? > What about Webpack users ? (even v11) ? > > * What was/is available pre-11 ? > =A0- I know there is a solution for Synplify users > =A0- What for XST users ? > Some users seem reluctant to switch to v11. FlexLM is to protect the _tools_, not your particular IP. -a-Article: 143291
On Sep 29, 10:02=A0am, "Antti.Luk...@googlemail.com" <antti.luk...@googlemail.com> wrote: > On Sep 29, 1:47=A0pm, Uwe Bonnes <b...@elektron.ikp.physik.tu- > > > > > > darmstadt.de> wrote: > > Hello, > > > in quest for the HDL source files for the Spartan 6 SP601 Demo board an= d > > application, all I find ishttp://forums.xilinx.com/xlnx/board/message?b= oard.id=3DSpartan&thread.i... > > > > BTW, the design files are 'Coming Soon'.... > > > Some zip files are available at > > >http://www.xilinx.com/products/boards/sp601/reference_designs.htm > > > but they contain very few .v files. > > > This seems not enough to rebuild (and later adapt) the Ethernet/DSP > > application delivered with the board. Even not to bebuild the build-in = self > > test... > > > Any news about those HDL files? > > > Thanks > > -- > > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-d= armstadt.de > > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- > > hm i guess you did mean rdf0003.zip > Xilinx is bullshitting again, i would say, there is documentation how > to use the BSRD > BIT file, but no source code. > > to Xilinx: NO ONE who is buying SP601 or any other Xilinx board is > interested to > check out if Xilinx supplied BIT files work or not. > Xilinx has todo in house testing, clients can expect it has done, so > there is no > need the customers verify that using the BIT files. > > the customers NEED the reference desing SOURCE files, if those are > not available, may as well take the SP601 and try its flying > capabilities. > > probably its just a small delay, but hey the boards are out, so should > be refernece designs as well? > > Antti- Hide quoted text - > > - Show quoted text - These files should have been posted online shortly after the release of 11.3. I will look into this and get these up there. Ed McGettigan -- Xilinx Inc.Article: 143292
Hi everyone, I am a master student and this is my first post in this group. My research group is looking for a multicore embedded platform for deploying an in-house developed computer vision algorithm. I've checked some available development boards and now still weigh the ideas in my mind. One solution that interests me is 'synthesizable' processor cores on a FPGA chip, where I can parallelize the data processing on different cores. As far as I know, this solution is based on 'synthesizable' soft-cores, e.g. MicroBlaze, Nios or ARM Cortex-M1 etc. But I've seen one design article (carried out at NXP, the Netherlands) that claims they have implemented two ARM926EJ-S processors on a Xilinx Virtex 4 FPGA chip. I am wondering what technologies enable this implementation. My current knowledge only reaches the level of HDL-based hardware design on FPGAs (and some higher abstraction levels concerning software), but I am not very familiar with the 'macrocells', 'hard core IP' and digital ASIC design. I see some Virtex 4 products come with embedded hard PowerPC blocks, but I have not seen ARM...So I would like to ask you experienced scientists these questions: 1. How to implement one or more such ARM926EJ-S cores on a FPGA chip (detailed information on the NXP design article is not available)? I need some key words in this field and better with some recommended design articles. 2. How to interpret the word 'synthesizable' with respect to soft- cores and macrocells, respectively? 3. If someone has experiences on multicore parallel processing development, I would be grateful if you can suggest some nice development platforms (real-time performance is our top concern). Probably I need to make a new post later describing the requirements=85 Thanks very much for your attention! LucienArticle: 143293
The idea of obsolete has come up a couple of times in this discussion and I would like to take a minute to address it. Being a single engineer in an office somewhere I do not have much time to redesign, therefore one design to fit a multitude of applications. My applications are growing with the times and speed is key, a single bit stream ripping through copper at an increasing bandwidth, even though a GT may be pushing several gigs it requires 10s of gigs to support the rising edge of the digital signal. It has been said that the chip is outdated the board design was not meant specifically for the chip but for upcoming chips and the gigabit tranciever resources that are coming at a decreasing price. The chip may be obsolete but my four layer board design is not and will support a bga chip and GT resources. There is a reason for xilinx application notes such as xapp623 and xapp489 get it done once and be get it done right. I am not saying that anybodies project is wrong but there is a reason for four and more layers, it may not be for hobbyist but again I am not a hobbyist. respectfully Cy DrollingerArticle: 143294
emeb <ebrombaugh@gmail.com> wrote:
>On Sep 29, 2:00=A0pm, n...@puntnl.niks (Nico Coesel) wrote:
>> I recenty did an FPGA design on a 2 layer board. Used
>> the bottom layer as a ground plane and put 2 rings and a plane
>> underneath the FPGA on the top layer. And of course a size 0402
>> decoupling capacitor on each power supply pin.
>
>That's similar to what I did: on the backside I had ground plane plus
>a 'snail-shell' of 3 concentric supply traces with vias through to the
>top where the VQ100 package sits. I used 0603 caps on every supply pin
>- some on the back, some on the front. Didn't have any supply
>problems.
>
>FWIW - I'm impressed that you used 0402 parts. I haven't tried to
>handle parts that small yet, but I'm getting pretty good at the 0603s.
We had the board (18" x 8") assembled. But it is possible to mount
0402 parts by hand. It just takes some getting used to like handling
0603 parts once did. You'll need a magnifier for inspection though.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 143295Can anyone recommend any good USB 2.0 IP block vendors? We're looking to implement a virtual COM port on an Altera Cyclone III part with NIOS. The maximum target data rate is 500K bytes/sec device-to-host on the CDC bulk endpoint. So far we have identified potential candidates: Vreelin and SLS. Thanks, John Speth.Article: 143296
On Sep 30, 7:02=A0pm, nobody <cydrollin...@gmail.com> wrote: > The idea of obsolete has come up a couple of times in this discussion > and I would like to take a minute to address it. Being a single > engineer in an office somewhere I do not have much time to redesign, > therefore one design to fit a multitude of applications. My > applications are growing with the times and speed is key, a single bit > stream ripping through copper at an increasing bandwidth, even though > a GT may be pushing several gigs it requires 10s of gigs to support > the rising edge of the digital signal. It has been said that the chip > is outdated the board design was not meant specifically for the chip > but for upcoming chips and the gigabit tranciever resources that are > coming at a decreasing price. The chip may be obsolete but my four > layer board design is not and will support a bga chip and GT > resources. There is a reason for xilinx application notes such as > xapp623 and xapp489 get it done once and be get it done right. I am > not saying that anybodies project is wrong but there is a reason for > four and more layers, it may not be for hobbyist but again I am not a > hobbyist. > > respectfully > > Cy Drollinger Cy.. do whatever you like.. :) 4 layers is too little actually.. 6 to 10 is more likely layer count for "real boards" just i got the impression you hoped that lots of hobby open-source people would build your 4-layer board using your gerber files. I do not think that will be case.. that the point i was trying to make. AnttiArticle: 143297
On Sep 30, 7:34=A0pm, "John Speth" <johnsp...@yahoo.com> wrote: > Can anyone recommend any good USB 2.0 IP block vendors? > > We're looking to implement a virtual COM port on an Altera Cyclone III pa= rt > with NIOS. =A0The maximum target data rate is 500K bytes/sec device-to-ho= st on > the CDC bulk endpoint. > > So far we have identified potential candidates: Vreelin and SLS. > > Thanks, John Speth. does CDC allow 500K, you sure? most CDC compliant uarts tend to have poor performance AnttiArticle: 143298
Antti, You seem to need to slam my stuff as if it is incorrect, that's a difference between you and I. My project as it stands is what it is and suits my purpose, however others may find use of such a project and am trying to make it available. Other boards and projects mentioned on this forum are what they are and suit their purpose. But when an individual makes remarks about obsolete, not useful, not necessary and the like explanation is necessary. As engineers we are to take the body of knowledge we have been allotted and use it, break it, expand it and make a contribution. If younger engineers read our comments for their enhancement they should be unbiased and factual as possible. If one were to read over these post they might think that there is no need for a four layer board and as you commented that is just not true. I take offense with your comment about a "real board" needing 6 - 10 layers, well, taken in jest, nope, not funny. Let us try and keep our communication at as high technical level as possible. My points about this post's origination: 1. I have completed a project that is affordable and can be built by a hobbyist. 2. Is there any need for an open source project with these mentioned capabilities? I appreciate all the comments on this post and has been very educational. Cy DrollingerArticle: 143299
but no cake ;) anywhy, september 2009 is released http://groups.google.com/group/antti-brain/files?hl=en in time, this time. Antti
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