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On Oct 17, 3:11=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > rickman <gnu...@gmail.com> wrote: > > (snip, then I wrote) > > >> Which seems simpler and more natural: ? > >> ? ? ? ? ? [8*n,8*n+7] ? ?or ? ?[31-8*n,24-8*n] > >> I do know that it took me longer to write the second one and > >> to verify that it did what I wanted it to do. ? > >> Or are you asking about the preference of big-endian for > >> processor design? > > > I don't know what the above equations are for. =A0I have never used > > either forms for anything that I can recall. > > That is the verilog from. =A0Most of the time I can read VHDL and > get the right idea, but I have never written it. =A0(I did some > VHDL to verilog conversions that worked, never the other way.) The verilog form for what? I have never used a calculation like that. What is n? Why are you performing this calculation? What is the context. > > I address bits in words all the time in VHDL. =A0I often use notation > > like (foo'high-bar'high downto 0) which gives the lsbs of foo where > > bar is a shorter length than foo. =A0Or conversely (foo'high downto > > bar'high) for the msbs in foo that are wider than bar. =A0I have never > > used any notation like you have shown. > > OK, > > =A0 =A0 =A0 =A0 (8*n upto 8*n+7) =A0 or =A0(31-8*n downto 24-8*n) > > I believe in some cases verilog can do that with a variable n, > otherwise it can defintely do it with a constant n. =A0Also, note > that the one on the right depends on knowing the width of the > word, while the one on the left does not. Like I said above, I have no idea why you are using a complicated calculation to specify the bit of a word. It is extremely seldom that I need to select a bit range based on a byte address the way you have shown. In fact, I can't remember ever doing that. Ignoring that, I don't see this one calculation as being a driving reason to choose a numbering scheme for a bus. It seems to me to be infinitely more useful to have the index correspond to the weight of each bit to facilitate the calculation of the values in this signal. RickArticle: 143601
rickman <gnuarm@gmail.com> wrote: (snip, then I wrote) >> That is the verilog from. ?Most of the time I can read VHDL and >> get the right idea, but I have never written it. ?(I did some >> VHDL to verilog conversions that worked, never the other way.) > The verilog form for what? I have never used a calculation like > that. What is n? Why are you performing this calculation? What is > the context. (snip) >> ? ? ? ? (8*n upto 8*n+7) ? or ?(31-8*n downto 24-8*n) >> I believe in some cases verilog can do that with a variable n, >> otherwise it can defintely do it with a constant n. ?Also, note >> that the one on the right depends on knowing the width of the >> word, while the one on the left does not. > Like I said above, I have no idea why you are using a complicated > calculation to specify the bit of a word. It is extremely seldom that > I need to select a bit range based on a byte address the way you have > shown. In fact, I can't remember ever doing that. Select a byte from a word. I haven't looked at the internals of microblaze at all, but it isn't unusual to address bytes in a 32 bit word. assign n=x[0:1]; assign byte=word[8*n,8*n+7]; > Ignoring that, I don't see this one calculation as being a driving > reason to choose a numbering scheme for a bus. It seems to me to be > infinitely more useful to have the index correspond to the weight of > each bit to facilitate the calculation of the values in this signal. I would expect selecting bytes from words to happen much more often in processor hardware than calculating the value of bits. Sometimes software has to compute the value of bits, but even that is pretty rare. As I said before, you might make the arguement for little-endian over big-endian, but when designing a big-endian processor, a decision that someone else might have made for you, you do it in the most appropriate way. -- glenArticle: 143602
On Oct 17, 7:01=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
> rickman <gnu...@gmail.com> wrote:
>
> =A0(snip, then I wrote)
>
> >> That is the verilog from. ?Most of the time I can read VHDL and
> >> get the right idea, but I have never written it. ?(I did some
> >> VHDL to verilog conversions that worked, never the other way.)
> > The verilog form for what? =A0I have never used a calculation like
> > that. =A0What is n? =A0Why are you performing this calculation? =A0What=
is
> > the context.
>
> (snip)
>
> >> ? ? ? ? (8*n upto 8*n+7) ? or ?(31-8*n downto 24-8*n)
> >> I believe in some cases verilog can do that with a variable n,
> >> otherwise it can defintely do it with a constant n. ?Also, note
> >> that the one on the right depends on knowing the width of the
> >> word, while the one on the left does not.
> > Like I said above, I have no idea why you are using a complicated
> > calculation to specify the bit of a word. =A0It is extremely seldom tha=
t
> > I need to select a bit range based on a byte address the way you have
> > shown. =A0In fact, I can't remember ever doing that.
>
> Select a byte from a word. =A0I haven't looked at the internals
> of microblaze at all, but it isn't unusual to address bytes in
> a 32 bit word.
>
> =A0 =A0assign n=3Dx[0:1];
> =A0 =A0assign byte=3Dword[8*n,8*n+7];
>
> > Ignoring that, I don't see this one calculation as being a driving
> > reason to choose a numbering scheme for a bus. =A0It seems to me to be
> > infinitely more useful to have the index correspond to the weight of
> > each bit to facilitate the calculation of the values in this signal.
>
> I would expect selecting bytes from words to happen much more
> often in processor hardware than calculating the value of bits.
>
> Sometimes software has to compute the value of bits, but even
> that is pretty rare. =A0
>
> As I said before, you might make the arguement for little-endian
> over big-endian, but when designing a big-endian processor, a
> decision that someone else might have made for you, you do it
> in the most appropriate way.
I don't care about the endianness. I just have never needed to use
that one calculation before. I would code a mux the way I code a mux
for arbitrary inputs.
with x select
byte <=3D word(31 downto 24) when =9300=94,
word(23 downto 16) when =9301=94,
word(15 downto 8) when =9310=94,
word( 7 downto 0) when =9311=94;
It may be more verbose, but I think it is more clear than any
calculation, especially since it is the same form as used elsewhere.
I recognize instantly that this is a 4 input mux. But then I code a
hardware description so that I have some idea of what hardware will be
produced. I know a lot of people like to treat HDLs like software
where they depend on the tools to optimize the design.
The calculations I showed had to do with assigning values between
buses of different sizes which is about the only place I can think to
use calculations for array indexes. But then I'm sure there are
others I just am not thinking of.
Like I said, short of some special reason, I would always use N downto
0 notation because it indicates the bit weights. What is the value of
bit 4 and 7 set? In this notation I know it is 144 without even
knowing the width of the word.
Rick
Article: 143603In article <hbc3f1$llh$1@naig.caltech.edu>, glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote: > Antti <antti.lukats@googlemail.com> wrote: > > what board you mean? > > digilent s3e board was available with s3e-1600 what is the > > largest s3e for a while i think they stopped selling it > > As far as I know, it comes only with the S3E-500. As of right now, the s3e-1600 version of the board is listed as 'Shipping immediately' <http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,793&Prod=S3E1600> -- David M. Palmer dmpalmer@email.com (formerly @clark.net, @ematic.com)Article: 143604
The trenz boards only offers 55 IO pins for the large FPGA if I read it right. And they're German so shipping might be rather expensive to US. The Digilent board has the same 100 pin IO limit as the original S3E boards, which I have 3 of. I don't know if the 1600 S3E board has the same huge signal stubs on the FX2 connector as the original S3E starter board but those stubs make higher speeds difficult. What I would like is at least 200 IO signals that can run at over 150Mhz, so fairly decent & direct signalling. I don't really want all of the extras, I'll put those on the daughter cards. Also at least 5A power supply. Any other possibilities ? "Antti" <antti.lukats@googlemail.com> wrote in message news:e5d05a28-2194-449b-a679-054519a7745a@x37g2000yqj.googlegroups.com... On Oct 17, 8:21 am, "nwreader" <no...@home.com> wrote: > Is there any interest in a group buy & design of a Xilinx fpga board ? > I would like a fairly large Spartan FPGA + lots of IO expansion + low cost > $200 - $250 usd. > The exisiting FPGA boards on the market seems either too expensive or > small > FPGA or too little > expansion potential. > > The idea is to get a high capacity & low cost expandable board via a group > buy to save on the > PCB + assembly. Probably only for US participants. hi S3ADSP board from trenz may actually fit your requirements those modules are not yet in their online shop, but you can see high res photos of the modules in Antti-Brain august 2008 issue first units are actually sold, and the modules should be very soon be available for general buy also, the main goal for that board was low cost lots of resources, thats also the reason for low cost connectors being used - 1.27mm headers not the hirose as other modules from trenz a baseboard will also be available with breakout of the module to 4 x 2x20 100mil headers AnttiArticle: 143605
David M. Palmer <dmpalmer@email.com> wrote: (snip, I wrote) >> As far as I know, it comes only with the S3E-500. > As of right now, the s3e-1600 version of the board is listed as > 'Shipping immediately' > <http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,793&Prod=S3E1600> I suppose I should have looked again before posting. It was some months ago that I bought the S3E500 board. That should be big enough for good sized designs. -- glenArticle: 143606
On Oct 18, 8:33=A0am, "nwreader" <no...@home.com> wrote: > The trenz boards only offers 55 IO pins for the large FPGA if I read it > right. And they're German so shipping might be rather > expensive to US. =A0The Digilent board has the same 100 pin IO limit as t= he > original S3E boards, which I > have 3 of. =A0I don't know if the 1600 S3E board has the same huge signal > stubs on the FX2 connector as the > original S3E starter board but those stubs make higher speeds difficult. > > What I would like is at least 200 IO signals that can run at over 150Mhz,= so > fairly decent & direct signalling. I don't really > want all of the extras, I'll put those on the daughter cards. Also at lea= st > 5A power supply. if you want a module with 200 high speed IOs this means the module shoud have connectors with total amount of pins about 400 (for power and gnd) that kind of connectors exist, but i bet you have hard time find such a module for low price AnttiArticle: 143607
On Sat, 17 Oct 2009 22:33:54 -0700, "nwreader" <noone@home.com> wrote: >The trenz boards only offers 55 IO pins for the large FPGA if I read it >right. And they're German so shipping might be rather >expensive to US. The Digilent board has the same 100 pin IO limit as the >original S3E boards, which I >have 3 of. I don't know if the 1600 S3E board has the same huge signal >stubs on the FX2 connector as the >original S3E starter board but those stubs make higher speeds difficult. > >What I would like is at least 200 IO signals that can run at over 150Mhz, so >fairly decent & direct signalling. I don't really >want all of the extras, I'll put those on the daughter cards. Also at least >5A power supply. > >Any other possibilities ? Enterpoint may have something approaching your needs. http://www.enterpoint.co.uk/boardproducts.html A PC104 card with 115 I/O on 0.1" headers, plus the PC104 connector (I couldn't determine if they are shared; ask Enterpoint. http://www.enterpoint.co.uk/moelbryn/hollybush1.html A PGA replacement with 219 I/O pins. http://www.enterpoint.co.uk/moelbryn/darnaw1.html - BrianArticle: 143608
Hello,
I'm simulating a FSM written in Verilog using Xilinx ISim. Is there any
possibility to see in waveform the FSM state names instead of just
numbers, which I have to manually decode to state names?
Regards,
Misiu
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From: Arlet <usenet+5@ladybug.xs4all.nl>
Subject: Re: Xilinx ISim and FSM states names
Date: Sun, 18 Oct 2009 14:02:40 +0200
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On Sun, 18 Oct 2009 13:13:39 +0200, Misiu wrote:
> Hello,
>
> I'm simulating a FSM written in Verilog using Xilinx ISim. Is there any
> possibility to see in waveform the FSM state names instead of just
> numbers, which I have to manually decode to state names?
I use a different simulator, but I usually do something like this:
`ifdef SIM
/*
* easy to read names in simulator output
*/
reg [8*6-1:0] statename;
always @*
case( state )
DECODE: statename <= "DECODE";
READ: statename <= "READ";
WRITE: statename <= "WRITE";
endcase
`endif
Article: 143609
> Just because FPGAs have to cobble together logic to create a latch
> (and cause potential timing issues in doing so)
This is not true - or at least, it's not true of all FPGAs. The
Spartan and Virtex lines, even in their latest incarnations (V6/S6),
allow the memory elements in every slice to be configured either as D-
type flip-flops or as transparent latches. I don't know how many
customers use this feature, but I'm guessing there are some key users
who do (military accounts with big legacy circuits that would be
expensive to redesign and re-certify - just a guess). Otherwise, the
feature wouldn't still be there.
When I first learned what a flip-flop was, the most common design was
to build it out of two latches in a master-slave arrangement.
Obviously, that's not true of the FFs in today's ICs. But once upon a
time, it would seem that there was a serious area advantage to be had
from using latches instead of FFs.
Cheers,
-Ben-
Article: 143610On Oct 18, 11:37=A0am, Ben Jones <benj...@gmail.com> wrote: > > Just because FPGAs have to cobble together logic to create a latch > > (and cause potential timing issues in doing so) > > This is not true - or at least, it's not true of all FPGAs. Correct, I should've said "may have to cobble..." > Spartan and Virtex lines, even in their latest incarnations (V6/S6), > allow the memory elements in every slice to be configured either as D- > type flip-flops or as transparent latches. Making use of 'hard' latches that may be available in a given target is OK as long as one also verifies that the hard latches actually get used in each and every instance. A latch designed by the silicon guys is not the same as one that has to be put together from logic arrays (CPLDs) or lookup tables (FPGAs). If one chooses the route of wanting to make use of hard latches that are available, then one still has to make sure that the synthesized output does indeed end up using the hard latch and not implement the latch in logic because the tool didn't quite spot it. I don't know if the tools support reporting of latches that have been implemented the two different ways...after all, a 'latch' is really anything that has a combinatorial logic path that loops back on itself, not just the canonical expression Q <=3D D when (CE=3D'1'); Kevin JenningsArticle: 143611
1. It doesn't have to be 1 connector. 2. Doesn't the typical cheap DDR2 dimm module plug into a 240 pin connector capable of > 150Mhz speed ? "Antti" <antti.lukats@googlemail.com> wrote in message news:bbc6176e-176e-48f1-b300-0387ca2b365e@j4g2000yqa.googlegroups.com... On Oct 18, 8:33 am, "nwreader" <no...@home.com> wrote: > The trenz boards only offers 55 IO pins for the large FPGA if I read it > right. And they're German so shipping might be rather > expensive to US. The Digilent board has the same 100 pin IO limit as the > original S3E boards, which I > have 3 of. I don't know if the 1600 S3E board has the same huge signal > stubs on the FX2 connector as the > original S3E starter board but those stubs make higher speeds difficult. > > What I would like is at least 200 IO signals that can run at over 150Mhz, > so > fairly decent & direct signalling. I don't really > want all of the extras, I'll put those on the daughter cards. Also at > least > 5A power supply. if you want a module with 200 high speed IOs this means the module shoud have connectors with total amount of pins about 400 (for power and gnd) that kind of connectors exist, but i bet you have hard time find such a module for low price AnttiArticle: 143612
Jon, try this: http://www.fpga4fun.com/ Giuseppe MarulloArticle: 143613
On 15 Okt., 10:30, Fabian Schuh <use...@xeroc.org> wrote: > In more courious tests i found out, that some FSMs enter two states at th= e same > time: > =A0 (fsm_state =3D idle & fsm_state=3Derror_frame) =3D=3D true This is only possible, if your statemachine uses one-hot encoding. In that case I would use some logic that recovers from illegal (unused) states. In a later post you ask, if a when-others statement in VHDL is sufficient to obtain this function. No that is unfortunately not the case for some synthesis tools. Some tools inferring one-hot-fsm allow to select self recovering one-hot- fsm. For other tools you need to figure out how to avoid this. For some fsm it will be best practice to start cycling trough all unused states before entering the usual idle state. This will force the synthesis tool to cover every state and includes a dedicated way to recover from "unused" states. bye ThomasArticle: 143614
The dreaded License expiration has bitten me in the butt again. I don't recall if I had this exact same problem before, but I am pretty sure I was told at one point that my tools would not expire when maintenance ran out, because that is what is stuck in my head. However, that is not the case. My copy of ispLever from Lattice will not run compile or simulate because neither of these tools will run due to the license expiring. Maybe the deal is that I have to update the license file periodically, but I just did that earlier this year. The real problem is that I can't get anyone to talk straight with me about this. I had an email exchange with licensing the last time I updated the license and they never answered my questions about this. So now I am trying to use the Xilinx Webpack to allow me to continue working until I can get a new license file, but it won't run either. I think that it somehow is using networking to communicate between processes and it won't go through the firewall! Talk about making simple things difficult! This is the error message I get. IPC connection failed port=58676 hostname=localhost I am using Sophos for AVS and firewall. Anyone know what has to be turned on to allow ISE to talk to the simulator? RickArticle: 143615
Nice articles from Linux Journal: http://www.linuxjournal.com/article/10330 Xilinx FPGA Design Tools for Linux: http://www.linuxjournal.com/article/6857 -- Torfinn Ingolfsen, NorwayArticle: 143616
On Sun, 20 Sep 2009 21:48:41 -0500, "mlin" <maddie.gun@gmail.com> wrote: |>On Thu, 17 Sep 2009 19:57:49 -0500 |>"mlin" <maddie.gun@gmail.com> wrote: |> |>> Hi, |>> |>> I am using MIG v2.1 that targets spartan 3 starter kit. I want to |>> know, if sram on the starter board could be accessed using MIG and if |>> the MIG is used for accessing memory development boards? |>> |>> Thanks in advance! |>> |>> |> |>MIG is for talking to DRAMs, which are complicated. SRAM is |>easy: there are data lines and address lines and it just does what you |>ask it to. The interface is trivial enough to implement that I'd be |>surprised if anyone has a core to do it; it would mostly just be wires. |> |>-- |>Rob Gaddi, Highland Technology |>Email address is currently out of order |> | |Thank you so much. Could you please clear my other doubt? How do I send |address and data to the SRAM? | |Thanks. | |--------------------------------------- |This message was sent using the comp.arch.fpga web interface on |http://www.FPGARelated.com |==================== You gotta be kidding I hope? If not, then is the state of college students is getting poorer by the year? jamesArticle: 143617
On Sat, 17 Oct 2009 09:40:49 +0000 (UTC), glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote: |Antti <antti.lukats@googlemail.com> wrote: |> On Oct 17, 11:56?am, I wrote: |>> nwreader <no...@home.com> wrote: |>> > Is there any interest in a group buy & design of a Xilinx fpga board ? |>> > I would like a fairly large Spartan FPGA + lots of |>> > IO expansion + low cost $200 - $250 usd. | |>> > The exisiting FPGA boards on the market seems either too |>> > expensive or small FPGA or too little expansion potential. | |>> One that I have wondered about for a while: | |>> Can the Digilent S3E board take a larger FPGA than the one |>> it comes with? ?That wouldn't require a new board design, though |>> it does require unsoldering and soldering. | |> what board you mean? |> digilent s3e board was available with s3e-1600 what is the |> largest s3e for a while i think they stopped selling it | |As far as I know, it comes only with the S3E-500. | |Otherwise, it would seem a fine board for the OP. | |-- glen |=============== Digilent still has the S3E-1600 development board for $225 listed on their webpage and available to ship. The Nexsys2 board comes with either the XC3S500E or XC3S1200E for $40 dollars more than teh base price of $129. jamesArticle: 143618
Regarding Lattice ispLever, this is a statment I got from them a while back: "The Warranty maintenance expiration and Third party OEM License feature expiration are separate functions. Contractually we license the third party tools annually from the latest license generation. You own the license and we renew the features at any time regardless of the Warranty maintenance status, for the life of the product. The Warranty maintenance allows for distribution of new versions of the tool suite as they are released." I guess that means if you renew maintenance you always get the latest, if you don't, they lock <ou into the last maintained version of the OEM tools (e.g. Synplify) rickman schrieb: > The dreaded License expiration has bitten me in the butt again. I > don't recall if I had this exact same problem before, but I am pretty > sure I was told at one point that my tools would not expire when > maintenance ran out, because that is what is stuck in my head. > However, that is not the case. My copy of ispLever from Lattice will > not run compile or simulate because neither of these tools will run > due to the license expiring. Maybe the deal is that I have to update > the license file periodically, but I just did that earlier this > year. > > The real problem is that I can't get anyone to talk straight with me > about this. I had an email exchange with licensing the last time I > updated the license and they never answered my questions about this. > > So now I am trying to use the Xilinx Webpack to allow me to continue > working until I can get a new license file, but it won't run either. > I think that it somehow is using networking to communicate between > processes and it won't go through the firewall! Talk about making > simple things difficult! This is the error message I get. > > IPC connection failed port=58676 hostname=localhost > > I am using Sophos for AVS and firewall. Anyone know what has to be > turned on to allow ISE to talk to the simulator? > > RickArticle: 143619
james <bubba@bud.u> wrote: (big snip) > Digilent still has the S3E-1600 development board for $225 listed on > their webpage and available to ship. The Nexsys2 board comes with > either the XC3S500E or XC3S1200E for $40 dollars more than teh base > price of $129. Yes, I just saw that last night. They didn't have that when I bought my S3E with the -500 on it, but it looked like there were sample designs to use with the -1600. The -500 should be good enough for many designs, but I had some ideas for bigger ones. One was to implement something like the Sun Sparcstation1. Well, Sun has available the HDL code for newer Sparc processors, probably too big for even the -1600. I had asked someone at Sun about the older SPARC versions, which might fit on the 1600. (Hopefully also including some support circuitry.) Or, if you have BGA soldering tools, then just replace one with the other... -- glenArticle: 143620
On Oct 16, 6:36=A0am, Fabian Schuh <use...@xeroc.org> wrote: > All my FSM do have the > =A0 =A0 =A0 =A0 ---------------------- > =A0 =A0 =A0 =A0 when others=3D> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 state <=3D idle; > =A0 =A0 =A0 =A0 ---------------------- > Is this enough? I thought so. > That's tool dependent. Check for some synthesis option that says something about implementing safe state machines. It can add additional logic to use that option. This would only be a band-aid to fix a symptom, not a fix to the problem. > Just started implementing a wait counter to reset the FSM for some clockc= lycles > before starting the FSMs. Gonna test, if it helps. > My guess is that it will fix the problem since it sounds like you're not resetting the FSM when it comes alive. Unless your system clock is synchronized with the end of configuration, you'll have no way of guaranteeing that you meet setup time requirements on the very first clock cycle after coming out of configuration. I also wouldn't implement the 'wait counter' as a counter if it is in the logic that is getting reconfigured, since you can't guarantee meeting setup requirements on that counter when configuration ends either. The way to do this is with a shift register. You can still violate setup time on the input to the first stage but it will propogate through. Your newly configured logic can be considered alive and well by the stuff that has not been reconfigured once you see two consecutive 'not resets' coming out of the shift register (consider using a shift register of 3-4 stages or so). That way the new logic gets reset properly, and the other logic knows when things are really alive. The shift register reset after configuration is not unique to partial configuration, it should be a part of every design. > Is there some good way to get an FSM into a defined state, if it runs int= o an > illegal one? > The illegal state is just a symptom of the problem. The problem is (most likely) not meeting timing requirements (the other possibility is inadequate power to the chip). The correct solution fixes the problem, not the symptom. Kevin JenningsArticle: 143621
On Oct 19, 12:55=A0am, Torfinn Ingolfsen <ti...@start.no> wrote: > Nice articles from Linux Journal:http://www.linuxjournal.com/article/1033= 0 > > Xilinx FPGA Design Tools for Linux:http://www.linuxjournal.com/article/68= 57 > > -- > Torfinn Ingolfsen, > Norway the first article requires PAID subscription the second article just talks about ISE, i see nothong so linux related info, all the same applies for windows too AnttiArticle: 143622
KJ <kkjennings@sbcglobal.net> schrieb:
> That's tool dependent. Check for some synthesis option that says
> something about implementing safe state machines. It can add
> additional logic to use that option. This would only be a band-aid to
> fix a symptom, not a fix to the problem.
Thought so.
> My guess is that it will fix the problem since it sounds like you're
> not resetting the FSM when it comes alive. Unless your system clock
> is synchronized with the end of configuration, you'll have no way of
> guaranteeing that you meet setup time requirements on the very first
> clock cycle after coming out of configuration. I also wouldn't
> implement the 'wait counter' as a counter if it is in the logic that
> is getting reconfigured, since you can't guarantee meeting setup
> requirements on that counter when configuration ends either. The way
> to do this is with a shift register. You can still violate setup time
> on the input to the first stage but it will propogate through. Your
> newly configured logic can be considered alive and well by the stuff
> that has not been reconfigured once you see two consecutive 'not
> resets' coming out of the shift register (consider using a shift
> register of 3-4 stages or so). That way the new logic gets reset
> properly, and the other logic knows when things are really alive.
Gonna try that.
> The illegal state is just a symptom of the problem. The problem is
> (most likely) not meeting timing requirements (the other possibility
> is inadequate power to the chip). The correct solution fixes the
> problem, not the symptom.
Yep. I know the timing issues. Unfortunatelly, there's atm no way to solve
them, as parts of the design must run at 200MHz. Anyway the FSMs are clocked
20MHz, and the timing checkes passed.
> Kevin Jennings
--
best regards
-- Fabian Schuh
Article: 143623The Hollybush1 board mentioned by Brian has headers that are not shared and have about 116 on the main header set from memory. The PC104 interface can also be used if not running stand alone giving another 50+ I/O. We have boards like Raggedstone1, MINICAN that have a similar amounts. Generally large pinout devices cost a lot more if you do want to make your own board. Commercial manufacturers like oursleves are also recovering design costs over what is normally a smallish market so I would be surprised if you got this many I/O, with a high quality connector, for such a low price.The chance may well be a board with multiple DIMMs assuming they don't share I/Os between DIMMs. The other aspect that I ddn't see mention of is that the larger devices are not usually covered by the "free" versions of tools so you may want to qualify how big a device you want. John Adair Home of Drigmorn3 - The Spartan-6 Starter Board. On 17 Oct, 06:21, "nwreader" <no...@home.com> wrote: > Is there any interest in a group buy & design of a Xilinx fpga board ? > I would like a fairly large Spartan FPGA + lots of IO expansion + low cost > $200 - $250 usd. > The exisiting FPGA boards on the market seems either too expensive or small > FPGA or too little > expansion potential. > > The idea is to get a high capacity & low cost expandable board via a group > buy to save on the > PCB + assembly. Probably only for US participants.Article: 143624
Antti wrote: > the first article requires PAID subscription Yes, because it is from the current (paper) issue. I guess it will be free when next months paper issue hits a newsstand near you. :-) -- Torfinn Ingolfsen, Norway
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