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Messages from 126125

Article: 126125
Subject: Re: Xilinx Virtex-II Newbie
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Thu, 15 Nov 2007 15:37:47 +1300
Links: << >>  << T >>  << A >>
Andrew Ganger wrote:
> 
>> Are you sure that you need 4 read and 2 write ports? Do you need to
>> assign the data read at the time - at the same clock edge? In that
>> case you could just assign the same data read to multiple signals.
>>
>> How big is your register file? 
> 
> 
> Thanks for your answer Dan, I need a data and instruction RAM with one 
> read/write port each but I would need a register file with 4 read ports
> and 2 write ports. Is such a thing feasable with Virtex II? If not, are
> there any FPGA Boards that would support 4 Read Ports and 2 Write Ports
> Register Files? The register File itself contains 16 registers, each of
> 32bits.And in the worst case it can happen that at the same clock cycle
> I have to read 4 registers and to write back 2 values.

What I described in my other post can do this too. (it would be up to
the user to make sure the writes did not collide ..)
Take 2 dual port memories, and parallel the write ports, on each side,
but separate the read ports. As you always write before read, the info 
in the two is always identical. With a FPGA, done this way, you can
also add 1 cycle register bank-switching for interrupts, or a register 
page scheme, to use larger dual-port memory.

What CPU are you using ?

-jg


Article: 126126
Subject: Xilinx Chipscope Pro in EDK system - ILA:how specify separate signals
From: Andrew FPGA <andrew.newsgroup@gmail.com>
Date: Wed, 14 Nov 2007 19:08:51 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi,
This is an embarrassing question to be asking - how does one attach
signals from the edk design to the chipscope ILA? When I sit down at
my desk to debug with a benchtop logic analyser, the first thing I do
is attach the probes to the pcb - I kinda expected it would be simple
and straightforward with chipscope pro also?

I'm using EDK 9.1i, sp3. I used the debug->debug config menu and
selected an ILA. Its easy to select signals and add them to Trig0. But
if I want the trigger and data capture signals to be different, where
and how do I attach signals in my design to the data capture port on
the ILA?

(I have limited resources remaining on my FPGA and I only need a few
simple signals connected to the trigger input, but I want a wider
selection of signals captured in the trace buffer)

I tried manually editing the ILA component in the .mhs file, by adding
the entry below:

PORT DATA =
EthInterfaceTimestamp_0_rx_dv_falling_edge_r_to_chipscope_ila_0 &
EthInterfaceTimestamp_0_rx_dv_rising_edge_r_to_chipscope_ila_0 &
EthInterfaceTimestamp_0_tx_en_falling_edge_r_to_chipscope_ila_0 &
EthInterfaceTimestamp_0_tx_en_rising_edge_r_to_chipscope_ila_0 &
EthInterfaceTimestamp_0_timestamp_to_chipscope_ila_0

Which caused edk to crash...Is editing the .mhs file ok?

Regards
Andrew



Article: 126127
Subject: Re: FPGA for hobby use
From: Alex Colvin <alexc@TheWorld.com>
Date: Thu, 15 Nov 2007 03:36:21 +0000 (UTC)
Links: << >>  << T >>  << A >>
>Long-term, perhaps we'll expect better graphical tools.  We have
>text-based languages now partly because they are easier to define
>accurately and because they exploit our familiarity with complex text

Experience from software systems is that graphical tools don't scale to 
large systems. The trick is to reduce a complex system to a few components 
that can be glued together with graphical tools.

-- 
	mac the naf

Article: 126128
Subject: Re: Xilinx Virtex-II Newbie
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Thu, 15 Nov 2007 16:38:14 +1300
Links: << >>  << T >>  << A >>
Andrew Ganger wrote:
> 
>> My question should be: do you have instructions that use 4 register
>> operands?
> 
> 
> Yes, I have defined an own ISA. There are instructions that take up to
> 4 src operands and can write up to two results back to the register 
> file. So I need these 4 read ports for some, not all, instructions!

So that's 24 bits of operand, leaves 8 bits of opcode, if 32 bit ?

Which opcodes need to write two results, in one cycle ?

I can think of MUL, DIV, MOD that might write two results,
(but not so much in one cycle)
but the only other instances I could think of would be
extended size opcodes (normally handled reg-paired), and maybe
merge of a MOV.

Source code does not tend to have two writes per expression ?

-jg


Article: 126129
Subject: Re: Xilinx Virtex-II Newbie
From: jhallen@TheWorld.com (Joseph H Allen)
Date: Thu, 15 Nov 2007 04:03:40 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <fhfd7q$r2k$1@aioe.org>,
Andrew Ganger  <Andrew.G@yahoo.co.uk> wrote:

>my Register File should have 4 read ports and two 
>write ports

You have several options besides time multiplexing the existing RAM:

- Implement the RAM using flops instead of RAM.  This may be reasonable if
  you do not have too many registers.  I'm not sure if xst will infer the
  flops, but I would try something like this:

reg [31:0] r[15:0]; // 512 flops, not ram.

always @(posedge clk)
  begin
    if (write_enable_a) r[write_addr_a] <= write_data_a;
    if (write_enable_b) r[write_addr_b] <= write_data_b;
  end

- Use XOR differences.  Each write port writes to a set of RAMs- you want
  two ports, so there will be set A and set B.  Each set of RAMs is made up
  of a bunch of dual-port async read RAMs (Xilinx distributed RAM) in
  parallel.  Within each set, the write side of these dual port RAMs are all
  tied together and use a single address.  The read ports all get their own
  addresses.

  So this is how it works: each read port is created by XORing a read port
  from set A and one from set B.  So lets say write port A wants to write an
  X to location N- it has to write A'[N] <= X ^ B[N] so that on read you will
  have X == (A'[N]) ^ B[N] == (X ^ B[N]) ^ B[N] == X.

  This means that each set needs a read port for the writer of the other
  set, plus a read port for each final read port.  For two write ports and
  four read ports you will need 5 ports in each set: 10 dual-port
  distributed RAMs total per bit.

To simulate a superscalor or VLIW CPU you need many read ports and many
write ports, so any way you do it gets to be very expensive.

-- 
/*  jhallen@world.std.com AB1GO */                        /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

Article: 126130
Subject: Re: FPGA for hobby use
From: jhallen@TheWorld.com (Joseph H Allen)
Date: Thu, 15 Nov 2007 04:15:22 +0000 (UTC)
Links: << >>  << T >>  << A >>
I just want to say that old DOS OrCAD plus old Xilinx "Xblox" ended up being
very quick and very abstract, even if you are instaniating things instead of
synthesizing them.  First, DOS OrCAD is *still* the best schematic editor
(which is just pathetic but true- compare it with Cadance Concept). Second,
Xblox adds the abstraction.  It worked like this- there is for example and
adder component.  A parameter on the adder sets its width.  Wires are used
for busses instead of OrCAD busses, which means to change the width you only
have to mess with the parameters and not a bunch of bus labels.

Also I will point out that ASICs generally use synthesis but high end CPUs
tend to use all hand instantiation (no Verilog case statements allowed). 
This makes hand layout and especially gate-level patches easier.
-- 
/*  jhallen@world.std.com AB1GO */                        /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

Article: 126131
Subject: Re: Xilinx Encrypted bit file
From: Matthieu <m.a.t.t.h.i.e.u.m.i.c.h.o.n@laposte.net>
Date: Thu, 15 Nov 2007 13:52:30 +0900
Links: << >>  << T >>  << A >>
To follow what said Austin, a side-effect caused by the contents of the 
encrypted bit-file locking like noise is that the compression ratio of 
the encrypted bit file will be near 1:1.

Therefore a practical solution regarding the problem of the OP would 
consist in compressing all his BIT files in a single archive and then 
sort the contents of the archive by compression ratio (or compressed size).

This however may not work if bitgen is called with the "Compress" 
parameter...

Article: 126132
Subject: Re: FPGA for hobby use
From: Herbert Kleebauer <klee@unibwm.de>
Date: Thu, 15 Nov 2007 09:40:23 +0100
Links: << >>  << T >>  << A >>
cs_posting@hotmail.com wrote:
> On Nov 14, 9:46 am, Herbert Kleebauer <k...@unibwm.de> wrote:
> 
> > Sadly the same can't be
> > said about the current Xilinx software (schematic editor + simulator),
> > so we will try to stay as long as possible with the X3000 chips and the
> > old Xilinx DOS software (with ViewLogic schematic entry + simulator).
> 
> The real problem is your insistence on using schematic entry for
> things of moderate complexity.
> 
> Learn a hardware description language and your life will be much
> easier.

That's no alternative. At the time of the course, the students know
about logic gates, flip-flops, how to minimize a logic equation and
how to design a simple state machine. And then there are exactly 10 hours
form reading the processor specification till the download of the 
bit stream into the FPGA. This includes the time to get used to the
development software. And most of them will never do any hardware
design later anymore. But this year we will let one group use the new
Xilinx software, so we will see what's happen.

Article: 126133
Subject: Re: FPGA for hobby use
From: Herbert Kleebauer <klee@unibwm.de>
Date: Thu, 15 Nov 2007 09:41:48 +0100
Links: << >>  << T >>  << A >>
Jim Granville wrote:
> Herbert Kleebauer wrote:

> > voltage converters and program flash on board. Sadly the same can't be
> > said about the current Xilinx software (schematic editor + simulator),
> > so we will try to stay as long as possible with the X3000 chips and the
> > old Xilinx DOS software (with ViewLogic schematic entry + simulator).
> 
> So, hundreds of man months of SW effort have seen a nett-step backwards ?
> Can you elaborate on some of the drawbacks, and perhaps Xilinx can fix
> them ?

- I had more crashes with ISI 9.2 in the last few weeks than I have seen 
  in 10 years laboratory course with the old XILINX DOS software

- The essential drawback is the missing back annotation of the simulation
  results into the schematic. This is like debugging software with print
  statements instead of a source code debugger. A few years ago I tested
  an older version (I think it was ISI 2.1) and there at least you could 
  attach probes in the schematic to display the states of signals.
  This also was only a makeshift, but better than nothing.

- To much of the screen is wasted with the different windows. There should
  be a full screen mode for the editor with keyboard commands and no menus 
  at all (only hidden pull down menus). 

- I think the documentation has to be improved. If you have to use Google 
  to find some information, then something is wrong with the documentation.
  Had real problems to find out how to update the bit stream with a new memory
  content using data2mem.exe. This was also because of some very poor error
  messages generated by the software.

- There also could be some improvement in the user interface, but this
  always depends on user preferences. Does Xilinx have a quality feed
  back program where customers are asked for suggestion for improvements?

Article: 126134
Subject: Re: Block-ram FIFO in Xilinx
From: "zlotawy" <paraliczb@NO_SPAM_orange.pl>
Date: Thu, 15 Nov 2007 12:14:24 +0100
Links: << >>  << T >>  << A >>

Uzytkownik "Peter Alfke" <peter@xilinx.com> napisal w wiadomosci 
news:1195079702.949034.33320@e9g2000prf.googlegroups.com...
>A large asynchronous FIFO will always most efficiently be implemented
> in a dual-ported BlockRAM, and have a width of 1, 2, 4, 9, 18, or 36
> bits. If you need a different width, just pad it to the higher value.
> Also Din and Dout have the same width.
> Anything different will get very complicated...

> The main problem in the design of asynchronous (2-clock) FIFOs is the
> reliable generation of the Full and Empty flags at high clock rates.

hmmm... which clock sets flags?

And what if two clocks are the same? Then should I change type of fifo (one 
clock)?

zlotawy 



Article: 126135
Subject: Re: newbie to 16v8
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Thu, 15 Nov 2007 13:04:27 +0000
Links: << >>  << T >>  << A >>
On Wed, 14 Nov 2007 18:31:15 -0800 (PST), Amit <amit.kohan@gmail.com>
wrote:

>On Nov 12, 8:57 am, Ray Andraka <r...@andraka.com> wrote:
>Hi Ray,

>Thank your response. what is your webiste's domain?

I think I'd try www.andraka.com just to see what happened...

- Brian

Article: 126136
Subject: Re: Xilinx Virtex-II Newbie
From: Andreas Ehliar <ehliar-nospam@isy.liu.se>
Date: Thu, 15 Nov 2007 13:15:40 +0000 (UTC)
Links: << >>  << T >>  << A >>
On 2007-11-14, Andrew Ganger <Andrew.G@yahoo.co.uk> wrote:
> I am just reading the XST userguide. There it says that with version 
> 8.1i it is possible to directly specify data with the RAM module or
> load it from an external source. IN addition it says the multiple write 
> ports in the RAM are supported from version 8.1 on. UNfortuantely I just 
> have version 7.1 and I should have a RAM that has 4 read ports and 2 
> write ports? Is that somehow to realise with ISE 7.1 or do I need to 
> upgrade to version 8.1?

Hi, as others have pointed out you can create a register file with
one write port and several read ports quite efficient. Could you constrain
your instruction set so that the instruction that need to write to two
registers is limited to a register pair of even and odd registers?

As in: (R1,R0) = R2*R3 ; Ok R1 odd, R0 even
And:   (R2,R0) = R4*R5 ; Not OK, Both R2 and R0 are even

In that case you can implement your register file as two memories with
one write port.

/Andreas

Article: 126137
Subject: Re: FPGA for hobby use
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Thu, 15 Nov 2007 14:27:46 +0000
Links: << >>  << T >>  << A >>
On Wed, 14 Nov 2007 15:46:03 +0100, Herbert Kleebauer <klee@unibwm.de>
wrote:

>A few month ago I asked for a recommendation for FPGA (not a ready to use demo board)
>which could be handled with simple home equipment. I got the link to:
>
>http://www.enterpoint.co.uk/moelbryn/darnaw1.html

>Conclusion: 
>The board is great, [...] Sadly the same can't be 
>said about the current Xilinx software (schematic editor + simulator), 
>so we will try to stay as long as possible with the X3000 chips and the
>old Xilinx DOS software (with ViewLogic schematic entry + simulator).

Is there any technology-independent way out of the Viewlogic/Dos
software? Such as a fairly generic EDIF netlist?

The newer tools seem pretty stable, with the apparent exception of the
schematic path. Perhaps they can be induced to work with EDIF input
generated from the old schematic flow.

(If so, that may open the way to finding other, non-Xilinx, schematic
tools capable of generating compatible EDIF. Altium may have something
worth looking at, but not needing schematics, I haven't properly looked
at their products.)

- Brian


Article: 126138
Subject: Re: Xilinx Virtex-II Newbie
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Thu, 15 Nov 2007 14:27:51 +0000
Links: << >>  << T >>  << A >>
On Wed, 14 Nov 2007 23:49:25 +0100, Andrew Ganger
<Andrew.Ganger@yahoo.co.uk> wrote:

>
>> What you are asking for is outside the abilities of the Virtex-II
>> FPGA. Since the FPGA only contains dual-ported memories (either
>> SelectRAM-based or BlockRAM-based), there is no possible way to map
>> such a HDL description to the FPGA device.
>
>Thanks for your answer Nathan, so I cant have a register file that has 4
>read ports and 2 write ports with a Virtex II? Well, unfortunately I 
>need these number of ports else my ISA is not working. 

Register file should be no problem, inplemented in the FPGA fabric;
though it could be fairly large (assuming your description is
synthesisable). I suspect Nathan was talking about multi-port larger
blocks of memory.

Even there you can do it; multiplexing is simplest if your performance
needs are low, but it's not the only way. For example, to increase the
number of read ports, you can simply parallel memories, writing to them
all simultaneously. If you can get away with 2:1 multiplexing the write
ports, that may be all you need.

Do you need full bandwidth on all six ports simultaneously?

In any case, use the component you have as a wrapper for the detailed
implementation for that behaviour.

- Brian


Article: 126139
Subject: Re: Xilinx Virtex-II Newbie
From: Andrew Ganger <Andrew.G@yahoo.co.uk>
Date: Thu, 15 Nov 2007 14:38:44 +0000
Links: << >>  << T >>  << A >>

> I can think of MUL, DIV, MOD that might write two results,
> (but not so much in one cycle)
> but the only other instances I could think of would be
> extended size opcodes (normally handled reg-paired), and maybe
> merge of a MOV.
> 
> Source code does not tend to have two writes per expression ?

Yeah, multiplication is one example that uses two write ports.
The ISA is tailored towards a very specific domain of applications,
so therefore I have some not straight forward instructions. But
it would be handy in this case to have instructions that take 4 inputs
and generate 2 outputs.

Article: 126140
Subject: Re: Xilinx Virtex-II Newbie
From: Andrew Ganger <Andrew.G@yahoo.co.uk>
Date: Thu, 15 Nov 2007 14:41:20 +0000
Links: << >>  << T >>  << A >>

> Two write ports sounds dangerous :) -  but classic RISC devices
> might need 3 read ports, and one write port
> 
> Rd = Ra OPERAND Rb OPERAND Rc
> 
> one fast/simple idea I had for emulating this on dualport memory is to
> use two blocks and simply parallel  the one write port
> - so the two have identical info, and would actually give 4 read ports
> 
> Yes, it's a little redundant, but easy to implement, and the RegFiles
> are small anyway.

Yeah, it might be dangerous, but in my case I would need two write ports ;).

So yeah, this sounds like a good idea. So I would have two RAM blocks 
each with two read, and two write ports. In this case I write the result
back simultanlously in both register files. Looks like a good idea for
a first evaluation!

Thanks!

Article: 126141
Subject: Re: Xilinx Virtex-II Newbie
From: Andrew Ganger <Andrew.G@yahoo.co.uk>
Date: Thu, 15 Nov 2007 14:47:02 +0000
Links: << >>  << T >>  << A >>

> Register file should be no problem, inplemented in the FPGA fabric;
> though it could be fairly large (assuming your description is
> synthesisable). I suspect Nathan was talking about multi-port larger
> blocks of memory.

Thanks for your comment Brian. I will try and see what the tool tells me 
when trying to synthesise it. Is there an upper limit for read and write
ports for such kind of register files? Or is this just the case for 
memories?

> Even there you can do it; multiplexing is simplest if your performance
> needs are low, but it's not the only way. For example, to increase the
> number of read ports, you can simply parallel memories, writing to them
> all simultaneously. If you can get away with 2:1 multiplexing the write
> ports, that may be all you need.

Yeah that also sounds like a good idea. But as memory I have a simple 
single port read/write interface!

Cheers!


Article: 126142
Subject: Re: FPGA for hobby use
From: Ray Andraka <ray@andraka.com>
Date: Thu, 15 Nov 2007 09:48:22 -0500
Links: << >>  << T >>  << A >>
Brian Drummond wrote:

> Is there any technology-independent way out of the Viewlogic/Dos
> software? Such as a fairly generic EDIF netlist?

Yes, Viewlogic can output an edif netlist, at least it did some 10 years 
ago when I last used it.



Article: 126143
Subject: Re: newbie to 16v8
From: Ray Andraka <ray@andraka.com>
Date: Thu, 15 Nov 2007 09:50:11 -0500
Links: << >>  << T >>  << A >>
Amit wrote:

> Hi Ray,
> 
> Thank your response. what is your webiste's domain?
> 

http://www.andraka.com   You can find the multipliers under the DSP tab, 
or go directly to it with http://www.andraka.com/multipli.htm

Article: 126144
Subject: Re: Xilinx Virtex-II Newbie
From: EEngineer <maricic@gmail.com>
Date: Thu, 15 Nov 2007 07:12:55 -0800 (PST)
Links: << >>  << T >>  << A >>
On Nov 15, 9:41 am, Andrew Ganger <Andre...@yahoo.co.uk> wrote:
> > Two write ports sounds dangerous :) -  but classic RISC devices
> > might need 3 read ports, and one write port
>
> > Rd = Ra OPERAND Rb OPERAND Rc
>
> > one fast/simple idea I had for emulating this on dualport memory is to
> > use two blocks and simply parallel  the one write port
> > - so the two have identical info, and would actually give 4 read ports
>
> > Yes, it's a little redundant, but easy to implement, and the RegFiles
> > are small anyway.
>
> Yeah, it might be dangerous, but in my case I would need two write ports ;).
>
> So yeah, this sounds like a good idea. So I would have two RAM blocks
> each with two read, and two write ports. In this case I write the result
> back simultanlously in both register files. Looks like a good idea for
> a first evaluation!
>
> Thanks!

Probelem with this is what if more than two registers that need to be
written are located at the same RAM block! I am using 8 parallel
blocks in my design as I am writting 8 memory locations at a time but
I am sure that all 8 memory locations belong to different RAM block.

Article: 126145
Subject: Re: Xilinx Virtex-II Newbie
From: Andrew Ganger <Andrew.G@yahoo.co.uk>
Date: Thu, 15 Nov 2007 15:44:49 +0000
Links: << >>  << T >>  << A >>

> Hi, as others have pointed out you can create a register file with
> one write port and several read ports quite efficient. Could you constrain
> your instruction set so that the instruction that need to write to two
> registers is limited to a register pair of even and odd registers?
> 
> As in: (R1,R0) = R2*R3 ; Ok R1 odd, R0 even
> And:   (R2,R0) = R4*R5 ; Not OK, Both R2 and R0 are even
> 
> In that case you can implement your register file as two memories with
> one write port.

Sorry, I dont understand that. You suggest also to use 2 RAM block with 
each two read ports. They both should contain the same register values, 
so in other words, each RAM block requires 2 write ports so that I can 
keep the values in both registers consistent!

Article: 126146
Subject: EDK 9.1 Issues
From: Matthew Hicks <mdhicks2@uiuc.edu>
Date: Thu, 15 Nov 2007 17:01:53 +0000 (UTC)
Links: << >>  << T >>  << A >>
When working with custom peripherals in EDK, is there a better way to make 
sure changes to the hardware design take effect than trying to re-import 
the peripheral?  I spent several hours last night debugging a design that 
was failing because EDK wasn't loading the updated hardware design (just 
logic, no change in external ports).  I made sure it did a fresh synth+impl 
run every time, but somehow the functionality never changed even though the 
hw design did.  Even after removing the instance and re-importing and re-connecting 
it.  I finally got it to work by creating a completely new hw design (in 
name only) with the same logical functionality and using it in place of the 
previous block.


---Matthew Hicks



Article: 126147
Subject: Re: EDK 9.1 Issues
From: Philip Potter <pgp@see.sig.invalid>
Date: Thu, 15 Nov 2007 17:10:36 +0000
Links: << >>  << T >>  << A >>
Matthew Hicks wrote:
> When working with custom peripherals in EDK, is there a better way to 
> make sure changes to the hardware design take effect than trying to 
> re-import the peripheral?  I spent several hours last night debugging a 
> design that was failing because EDK wasn't loading the updated hardware 
> design (just logic, no change in external ports).  I made sure it did a 
> fresh synth+impl run every time, but somehow the functionality never 
> changed even though the hw design did.  Even after removing the instance 
> and re-importing and re-connecting it.  I finally got it to work by 
> creating a completely new hw design (in name only) with the same logical 
> functionality and using it in place of the previous block.

I think Project->Rescan User Repositories will solve your problem.

-- 
Philip Potter pgp <at> doc.ic.ac.uk

Article: 126148
Subject: V4FX: Cannot access EMAC1 of Dual MAC system
From: JimboD2@gmail.com
Date: Thu, 15 Nov 2007 09:53:05 -0800 (PST)
Links: << >>  << T >>  << A >>
I am implementing an PowerPC embedded system in EDK and am trying to
use both emac0 and emac1 hard cores of the fpga. I have implemented
two instances of the plb_temac ip core and the hard_temac core in EDK.
I've configured the hard_mac core's parameters to include EMAC1, and
have assigned unique identifiers to both macs (emac0 = 0, emac1 = 1).
I've also connected the "Provider/Command shared host bus"  between
the two plb_temac cores per the datasheet MHS example.

Using chipscope, i've observed that the host bus to the hard MAC is
functioning during read/writes for emac0, but not when addressing
emac1. It seems that the plb_temac for emac1 does not initiate a
transfer on the host bus.

Has anyone ever configured a dual temac PPC system? I would appreciate
any ideas as I am running out.

Thanks

Article: 126149
Subject: Re: V4FX: Cannot access EMAC1 of Dual MAC system
From: JimboD2@gmail.com
Date: Thu, 15 Nov 2007 09:58:52 -0800 (PST)
Links: << >>  << T >>  << A >>
To clarify my previous post, I am attempting to read/write to the hard
MAC's internal registers (EMAC mode configuration, Management
configuration, etc).
Thanks




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