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Messages from 125800

Article: 125800
Subject: Re: FPGA I/O Selection in UCF
From: jtindle@gmail.com
Date: Mon, 05 Nov 2007 21:45:11 -0000
Links: << >>  << T >>  << A >>
On Nov 5, 3:01 pm, Gabor <ga...@alacron.com> wrote:
> On Nov 5, 4:26 pm, jtin...@gmail.com wrote:
>
> > I have an application with a Xilinx Spartan3 FPGA where I would like
> > to use a single FPGA binary to support to I/O voltage levels: 2.8v and
> > 1.8v.  My question is as follows:
>
> > Why does the UCF file include the selected IO standard for each pin?
>
> It doesn't have to, but if you don't include the IO standard you
> get the global default (which depends on the device family).
>
> > I understand that the drive strengths and slew may change based on the
> > I/O standard.  Are there any other functional hardware changes made
> > based on the selected standard?  What are the potential consequences
> > of telling the compiler that I am using 2.8v but then running the
> > application with 1.8v?
>
> > Thanks
>
> The obvious changes in hardware are the Vcco (Bank IO power supply)
> and Vref (reference voltage for single-ended standards requiring a
> reference).  The placement tools make sure that the standards are
> compatible for all IO's in each bank.  i.e you can't mix IO's
> that require Vcco at 1.8V with those that require Vcco at 2.5V in
> the same bank.  Similar for inputs requiring different Vref in
> a bank.
>
> Some input standards don't use a reference voltage, but may need
> a particular Vcco voltage.  Output standards all need a specific
> Vcco.  Telling the tools you are running at 2.5V (did you mean 2.5
> and not 2.8?) but powering Vcco with 1.8V will result in hardware
> that does not match the simulation in terms of timing and drive
> capability and in some cases just won't work.

Thanks for the response.  I understood that the compiler verifies that
you don't mix/match different standards on the same I/O bank.

In my particular case all of the pins are inputs and I am adjusting
the Vcco supply with LVCMOS (VREF not used).  At some stage of the I/O
blocks, digital input signals must transition from the I/O voltage
levels to the internal voltage levels.  This is the area where I am
most curious.

I am assuming that the Input Register has transistors should be
supplied with VCCO whose VIH and VIL thresholds will roughly track
with the VCCO (i.e VIH ~= VCCO - X volts).  At this stage I am not
concerned about the input register detecting the signal level
properly, but I am concerned about the connecting blocks (CLK, Reset,
and output voltage threshold).  Ignoring timing considerations, do we
know if the compiler makes any hardware configuration to interconnect
the two voltage domains (Vcore, VCCO) at the input register?


Article: 125801
Subject: Re: FPGA I/O Selection in UCF
From: jtindle@gmail.com
Date: Mon, 05 Nov 2007 21:56:13 -0000
Links: << >>  << T >>  << A >>
On Nov 5, 3:25 pm, austin <aus...@xilinx.com> wrote:
> jt,
>
> The strength of the driver depends on the selected number of "legs"
> enabled, and the attributes (FAST or SLOW) for any particular Vcco voltage.
>
> IO's that require a Vref will require a different Vref voltage
> externally to operate properly.
>
> LVDS only works at 2.5 volts (in the latest parts).
>
> But, a LVCMOS IO that is set for 12 mA in the highest Vcco, will still
> be fairly strong at a lower Vcco.  Timing, rise and fall times will be
> slower at lower Vcco, but the LVCMOS IO will still function just fine.
>
> To really make sure this will work, I would download the SPICE models,
> and run them at the different Vcco voltages, and make sure the signal
> integrity met all of your needs.  The reason for simulating with SPICE
> is that you can change the Vcco, and see the result of fast and slow
> process corner material, as well as how the IO behaves with temperature.
>
> Austin

Hi Austin, thanks for the response.  It was my suspicion that LVCMOS
should work with the two voltages.  I should have included that detail
in my original post.

On a side note--I'm very happy to see Xilinx support here.  It's much
faster than waiting a day "to receive security clearance" to access
the Xilinx WebCase =)

Jeff



Article: 125802
Subject: Linux capable free/GPL SOFT CPU for XC3S500E?
From: Wojciech Zabolotny <wzab@ipebio15.ise.pw.edu.pl>
Date: Mon, 5 Nov 2007 22:11:37 +0000 (UTC)
Links: << >>  << T >>  << A >>
Hi All,

I'm looking for a possibility to run Linux (may be a ucLinux) on a
XC3S500E containing CPU and some custom peripherials.
The hardware platform should be a Spartan3E Starter Kit (rev. D), 
or something like this.

I have found the almost ready to use solution here:
http://muranaka.info/pukiwiki/index.php?MicroBlaze%20uClinux%20and%20Spartan-3E%20Starter%20Kit
but it is MicroBlaze based, which is not acceptable for me due to
licensing terms (which are even worse for the Ethernet MAC controller).
Has anybody tried to use the aeMB clone with the free OpenCores Ethernet
MAC controller with the MicroBlaze ucLinux? 

The OpenRisc and LEON3 seem to be too big for XC3S500E (or at least I
was not able to trim them sufficiently for this FPGA).

The most preferable solution seem to be a CPU which has a standard
instruction set (e.g. Plasma, which is MIPS I compatible), because in
this case the toolchain is well supported.

However I could not find any information if it is possible to run Linux
on the Plasma (or mips789) SOFT CPU.
Has anybody any experience in that subject?

There is an ideal solution announced on the OpenCores:
http://www.opencores.org/projects.cgi/web/m1_core/overview
But it is only an idea (Development status :: alpha)
-- 
TIA & Regards,
Wojtek Zabolotny


Article: 125803
Subject: Re: FPGA I/O Selection in UCF
From: austin <austin@xilinx.com>
Date: Mon, 05 Nov 2007 14:28:33 -0800
Links: << >>  << T >>  << A >>
jt,

Level shifters exist between all IO circuitry and all logic circuitry
which takes care of the differences between the IO and the core voltages.

As you have guessed, timing will be different.

Austin

Article: 125804
Subject: Re: Audio Output from Spartan 3 Starter Kit
From: Ray Andraka <ray@andraka.com>
Date: Mon, 05 Nov 2007 18:22:08 -0500
Links: << >>  << T >>  << A >>
FPGAs do indeed have the protection diodes.  You can drive a piezo 
directly from the FPGA if you like, however you'll probably find the 
audio volume less than satisfactory with the typical miniature 
transducers, especially with the low voltage I/O standards found on most 
of the modern FPGAs.  It helps if you drive it in a differential mode.

Article: 125805
Subject: Re: code hang after loading through gdb
From: xmkong@gmail.com
Date: Tue, 06 Nov 2007 00:29:08 -0000
Links: << >>  << T >>  << A >>
I found the reason now. In my case, I have several software
applications. When I downloaded the bitstream, sometimes pc register
doesn't contain correct value. Using GDB to download the elf file of
the application I want to run doesn't correct the pc register value
and hence the code hang. But downloading the elf file through xmd
shell can solve the problem.


Article: 125806
Subject: Re: Audio Output from Spartan 3 Starter Kit
From: MikeShepherd564@btinternet.com
Date: Tue, 06 Nov 2007 01:12:07 +0000
Links: << >>  << T >>  << A >>
>FPGAs do indeed have the protection diodes...

I am guided by "Cyclone II Device Handbook, Volume 1" (Altera
Corporation, July 2005), chapter 4 ("Hot Socketing & Power-On Reset"),
page 4-1:

   "There are no internal current paths from I/O pins
     to VCCIO or VCCINT power supplies. Signals
     driven in on I/O pins do not power the VCCIO or
     VCCINT power buses".

I understood this to indicate that there are no protection diodes in
this case (except perhaps to 0V), but you indicate that there are
always such diodes.  Have I misunderstood this?

Mike

Article: 125807
Subject: Re: Audio Output from Spartan 3 Starter Kit
From: Peter Alfke <alfke@sbcglobal.net>
Date: Mon, 05 Nov 2007 17:25:25 -0800
Links: << >>  << T >>  << A >>
On Nov 5, 5:12 pm, MikeShepherd...@btinternet.com wrote:
> >FPGAs do indeed have the protection diodes...
>
> I am guided by "Cyclone II Device Handbook, Volume 1" (Altera
It's the old conflict between ESD (electro-static discharge)
protection (which wants a strong diode against a well-defined voltage,
like VCC) and "Hot Socketing" which cannot tolerate a diode connected
to Vcc (since that would be against ground while the card is being
pushed in).
I cannot speak for Altera, but a traditional compromisen is a diode
against a positive Zener diode level.
If I were you, I would get a positive supply, a 10 kilohm series
resistor, and probe the pin to see how high the voltage will go. You
cannot do any harm with less than a mA, but it will clearly show you
the clamp voltage.
A good old multimeter is a wonderful thing, be it analog or
digital  :-)
A scope will do also, especially when it sits already on your bench.
Peter Alfke

> Corporation, July 2005), chapter 4 ("Hot Socketing & Power-On Reset"),
> page 4-1:
>
>    "There are no internal current paths from I/O pins
>      to VCCIO or VCCINT power supplies. Signals
>      driven in on I/O pins do not power the VCCIO or
>      VCCINT power buses".
>
> I understood this to indicate that there are no protection diodes in
> this case (except perhaps to 0V), but you indicate that there are
> always such diodes.  Have I misunderstood this?
>
> Mike



Article: 125808
Subject: Re: FPGA I/O Selection in UCF
From: hal-usenet@ip-64-139-1-69.sjc.megapath.net (Hal Murray)
Date: Mon, 05 Nov 2007 21:40:26 -0600
Links: << >>  << T >>  << A >>

>Thanks for the response.  I understood that the compiler verifies that
>you don't mix/match different standards on the same I/O bank.

I assume it only checks for incompatable standards.


>In my particular case all of the pins are inputs and I am adjusting
>the Vcco supply with LVCMOS (VREF not used).  At some stage of the I/O
>blocks, digital input signals must transition from the I/O voltage
>levels to the internal voltage levels.  This is the area where I am
>most curious.

>I am assuming that the Input Register has transistors should be
>supplied with VCCO whose VIH and VIL thresholds will roughly track
>with the VCCO (i.e VIH ~= VCCO - X volts).  At this stage I am not
>concerned about the input register detecting the signal level
>properly, but I am concerned about the connecting blocks (CLK, Reset,
>and output voltage threshold).  Ignoring timing considerations, do we
>know if the compiler makes any hardware configuration to interconnect
>the two voltage domains (Vcore, VCCO) at the input register?

How about making two versions of the same program that only differ
on the input standards.  Get the output to some sort of ascii
text and run them through diff.

-- 
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 125809
Subject: not totally repulsive
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Mon, 05 Nov 2007 20:33:42 -0800
Links: << >>  << T >>  << A >>


I usually have +5 volts available in VME modules, so I generally
linear-regulate down from +5 to 3.3, 2.5, and 1.2 for Spartan3 fpga's.
VME has lots of power and lots of air flow. My favorite trick is to
use an LM1117 regulator with its ADJ pin grounded, to make 1.25 volts.
A second LM1117 has its ADJ pin riding on the 1.25, so I get 2.5, all
with no resistors.

Now this new gadget: it's an uncooled small box powered from a 12 volt
wart. I don't need much 5 volts, so I switched directly to 3.3 and did
the same LM1117 thing. Oops. The 1117 has about a 1.1 volt dropout, so
I'm getting about +2.2 for Vccaux, sort of marginal.

So I'm thinking, why not yank the regulator and put a diode from 3.3
to make 2.5? So I pulled all the MELF diodes we have in stock. The
current draw on +2.5 is about 40 mA, increasing to 50 mA after
configuration (XC3S400, running mostly at 64 MHz). So I'm looking for
a diode with 0.8 volts drop at 50 mA.

As expected, big 1 amp, low-voltage (100v) diodes have the least drop,
around 0.64 volts. Higher voltage diodes, 600 and 1000 volts increase,
to about 0.70. So I tried some 1-watt zeners in the forward direction.
Bingo. A 5.1 volt Zetex part is 0.84, and an 8.2 volt zener is 0.805.

I wonder what might be the trend of zener forward voltage versus zener
reverse voltage. Doping and stuff.

http://img141.imageshack.us/my.php?image=diodeklugeqo3.jpg

I'm going to spin the board after this batch is used up, for other
reasons, so I suppose I'll do it right next pass. Probably go to
switchers for most everything.

John


Article: 125810
Subject: Re: not totally repulsive
From: "BobW" <nimby_NEEDSPAM@roadrunner.com>
Date: Mon, 5 Nov 2007 22:31:28 -0800
Links: << >>  << T >>  << A >>

"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message 
news:eiqvi3d3sfklij5lig4l258751bsopj0as@4ax.com...
>
>
> I usually have +5 volts available in VME modules, so I generally
> linear-regulate down from +5 to 3.3, 2.5, and 1.2 for Spartan3 fpga's.
> VME has lots of power and lots of air flow. My favorite trick is to
> use an LM1117 regulator with its ADJ pin grounded, to make 1.25 volts.
> A second LM1117 has its ADJ pin riding on the 1.25, so I get 2.5, all
> with no resistors.
>
> Now this new gadget: it's an uncooled small box powered from a 12 volt
> wart. I don't need much 5 volts, so I switched directly to 3.3 and did
> the same LM1117 thing. Oops. The 1117 has about a 1.1 volt dropout, so
> I'm getting about +2.2 for Vccaux, sort of marginal.
>
> So I'm thinking, why not yank the regulator and put a diode from 3.3
> to make 2.5? So I pulled all the MELF diodes we have in stock. The
> current draw on +2.5 is about 40 mA, increasing to 50 mA after
> configuration (XC3S400, running mostly at 64 MHz). So I'm looking for
> a diode with 0.8 volts drop at 50 mA.
>
> As expected, big 1 amp, low-voltage (100v) diodes have the least drop,
> around 0.64 volts. Higher voltage diodes, 600 and 1000 volts increase,
> to about 0.70. So I tried some 1-watt zeners in the forward direction.
> Bingo. A 5.1 volt Zetex part is 0.84, and an 8.2 volt zener is 0.805.
>
> I wonder what might be the trend of zener forward voltage versus zener
> reverse voltage. Doping and stuff.
>
> http://img141.imageshack.us/my.php?image=diodeklugeqo3.jpg
>
> I'm going to spin the board after this batch is used up, for other
> reasons, so I suppose I'll do it right next pass. Probably go to
> switchers for most everything.
>
> John
>

Keep in mind that VCCAUX is used to power all sorts of stuff, and I don't 
think it's all documented. So, if you change the FPGA design you may get 
more/less VCCAUX current. That along with temperature effects may push the 
voltage beyond its published limits.

If it were mine, I would bite the bullet and put in a proper ldo.

Maybe some wonderful Xilinx guy (e.g. Austin) will drop his $0.02 regarding 
the constancy of VCCAUX current on S3.

Bob



Article: 125811
Subject: Re: not totally repulsive
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Tue, 06 Nov 2007 19:33:47 +1300
Links: << >>  << T >>  << A >>
John Larkin wrote:

> 
> I usually have +5 volts available in VME modules, so I generally
> linear-regulate down from +5 to 3.3, 2.5, and 1.2 for Spartan3 fpga's.
> VME has lots of power and lots of air flow. My favorite trick is to
> use an LM1117 regulator with its ADJ pin grounded, to make 1.25 volts.
> A second LM1117 has its ADJ pin riding on the 1.25, so I get 2.5, all
> with no resistors.
> 
> Now this new gadget: it's an uncooled small box powered from a 12 volt
> wart. I don't need much 5 volts, so I switched directly to 3.3 and did
> the same LM1117 thing. Oops. The 1117 has about a 1.1 volt dropout, so
> I'm getting about +2.2 for Vccaux, sort of marginal.
> 
> So I'm thinking, why not yank the regulator and put a diode from 3.3
> to make 2.5? So I pulled all the MELF diodes we have in stock. The
> current draw on +2.5 is about 40 mA, increasing to 50 mA after
> configuration (XC3S400, running mostly at 64 MHz). So I'm looking for
> a diode with 0.8 volts drop at 50 mA.
> 
> As expected, big 1 amp, low-voltage (100v) diodes have the least drop,
> around 0.64 volts. Higher voltage diodes, 600 and 1000 volts increase,
> to about 0.70. So I tried some 1-watt zeners in the forward direction.
> Bingo. A 5.1 volt Zetex part is 0.84, and an 8.2 volt zener is 0.805.
> 
> I wonder what might be the trend of zener forward voltage versus zener
> reverse voltage. Doping and stuff.
> 
> http://img141.imageshack.us/my.php?image=diodeklugeqo3.jpg
> 
> I'm going to spin the board after this batch is used up, for other
> reasons, so I suppose I'll do it right next pass. Probably go to
> switchers for most everything.
> 
> John

There will be a temperature variantion on this, and you should verify 
the drop in operating conditions (it is a diode, and any ringing will be
rectified - so a slow one like a Zener is probably a good choice )

Also note that the % Vcc variation is amplified on this.
3.3C +/- 10% or 3.0..3.6 , now becomes 2.2-2.8V, and a 20% window,
is now 27.3% - so you'll need tighter starting Vcc levels.

But it will work. I've also looked at using Yellow LEDs as low-cost
1.8V shunt regulators for CPLDs :)

-jg






Article: 125812
Subject: Re: Digilent V2P Board
From: Andreas Ehliar <ehliar-nospam@isy.liu.se>
Date: Tue, 6 Nov 2007 07:17:07 +0000 (UTC)
Links: << >>  << T >>  << A >>
On 2007-10-31, David Binnie <td.binnie@blueyonder.co.uk> wrote:
> Using the Digilent XUP V2P Board, I have to use additional memory (256 Mb 
> DDR SDRAM).
>
> The only memory drivers I can find run with the embedded processor kit.  I 
> do not wish to use the PowerPC or Microblaze processor nor the EDK.  Does 
> any one have access to some code to access the add on memory module 
> directly.

Try looking for the memory interface generator (MIG) on Xilinx' homepage.
You will have to register to access it, but as far as I know, anyone can
register.


/Andreas

Article: 125813
Subject: Re: Linux capable free/GPL SOFT CPU for XC3S500E?
From: Antti <Antti.Lukats@googlemail.com>
Date: Tue, 06 Nov 2007 07:45:28 -0000
Links: << >>  << T >>  << A >>
On 5 Nov., 23:11, Wojciech Zabolotny <w...@ipebio15.ise.pw.edu.pl>
wrote:
> Hi All,
>
> I'm looking for a possibility to run Linux (may be a ucLinux) on a
> XC3S500E containing CPU and some custom peripherials.
> The hardware platform should be a Spartan3E Starter Kit (rev. D),
> or something like this.
>
> I have found the almost ready to use solution here:http://muranaka.info/pukiwiki/index.php?MicroBlaze%20uClinux%20and%20...
> but it is MicroBlaze based, which is not acceptable for me due to
> licensing terms (which are even worse for the Ethernet MAC controller).
> Has anybody tried to use the aeMB clone with the free OpenCores Ethernet
> MAC controller with the MicroBlaze ucLinux?
>
> The OpenRisc and LEON3 seem to be too big for XC3S500E (or at least I
> was not able to trim them sufficiently for this FPGA).
>
> The most preferable solution seem to be a CPU which has a standard
> instruction set (e.g. Plasma, which is MIPS I compatible), because in
> this case the toolchain is well supported.
>
> However I could not find any information if it is possible to run Linux
> on the Plasma (or mips789) SOFT CPU.
> Has anybody any experience in that subject?
>
> There is an ideal solution announced on the OpenCores:http://www.opencores.org/projects.cgi/web/m1_core/overview
> But it is only an idea (Development status :: alpha)
> --
> TIA & Regards,
> Wojtek Zabolotny

linux should run nicely on MIPS arch, but not sure about Plasma, well
also interested in the same as you
Antti




Article: 125814
Subject: Re: Is it possible to debug a vhdl design over jtag?
From: Pablo <pbantunez@gmail.com>
Date: Tue, 06 Nov 2007 00:26:40 -0800
Links: << >>  << T >>  << A >>
Thanks for your advices. I suppose that Chipscope is a good option.





Article: 125815
Subject: Re: Linux capable free/GPL SOFT CPU for XC3S500E?
From: mares.vit@gmail.com
Date: Tue, 06 Nov 2007 00:44:08 -0800
Links: << >>  << T >>  << A >>
You can try http://www.niktech.com/ and their Manik CPU
It seems to be small enough to fit into the XCS500E with several
peripherals.
Here is startup description for Spartan-3 Starter Kit
http://www.niktech.com/GettingStarted.pdf
Vit


Article: 125816
Subject: Re: Linux capable free/GPL SOFT CPU for XC3S500E?
From: Steven Derrien <sderrienREMOVE@irisa.fr>
Date: Tue, 06 Nov 2007 09:55:19 +0100
Links: << >>  << T >>  << A >>
Antti a écrit :
> On 5 Nov., 23:11, Wojciech Zabolotny <w...@ipebio15.ise.pw.edu.pl>
> wrote:
> 
> linux should run nicely on MIPS arch, but not sure about Plasma, well
> also interested in the same as you
> Antti
> 

Hi,

I was also considering trying to port uCLinux on the Plasma CPU, but I 
quickly gave up (too complicated for me ;)), however I found an 
interesting page regarding the porting on uCLInux to MIPS arch.

http://www.xiptech.com/uclinuxformips.htm

Hope it can help.

Steven



> 

Article: 125817
Subject: Re: Linux capable free/GPL SOFT CPU for XC3S500E?
From: Wojciech Zabolotny <wzabolot@elektron.elka.pw.edu.pl>
Date: Tue, 6 Nov 2007 10:40:08 +0100
Links: << >>  << T >>  << A >>


On Tue, 6 Nov 2007, mares.vit@gmail.com wrote:

> You can try http://www.niktech.com/ and their Manik CPU
> It seems to be small enough to fit into the XCS500E with several
> peripherals.
> Here is startup description for Spartan-3 Starter Kit
> http://www.niktech.com/GettingStarted.pdf
> Vit
>
When I checked Manik CPU a few months ago, I couldn't find any information 
regarding its licensing.
I have sent a question to niktech about it, but have never received any 
answer. Without clear license allowing me to use it, I will not risk 
basing my laboratory on this design, even though it seems to be very 
nice...

Wojtek


Article: 125818
Subject: Re: Linux capable free/GPL SOFT CPU for XC3S500E?
From: mares.vit@gmail.com
Date: Tue, 06 Nov 2007 02:17:28 -0800
Links: << >>  << T >>  << A >>
On 6 Lis, 10:40, Wojciech Zabolotny <wzabo...@elektron.elka.pw.edu.pl>
wrote:
> On Tue, 6 Nov 2007, mares....@gmail.com wrote:
> > You can tryhttp://www.niktech.com/and their Manik CPU
> > It seems to be small enough to fit into the XCS500E with several
> > peripherals.
> > Here is startup description for Spartan-3 Starter Kit
> >http://www.niktech.com/GettingStarted.pdf
> > Vit
>
> When I checked Manik CPU a few months ago, I couldn't find any information
> regarding its licensing.
> I have sent a question to niktech about it, but have never received any
> answer. Without clear license allowing me to use it, I will not risk
> basing my laboratory on this design, even though it seems to be very
> nice...
>
> Wojtek

To get some response it needed some investigation to get the right
email :-)
When you search this forum for Niktech+Manik you can find Sandeep
Dutta name
The right email was niktechc@niktech.com

He sent me answers to several questions
   >>> Did you try to port uClinux to Manik?
   No we have not yet started porting uCLinux, we do have plans to
port it.
   >>> What is the licence of Manik CPU core and other IP cores?
   The licensing scheme is very simple, you can use the core
   in your product for free, you cannot re-sell the core itself,
   you are not obligated to give out the source of any derived work.
   Consider it being a GPL with expection that if you instantiate this
   core in your design it does by itself make the resulting work
covered by
   GPL.
   >>> Will you put it to opencores.org?
   Currently we ave no plans to put it into opencores.
   Sandeep

Regards
   Vit


Article: 125819
Subject: May i program a Spartan 3 fpga with a 1,8 V Digilent cable?
From: "blisca" <bliscachiocciolinatiscali.it>
Date: Tue, 6 Nov 2007 11:20:41 +0100
Links: << >>  << T >>  << A >>
Hi ,i like to use cpld and fpgas scraped by boards at home at the purpose of
practicing VHDL.
I have some Spartan 3    XC3S1500,and an inexpensive Digilent JTAG cable
rated 1.8 to 5.5 V.
There is some trick to use it for programming a Spartan 3 ,having a core
voltage of 1,2V?
Thanks
Diego,Italy



Article: 125820
Subject: Re: Linux capable free/GPL SOFT CPU for XC3S500E?
From: Wojciech Zabolotny <wzabolot@elektron.elka.pw.edu.pl>
Date: Tue, 6 Nov 2007 11:47:51 +0100
Links: << >>  << T >>  << A >>
On Tue, 6 Nov 2007, mares.vit@gmail.com wrote:
>
> To get some response it needed some investigation to get the right
> email :-)
> When you search this forum for Niktech+Manik you can find Sandeep
> Dutta name
> The right email was niktechc@niktech.com
>
> He sent me answers to several questions
>   >>> Did you try to port uClinux to Manik?
>   No we have not yet started porting uCLinux, we do have plans to
> port it.
>   >>> What is the licence of Manik CPU core and other IP cores?
>   The licensing scheme is very simple, you can use the core
>   in your product for free, you cannot re-sell the core itself,
>   you are not obligated to give out the source of any derived work.
>   Consider it being a GPL with expection that if you instantiate this
>   core in your design it does by itself make the resulting work
> covered by
>   GPL.

It looks out much better, but anyway it would be nice to have the license 
terms included in the sources.
Additionally the above statement seem to me to be self-contradictory.
I'm not a native english speaker, so maybe I've misunderstood something,
but it seems to me that it should be either:
version 1
a) "you are not obligated to give out the source of any derived work"
b) "Consider it being a GPL with eception that if you instantiate this
    core in your design it does NOT by itself make the resulting work
    covered by GPL."

or:

version 2
a) "you are (deleted not) obligated to give out the source of any derived 
work"
b) "Consider it being a GPL with eception that if you instantiate this
    core in your design it does by itself make the resulting work
    covered by GPL."

The version two is less probable, because it would be the standard GPL, so 
no exception is needed at all.

BTW is the author of the MANIK the same Sandeep Dutta who originated the 
SDCC compiler (http://sdcc.sf.net)?
In this case we owe MAAAAANY THANKS to him for all his open source 
contributions ;-).
-- 
Wojtek

Article: 125821
Subject: Re: Linux capable free/GPL SOFT CPU for XC3S500E?
From: Andreas Ehliar <ehliar-nospam@isy.liu.se>
Date: Tue, 6 Nov 2007 11:01:03 +0000 (UTC)
Links: << >>  << T >>  << A >>
On 2007-11-05, Wojciech Zabolotny <wzab@ipebio15.ise.pw.edu.pl> wrote:
> The OpenRisc and LEON3 seem to be too big for XC3S500E (or at least I
> was not able to trim them sufficiently for this FPGA).

You might be interested in looking at the Lattice Mico32 as well. It is
also open source and I know that people have used it on Xilinx devices.

/Andreas

Article: 125822
Subject: Re: Linux capable free/GPL SOFT CPU for XC3S500E?
From: mares.vit@gmail.com
Date: Tue, 06 Nov 2007 03:16:35 -0800
Links: << >>  << T >>  << A >>
I think he is the SDCC original author.
Vit



Article: 125823
Subject: ERROR:MDT - transparent bus interface connector
From: xenix <lastval@gmail.com>
Date: Tue, 06 Nov 2007 13:50:28 -0000
Links: << >>  << T >>  << A >>
Hello all,
      I am facing the error below when i am doing generate libs and
BSB's.

ERROR:MDT - transparent bus interface connector 'xxx_bram' is only
referenced
   once!

any views?

I am using XPS 6.2 version.

regards


Article: 125824
Subject: Re: not totally repulsive
From: Eli Hughes <emh203@psu.edu>
Date: Tue, 06 Nov 2007 09:31:23 -0500
Links: << >>  << T >>  << A >>
Jim Granville wrote:
> John Larkin wrote:
> 
>>
>> I usually have +5 volts available in VME modules, so I generally
>> linear-regulate down from +5 to 3.3, 2.5, and 1.2 for Spartan3 fpga's.
>> VME has lots of power and lots of air flow. My favorite trick is to
>> use an LM1117 regulator with its ADJ pin grounded, to make 1.25 volts.
>> A second LM1117 has its ADJ pin riding on the 1.25, so I get 2.5, all
>> with no resistors.
>>
>> Now this new gadget: it's an uncooled small box powered from a 12 volt
>> wart. I don't need much 5 volts, so I switched directly to 3.3 and did
>> the same LM1117 thing. Oops. The 1117 has about a 1.1 volt dropout, so
>> I'm getting about +2.2 for Vccaux, sort of marginal.
>>
>> So I'm thinking, why not yank the regulator and put a diode from 3.3
>> to make 2.5? So I pulled all the MELF diodes we have in stock. The
>> current draw on +2.5 is about 40 mA, increasing to 50 mA after
>> configuration (XC3S400, running mostly at 64 MHz). So I'm looking for
>> a diode with 0.8 volts drop at 50 mA.
>>
>> As expected, big 1 amp, low-voltage (100v) diodes have the least drop,
>> around 0.64 volts. Higher voltage diodes, 600 and 1000 volts increase,
>> to about 0.70. So I tried some 1-watt zeners in the forward direction.
>> Bingo. A 5.1 volt Zetex part is 0.84, and an 8.2 volt zener is 0.805.
>>
>> I wonder what might be the trend of zener forward voltage versus zener
>> reverse voltage. Doping and stuff.
>>
>> http://img141.imageshack.us/my.php?image=diodeklugeqo3.jpg
>>
>> I'm going to spin the board after this batch is used up, for other
>> reasons, so I suppose I'll do it right next pass. Probably go to
>> switchers for most everything.
>>
>> John
> 
> There will be a temperature variantion on this, and you should verify 
> the drop in operating conditions (it is a diode, and any ringing will be
> rectified - so a slow one like a Zener is probably a good choice )
> 
> Also note that the % Vcc variation is amplified on this.
> 3.3C +/- 10% or 3.0..3.6 , now becomes 2.2-2.8V, and a 20% window,
> is now 27.3% - so you'll need tighter starting Vcc levels.
> 
> But it will work. I've also looked at using Yellow LEDs as low-cost
> 1.8V shunt regulators for CPLDs :)
> 
> -jg
> 
> 
> 
> 
> 


You realize that there ire tiny switching regulators that are about the 
same size as the monolithic linear ones?


National semi was any easy tool that will generate a reference design.



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