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Messages from 126050

Article: 126050
Subject: Re: Spartan3E Slave Serial Daisy chain
From: Gabor <gabor@alacron.com>
Date: Tue, 13 Nov 2007 08:25:50 -0800
Links: << >>  << T >>  << A >>
On Nov 13, 4:35 am, Andrew Greensted <ajg...@ohm.york.ac.uk> wrote:
> Andrew Greensted wrote:
> > Q3: As for bit ordering, I'm pretty sure this is correct:
> > I'm reading the generated binary file (array.bin) 1 byte at a time and
> > shifting the MSB first. I'm also shifting some dummy data (DIN='1')
> > after the bitstream.
>
> Well, I was sure I had the bit ordering right, but it would seem not!!!
> Shifting in the LSB first, on a byte-by-byte basis made is work.
>
> So just in case any one else has the same problem in the future:
>
> I've got 3 Spartan3E XC3S500E in slave serial mode daisy-chained together.
> I'm using an Atmel AVR (ATMega644) running at 3.3V with a 10MHz clock.
> (The bit file is held on an SDCard)
>
> The slave serial controls are connected to the AVR.
>
> DOUT (from fpga 3) is input to the AVR
> DIN (to fpga 1) is output from the AVR
> DONE is input to the AVR
> CCLK is output from the AVR
> INIT_B is input to the AVR
> PROG_B is output from the AVR
>
> For the Spartan3E, all signals apart from the PROG_B are 3.3V tolerant,
> so these can be connected directly to the AVR.
>
> DONE is 2.5V high, but the AVR should read this as a '1' (Just with a
> lower noise threshold)
>
> PROG_B needs to be 2.5V high, so it needs some kind of level
> translation, I used a SN74LVC1G07DCK (Farnell 128-7544). It's an open
> drain driver. use this with a 4.7k
>
> All FPGA DONE signals are common (with a 330R pull-up)
> All PROG_B signals are common (with a 4.7k pull-up)
> All INIT_B signals are common (with a 4.7k pull-up)
>
> A binary file is created using the following command:
> promgen -w -p bin -u 0 device1.bit device2.bit device3.bit -o array.bin
>
> It is loaded like this:
>
> for each byte in the bin file
>
>    // Get byte
>    byte = next byte from bin file;
>
>    // Iterate through each bit
>    for each bit 0 to 7
>
>      // If bit=1 set DATA high (Keep PROG_B high during config)
>      if (byte & 0x01) data = PROG_B | DATA_AVR2FPGA;
>      else data = PROG_B;
>
>      // output data
>      output data;
>
>      // set CCLK high
>      data = data | CCLK;
>
>      // output data and CCLK
>      output data;
>
>      byte >>= 1;
>
>    end for
>
> end for
>
> Hope all that helps someone
> Andy


This is interesting.  What revision of iMpact/promgen are you using?
I
have seen issues with version 8.x where the bits are swapped for .hex
file outputs even if you un-check the box for swap bits.  This was in
fact why i was using promgen from the command line for creating
my .hex
files rather than the iMpact GUI.  I haven't tried the .bin file
output option, though.  Perhaps if you look deep enough into the
documents you'll find that the .bin option also defaults to swapped
bits?

Regards,
Gabor


Article: 126051
Subject: Re: Structured way of changing eg time constants for real world build / simulation?
From: "Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk>
Date: Tue, 13 Nov 2007 16:26:59 -0000
Links: << >>  << T >>  << A >>
> I would use a generic, passed up to the top level, with a default
> value defined for synthesis. Then when you instantiate the top level
> module in your testbench for simulation, override the default value
> with a generic map. This can be done for one or a whole group of
> generics. If you use a group of generics, you can define them as
> elements of a record type in a package, and every entity takes that
> generic record. That way when you want to add a generic for some lower
> level entity, you just have to add it's element to the record
> definition, then set it at the top (default and testbench), and use it
> at the leaf level where needed. The record definition acts like a
> conduit through which you can pass anything you want.
>
> Andy


Another nice trick, although after spending ages trying to get my head
round a design I had to pick that used records on port maps everywhere
I tend to try to avoid them.

Sometimes they can be a great tool for obfuscation :-)



Nial. 



Article: 126052
Subject: Re: Spartan3E Slave Serial Daisy chain
From: Andrew Greensted <ajg112@ohm.york.ac.uk>
Date: Tue, 13 Nov 2007 16:47:11 +0000
Links: << >>  << T >>  << A >>
Gabor wrote:

> This is interesting.  What revision of iMpact/promgen are you using?

Its ISE version 9.1 (With SP3).

Yes, I have to admit, I'm confused too. I used the .rbt (ASCII 1s and 
0s) file to check the bit ordering. I assumed this would be created with 
the bits ordered in the sequence they should be shifted in the chain. I 
was sure I was reading the bin file to replicated this.

Hey ho, its working now

Andy

Article: 126053
Subject: Re: implementing MAC protocols on fpga
From: dilip <dilip.manu@gmail.com>
Date: Tue, 13 Nov 2007 16:47:50 -0000
Links: << >>  << T >>  << A >>
thanks for that fnd, but i am working on wireless protocols, not a
cable LAN....
does this work for wireless too??
Stef wrote:
> In comp.arch.fpga,
> dilip <dilip.manu@gmail.com> wrote:
> > hi fnds, i am working on implementing MAC protocols on fpga...i am a
> > bit stuck in the way to start the process, like, how to give 2
> > simultaneous inputs to an fpga? and how to detect if collision has
> > occured or not?
> > so, if anyone can help pls post a reply...
>
> Are you talking about Ethernet?
>
> If so, you need an analog frontend to interface with the cable, you can
> not directly connect the cable to the FPGA. Easiest (and only?) option is
> to use an Ethernet PHY. The PHY handles the analog stuff, speed
> negotiation, collisions  and other stuff. Connect it (or multiple) to
> your FPGA using the MII (or RMI) interface. Read the PHY datasheet and
> google for other ethernet information sources.
>
> --
> Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail)


Article: 126054
Subject: Re: implementing MAC protocols on fpga
From: EEngineer <maricic@gmail.com>
Date: Tue, 13 Nov 2007 17:07:30 -0000
Links: << >>  << T >>  << A >>
On Nov 13, 11:47 am, dilip <dilip.m...@gmail.com> wrote:
> thanks for that fnd, but i am working on wireless protocols, not a
> cable LAN....
> does this work for wireless too??
>
> Stef wrote:
> > In comp.arch.fpga,
> > dilip <dilip.m...@gmail.com> wrote:
> > > hi fnds, i am working on implementing MAC protocols on fpga...i am a
> > > bit stuck in the way to start the process, like, how to give 2
> > > simultaneous inputs to an fpga? and how to detect if collision has
> > > occured or not?
> > > so, if anyone can help pls post a reply...
>
> > Are you talking about Ethernet?
>
> > If so, you need an analog frontend to interface with the cable, you can
> > not directly connect the cable to the FPGA. Easiest (and only?) option is
> > to use an Ethernet PHY. The PHY handles the analog stuff, speed
> > negotiation, collisions  and other stuff. Connect it (or multiple) to
> > your FPGA using the MII (or RMI) interface. Read the PHY datasheet and
> > google for other ethernet information sources.
>
> > --
> > Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail)

You need an analog frontend again, with RF part on it. Google Wireless
Ethernet PHY.

Dan


Article: 126055
Subject: Re: Structured way of changing eg time constants for real world build / simulation?
From: John Adair <g1@enterpoint.co.uk>
Date: Tue, 13 Nov 2007 09:24:57 -0800
Links: << >>  << T >>  << A >>
Personally I use two copies of a VHDL package with constants etc in
there. Named clearly as SIM or SYNTHESIS. You just need to carefully
keep the two copies in track with any extra values added.

John Adair
Enterpoint Ltd. - Home of Darnaw1 the PGA FPGA Module.


On 13 Nov, 10:12, "Nial Stewart"
<nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:
> Frequently when doing simulation of a design I'll change time
> constants so I can run the simulation in a reasonable timescale.
>
> I like to keep things simple so to date this has mostly involved
> commenting out the 'proper' value with a -- XXXX comment at the end
> of the line. When I want to do a real workd build a search for
> -- XXXX throughout the design should allow me to quickly find the
> values that need changed and comment them back to their correct
> values.
>
> Except I keep forgetting. Over the years this has caused hours of
> lost work until I have realised what I've done.
>
> I've thought of including a generic in all my modules by default to
> indicate whether simulation or real world build is being done, this


> could be propogated down from the top of a design to select which
> values are being used. Another solution would be a script to search the
> source directory commenting out --XXXX lines and uncommenting -- YYYY
> lines (for example).
>
> But why re-invent the wheel....
>
> Does anyone have a clever (simple) structured way of ensuring that
> temporary simulation values aren't included when doing real world builds?
>
> Thanks for any pointers,
>
> Nial.



Article: 126056
Subject: Re: Spartan3E Slave Serial Daisy chain
From: "John_H" <newsgroup@johnhandwork.com>
Date: Tue, 13 Nov 2007 10:06:05 -0800
Links: << >>  << T >>  << A >>
"Gabor" <gabor@alacron.com> wrote in message 
news:1194971150.220560.193390@o3g2000hsb.googlegroups.com...
>
> This is interesting.  What revision of iMpact/promgen are you using?
> I
> have seen issues with version 8.x where the bits are swapped for .hex
> file outputs even if you un-check the box for swap bits.  This was in
> fact why i was using promgen from the command line for creating
> my .hex
> files rather than the iMpact GUI.  I haven't tried the .bin file
> output option, though.  Perhaps if you look deep enough into the
> documents you'll find that the .bin option also defaults to swapped
> bits?
>
> Regards,
> Gabor

I mentioned before: promgen produces one bit order, Impact produces another. 
There's an option to generate a .bin file for the main program file 
implementation "tab" as well as a "BIN" output format for the Impact 
project.  These two files are bit-reversed within a byte. 



Article: 126057
Subject: Re: Structured way of changing eg time constants for real world build / simulation?
From: Andy <jonesandy@comcast.net>
Date: Tue, 13 Nov 2007 10:46:45 -0800
Links: << >>  << T >>  << A >>
On Nov 13, 10:26 am, "Nial Stewart"
<nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:
> > I would use a generic, passed up to the top level, with a default
> > value defined for synthesis. Then when you instantiate the top level
> > module in your testbench for simulation, override the default value
> > with a generic map. This can be done for one or a whole group of
> > generics. If you use a group of generics, you can define them as
> > elements of a record type in a package, and every entity takes that
> > generic record. That way when you want to add a generic for some lower
> > level entity, you just have to add it's element to the record
> > definition, then set it at the top (default and testbench), and use it
> > at the leaf level where needed. The record definition acts like a
> > conduit through which you can pass anything you want.
>
> > Andy
>
> Another nice trick, although after spending ages trying to get my head
> round a design I had to pick that used records on port maps everywhere
> I tend to try to avoid them.
>
> Sometimes they can be a great tool for obfuscation :-)
>
> Nial.

Yeah, records on ports can get really ugly, especially since
everything ends up being of mode inout, with default 'Z' drivers,
etc.

Fortunately for generics, which are "in" only, it is not as bad.

I've been wishing for user defined modes for record type ports (or
procedure arguments), used in lieu of in, out or inout, that would
allow you to specify the mode of each individual element. If only we
could do something like:

  type bus_type is record
    data : std_logic_vector(31 downto 0);
    ack : std_logic;
    ...
  end record;
  mode slave of bus_type is (data => inout; ack => out; others => in);
  mode master of bus_type is (data => inout; ack | clk | rst => in;
others => out);

Andy


Article: 126058
Subject: Re: Students: where to go for help
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 13 Nov 2007 10:52:57 -0800
Links: << >>  << T >>  << A >>
"Philip Potter" <pgp@see.sig.invalid> wrote in message 
news:fhbsdg$3va$1@aioe.org...
>
> It was straight out of the box and into the computer, but it may have been 
> damaged in transit.
>
> -- 
> Philip Potter pgp <at> doc.ic.ac.uk

Hi Philip,

Scratched DVDs are defenceless against fresh fruit.

http://youtube.com/watch?v=eo9y7jjoWKs

HTH., Syms. 



Article: 126059
Subject: [EDK simulation] synopsys translate_off
From: Pasacco <pasacco@gmail.com>
Date: Tue, 13 Nov 2007 10:58:36 -0800
Links: << >>  << T >>  << A >>
Dear

I would like to ask some help, for simulating EDK project.

I did following steps:

--------------------------------------------------------------------------------
1. Generate "simulation model and compiler script" using EDK 8.2 tool.

2. Compile design.
    " do system.do"

Following error ocurred:

-----------------------
# ** Error: C:/Work/TEST/SimpleEDK8.2/pcores/mem_main/hdl/vhdl/
clock_dcm.vhd(19): Library virtex2 not found.
# ** Error: C:/Work/TEST/SimpleEDK8.2/pcores/mem_main/hdl/vhdl/
clock_dcm.vhd(20): (vcom-1136) Unknown identifier "virtex2".
-----------------------

In the "clock_dcm.vhd", I commented following library definition:
-----------------------
-- synopsys translate_off
-- library	virtex2;
-- use virtex2.all;
-- synopsys translate_on
-----------------------

Now "system.do" is compiled.

3. Load design

    "vsim system"

Following warning occurred:

-----------------------
Warning: Component instance "ramx32 : ramb16_s36_s36" is not bound.
-----------------------

This means that BRAM block is present.
I ignored this warning and proceeded to next step:

4. Run simulation

Finally, following error occurred:

-----------------------
# ** Fatal: (vsim-3421) Value 127 is out of range 0 to 5.
#    Time: 0 ns  Iteration: 12  Process: /testbench/uut/buffer/out_mux
File: C:/Work/TEST/SimpleEDK8.2/pcores/Buffer_Wrapper_v1_00_a/hdl/vhdl/
buffer.vhd
# Fatal error in Process out_mux at
-----------------------

This looks like a logical error in VHDL.
But this VHDL file is provided by the board vendor.
I think I made mistake in the simulation process.

--------------------------------------------------------------------------------

My question is that

If I need to use following library "virtex2", how can I generate this
library "virtex2"?

-----------------------
-- synopsys translate_off
    library	virtex2;
    use virtex2.all;
-- synopsys translate_on
-----------------------

Thank you again.


Article: 126060
Subject: Re: EDK 8.2 tool : simulator set up
From: Pasacco <pasacco@gmail.com>
Date: Tue, 13 Nov 2007 11:02:38 -0800
Links: << >>  << T >>  << A >>
Now simulation models and compile script are generated.
Thank you for your help.


Article: 126061
Subject: Chipscope Server for PowerPC?
From: biker@wavenet.at
Date: Tue, 13 Nov 2007 12:39:31 -0800
Links: << >>  << T >>  << A >>
Hi All,

I have got 2 Virtex5, each with its own PlatformFlash chained together
for Programming/Debugging over JTAG.
In-System-Programming is easy, because of the availability of the
Xilinx-Jtag-Player, which we have managed to run on a MPC8349 based
Linux board.

Q: Is there any chipscope server source code, or a compiled one for
MPC8349, so that debugging over Chipscope Pro without USB-Cable is
possible?


Thanks for any help you can offer
Ed


Article: 126062
Subject: Re: how to make ports visible?
From: roger <roger.jons@gmail.com>
Date: Tue, 13 Nov 2007 22:42:49 -0000
Links: << >>  << T >>  << A >>
On Nov 13, 2:41 pm, xenix <last...@gmail.com> wrote:
> Hello all,
>
> I am trying to make the  PORT B of a BRAM visible in EDK ver.6.2i .
> The only ports can make visible from PORT B is  only the CLK.
>
> have you any idea how to do the rest ports of BRAM PORT B visible?
>
> regards

Hi!

Do you mean that you want port B of a BRAM possible to connect to as
independent ports and not a bus interface? In that case make a copy of
the file bram_block_v2_1_0.mpd in the $EDK/hw/XilinxProcessorIPLib/
pcores/bram_block_v1_00_a/data folder and rename it for example
bram_block_modified.mpd. Remove the BUS = PORTB and the default
connections of the signals, i.e. instead of BRAM_Dout_B = BRAM_Dout
insert BRAM_Dout_B = "". Add the mpd file to the user repository of
EDK and then you might have to restart XPS. Add the modified file to
your project and now port B of the bram will be visible in the port
connections. I have done this in later versions of EDK, hopefully it
will work in 6.2 as well.

Regards,
Roger


Article: 126063
Subject: Synthesis-place&route performance test.
From: posedge52@yahoo.com
Date: Tue, 13 Nov 2007 16:41:40 -0800
Links: << >>  << T >>  << A >>
I would like to find out how well different system setups performs
when it comes to Synthesis, Place & Route with Xilinx ISE tools. I
would like you to synth/place/route the source package below. And then
reply with:
  cpu type, cpu frequency,
  ram type, ram size,
  motherboard vendor/model,
  operating system (uname -a),
  total time used.

File:  http://filewebhosting.com/download.php?file=476Minimig1.tar.bz2

Tested on linux Xilinx ISE 8.1i.
If you run any linux compatible system it's just to download and type:
  bzip2 -dc Minimig1.tar.bz2 | tar -xvpf -
  cd Minimig1
  time make ; uname -a

The makefile might work in win32 enviroment (or use the gui).
Even obsolete systems is of interest. To get more data on which
factors that makes a performance difference.


Article: 126064
Subject: REFCLK signal in Hard TEMAC core
From: JimboD2@gmail.com
Date: Tue, 13 Nov 2007 20:33:20 -0800
Links: << >>  << T >>  << A >>
I am troubleshooting a tri-mode ethernet interface utilizing the hard
MAC core provided in the VirtexFX series of FPGAs. I've instantiated
the hard TEMAC wrapper and the plb_TEMAC core that connects the plb
bus to the hard core. I'm still trying to read/write to the PHY's
registers over the management interface. I'm using GMII between the
MAC and PHY.

The hard temac wrapper core has a REFCLK input signal. The only
mention of this in the datasheet is regarding SGMII mode. REFCLK is
used for calibrating the IDELAYCTRL blocks needed for SGMII. I assumed
that for GMII, this clock was not needed. However, looking at the
plb_temac datasheet, they list an mhs file example for a dual MAC GMII
ethernet interface. In this example, they show REFCLK connected to the
plb clock.

Does anyone know if this signal is needed? Currently when I attempt a
PHY register read, I see both Management interrupts asset but never
see any data back. I have also not seen any activity on the MDIO/MDC
lines, so im led to believe this is a problem with how my cores are
configured.

Thanks


Article: 126065
Subject: Re: Synthesis-place&route performance test.
From: Jan Pech <no@spam.please>
Date: Wed, 14 Nov 2007 10:32:48 +0100
Links: << >>  << T >>  << A >>
On Tue, 2007-11-13 at 16:41 -0800, posedge52@yahoo.com wrote:
> I would like to find out how well different system setups performs
> when it comes to Synthesis, Place & Route with Xilinx ISE tools. I
> would like you to synth/place/route the source package below. And then
> reply with:
>   cpu type, cpu frequency,
>   ram type, ram size,
>   motherboard vendor/model,
>   operating system (uname -a),
>   total time used.
> 
> File:  http://filewebhosting.com/download.php?file=476Minimig1.tar.bz2
> 
> Tested on linux Xilinx ISE 8.1i.
> If you run any linux compatible system it's just to download and type:
>   bzip2 -dc Minimig1.tar.bz2 | tar -xvpf -
>   cd Minimig1
>   time make ; uname -a
> 
> The makefile might work in win32 enviroment (or use the gui).
> Even obsolete systems is of interest. To get more data on which
> factors that makes a performance difference.
> 

CPU: Intel Core2 Duo E6850, 3.00GHz
RAM: 4GB DDR2, 800MHz
MB:  GigaByte GA-P35-DS4 (Intel P35 + ICH9R)
OS:  Fedora 7, 2.6.23.1-21.fc7, x86_64

$ time make
real    3m46.928s
user    3m36.843s
sys     0m1.245s


Jan



Article: 126066
Subject: VCD Files Viewer?
From: Heinrich Burgsteiner <Heinrich255@yahoo.com>
Date: Wed, 14 Nov 2007 10:39:57 +0000
Links: << >>  << T >>  << A >>
Hello

I just generated with modelsim a VCD file and I wonder if it is possible 
to view this VCD file with modelsim? I tried to open it but I got the 
error message:

# WLF Error: File is not a WLF file: vcd.dump
# Cannot open file: vcd.dump

Unfortunately I cant install gtkwave on my machine, because I dont have 
root rights. Is there any other simple tool that I could use under Linux?

Cheers
Heinrich

Article: 126067
Subject: Re: VCD Files Viewer?
From: Jan Pech <no@spam.please>
Date: Wed, 14 Nov 2007 12:35:25 +0100
Links: << >>  << T >>  << A >>
On Wed, 2007-11-14 at 10:39 +0000, Heinrich Burgsteiner wrote:
> Hello
> 
> I just generated with modelsim a VCD file and I wonder if it is possible 
> to view this VCD file with modelsim? I tried to open it but I got the 
> error message:
> 
> # WLF Error: File is not a WLF file: vcd.dump
> # Cannot open file: vcd.dump
> 
> Unfortunately I cant install gtkwave on my machine, because I dont have 
> root rights. Is there any other simple tool that I could use under Linux?
> 
> Cheers
> Heinrich

Convert your VCD to WLF using vcd2wlf tool from ModelSim.
Rgrds,
Jan


Article: 126068
Subject: Re: Synthesis-place&route performance test.
From: Andreas Hofmann <ahnews@gmx.net>
Date: Wed, 14 Nov 2007 13:15:45 +0100
Links: << >>  << T >>  << A >>
I saw runtime differences up to 1 minute when I implement the design
multiple times. Each implementation was run on a freshly unpacked
project directory. Maybe this is due to your design not meeting timing.

CPU: Intel Core2 Duo E6600, 2.40GHz
RAM: 2GB DDR2, 667MHz
MB:  ASRock ConRoe 945G-DVI(Intel 945G + ICH7)
OS:  Ubuntu 7.10, 2.6.22-14-generic, i686

ISE 9.1.03i (design did not meet timing)
real    5m33.115s
user    5m31.925s
sys     0m1.080s

real    4m25.734s
user    4m24.641s
sys     0m1.004s

Article: 126069
Subject: Re: VCD Files Viewer?
From: Heinrich Burgsteiner <Heinrich255@yahoo.com>
Date: Wed, 14 Nov 2007 12:47:38 +0000
Links: << >>  << T >>  << A >>

> Convert your VCD to WLF using vcd2wlf tool from ModelSim.
> Rgrds,
> Jan

Thanks Jan, works fine ;)


Article: 126070
Subject: grouping bits to form bus in VCD file
From: Heinrich Burgsteiner <Heinrich255@yahoo.com>
Date: Wed, 14 Nov 2007 12:56:28 +0000
Links: << >>  << T >>  << A >>
Hi

I just have another issue. I try comparing the VCD files generated by 
Modelsim to a reference VCD file. Unfortuantely this is not working,
because the modelsim represents a 32-bit signal as 32 single bits 
whereas the reference VCD file treats the whole 32 bits as a bus.

So is there a way to group single bits in VCD to a single Bus?

Modelsim VCD has single bits

pipe.arc_fe_dc.fe_dc[31] Q+ from regr.vcd
pipe.arc_fe_dc.fe_dc[30] R+ from regr.vcd
....
pipe.arc_fe_dc.fe_dc[1] o+ from regr.vcd
pipe.arc_fe_dc.fe_dc[0] p+ from regr.vcd

Reference VCD looking for a bus of 32 bits and outputs error:
NO match pipe.arc_fe_dc.fe_dc[31:0]

Thanks,
Heinrich

Article: 126071
Subject: Re: VCD Files Viewer?
From: Guenter Dannoritzer <kratfkryksqq@spammotel.com>
Date: Wed, 14 Nov 2007 14:24:25 +0100
Links: << >>  << T >>  << A >>
Heinrich Burgsteiner wrote:
[...]
> 
> Unfortunately I cant install gtkwave on my machine, because I dont have
> root rights. Is there any other simple tool that I could use under Linux?

You don't have to have root rights to install software under Linux. It
is always possible to install software in your home folder. The
destination can usually be specified with the ./configure call.

However, especially with gtkwave and its dependency to gnome there might
be some dependency missing that you don't have installed. Which then
brings you in the same situation as before.

Cheers,

Guenter

Article: 126072
Subject: Xilinx Encrypted bit file
From: Amal <akhailtash@gmail.com>
Date: Wed, 14 Nov 2007 14:23:01 -0000
Links: << >>  << T >>  << A >>
I know Xilinx keeps its bit file header format secret.  But, does
anyone know how to detect if a bit file is encrypted or not?  As part
of our manufacturing builds, we need to make sure the bit file we are
choosing, is the encrypted file and not the regular bit file.

Maybe someone knows how to read and de-cypher the XIlinx bit file
header.  Or has a command-line tool to detect that.

Please let me know,
-- Amal


Article: 126073
Subject: FPGA for hobby use
From: Herbert Kleebauer <klee@unibwm.de>
Date: Wed, 14 Nov 2007 15:46:03 +0100
Links: << >>  << T >>  << A >>
A few month ago I asked for a recommendation for FPGA (not a ready to use demo board)
which could be handled with simple home equipment. I got the link to:

http://www.enterpoint.co.uk/moelbryn/darnaw1.html

We ordered a few samples and did some experimenting. Here the documentation
for a simple 16 bit CPU implemented on the DARNAW1. It includes also a step by
step introduction which should allow anybody still unfamiliar with FPGA design
to implement the demo in less than a hour.

ftp://137.193.64.130/pub/mproz/mproz3_e.pdf  (documentation)
ftp://137.193.64.130/pub/mproz/mproz3.zip    (documentation + schematics)

Conclusion: 
The board is great, not just an other demo board, but rather a package
converter from the FPG ball grid to a pin grid array with the necessary
voltage converters and program flash on board. Sadly the same can't be 
said about the current Xilinx software (schematic editor + simulator), 
so we will try to stay as long as possible with the X3000 chips and the
old Xilinx DOS software (with ViewLogic schematic entry + simulator).


Article: 126074
Subject: Re: FPGA for hobby use
From: cs_posting@hotmail.com
Date: Wed, 14 Nov 2007 07:07:49 -0800
Links: << >>  << T >>  << A >>
On Nov 14, 9:46 am, Herbert Kleebauer <k...@unibwm.de> wrote:

> Sadly the same can't be
> said about the current Xilinx software (schematic editor + simulator),
> so we will try to stay as long as possible with the X3000 chips and the
> old Xilinx DOS software (with ViewLogic schematic entry + simulator).

The real problem is your insistence on using schematic entry for
things of moderate complexity.

Learn a hardware description language and your life will be much
easier.





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