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Messages from 98200

Article: 98200
Subject: Internal pull down on the FPGA.....
From: "vssumesh" <vssumesh_asic@yahoo.com>
Date: 6 Mar 2006 22:35:18 -0800
Links: << >>  << T >>  << A >>
Hi all,
     I am facing a problem with my design. In which i assigned tri
state buffers to drive a bus which is connected to sixteen identical
blocks. This bus is controlling the register updation. But in the
default configuration when all blocks are driving high impedance to the
bus the bus is going to '1' state by internal pull up. I want to know
is there any way to pull down the internal signals in the Xilinx FPGA
(specifically Virtex 4 or Virtex E).
regards
Sumesh V S


Article: 98201
Subject: Re: Vccaux regulator
From: "Marco" <marco@marylon.com>
Date: 6 Mar 2006 23:37:26 -0800
Links: << >>  << T >>  << A >>
Thanks, so I could use the TPS54610 without the need for the shunt Rpar
resistor, right?
Marco


Article: 98202
Subject: Re: Pullup questions on Spartan3
From: "Marco" <marco@marylon.com>
Date: 6 Mar 2006 23:49:02 -0800
Links: << >>  << T >>  << A >>
Thanks, I'll go with external pullups, ok.
Marco


Article: 98203
Subject: Re: Internal Signals in OPB EMC In XIlinx PLatform studio
From: =?ISO-8859-1?Q?G=F6ran_Bilski?= <goran.bilski@xilinx.com>
Date: Tue, 07 Mar 2006 08:58:25 +0100
Links: << >>  << T >>  << A >>
sachink321@gmail.com wrote:
> HI
> how would i use internal signals in XPS for microblaze on spartan 3
> fpga board.
> 
> let me explain my project
> in opb_emc
> im using 2 memory banks
> so im having two Output enable signals
> but i have only one external pin
> so i need to AND these two output signals and produce a single output
> this output will be given to the external signal.
> 
> but i cant understand how can we produce a logic
> for these internal signals?
> 
> any ideaz
> 

Put a util_reduced_logic core in the .mhs

Göran

Article: 98204
Subject: Re: Power estimates in XC3S1500
From: "Marco" <marco@marylon.com>
Date: 7 Mar 2006 00:00:51 -0800
Links: << >>  << T >>  << A >>
Hi, the best way to estimate power consumption is through the XPower
tool within your ISE, starting from your vhdl/verilog design. Otherwise
should be hard, from my small experience, to get close-to-reality
results. However, for your XC3S1500 I would go also with, at least, 1A
for Vcco and Vccint, you can give something less only for Vccaux I
think. If it could help you, I'm making some test with an evaluation
board from Analog Devices (this has been done to extend the Blackfin
DSP features, but it can work alone as the other boards from Xilinx,
Avnet or so) equipped with a XC3S100. I have the schematic (or I can
give you a link, let me check) and you could take a look therein for
comparison.
Marco


Article: 98205
Subject: Re: Power estimates in XC3S1500
From: "Marco" <marco@marylon.com>
Date: 7 Mar 2006 00:05:30 -0800
Links: << >>  << T >>  << A >>
Here's the link
http://www.analog.com/processors/epManualsDisplay/0,2795,,00.html?SectionWeblawId=351&ContentID=87691&Language=English
Marco


Article: 98206
Subject: Re: why use an FPGA when a CPLD will do ??
From: "Thomas Stanka" <usenet_10@stanka-web.de>
Date: 7 Mar 2006 00:46:51 -0800
Links: << >>  << T >>  << A >>
Hi,

Simon Peacock schrieb:

> OK.. I admit there are a few minor players who have flash based or fuse
> based FPGA's.. but then they aren't by definition field Programmable are
> they?

Yes, for sure. Field programmable has nothing to do with
reconfiguration.

> They are in fact very large CPLD's as a FPGA is a Field Programmable Gate
> Array and Fuse devices aren't field programmable (or at least are only
> one-shot) FLASH devices could be considered field programmable... but some
> can't be used while a new program is getting uploaded.  So that excludes
> them from what I would call Field Programmable.

Ever tried to use a xilinx device while uploading them? If my memories
correct,  uloading with parallel port took over a minute for the first
Virtex.

Ok, my answer on your last posting was a bit short, because a similar
thread started in comp.lang.vhdl a few days ago :=). Sorry, should have
used a full answer.

Originaly you had CPLD with less registers and weak routing abilities
providing fast pathdelays against FPGAs with more registers and good
routing but slow path delays.

Nowadays you differ between CPLD and FPGA mostly by marketing. The big
CPLDs from Altera and Lattice are AFAIK FPGAs on a technological point
of view. It seems to me only marketing to call them CPLD (maybe some
customer are used to CPLDs and would never change to Fpga).

bye Thomas


Article: 98207
Subject: Re: Vccaux regulator
From: Allan Herriman <allanherriman@hotmail.com>
Date: Tue, 07 Mar 2006 20:21:19 +1100
Links: << >>  << T >>  << A >>
On 6 Mar 2006 23:37:26 -0800, "Marco" <marco@marylon.com> wrote:

>Thanks, so I could use the TPS54610 without the need for the shunt Rpar
>resistor, right?

Yes.

Allan.

Article: 98208
Subject: Re: A few questions about FPGAs
From: fpga_toys@yahoo.com
Date: 7 Mar 2006 02:07:45 -0800
Links: << >>  << T >>  << A >>

mahurshi@gmail.com wrote:
> I had two basic questions about FPGAs and I wanted to know what you
> guys thought about those:
>
> 1.  Are FPGAs mostly PALs and PLAs ?

Very different technology difference. PAL/PLA designs are normally
based on a fixed array of wire AND/OR functions.  FPGA's are normally
designed using lookup tables.  See the data sheets for the devices.

> 2.  For large designs, how is the timing analysis done on FPGAs?  Is it
> done using the libraries for the standard cells used or is it done only
> after the code is synthesized "for" the FPGA (which makes more sense)

It's normally done at several levels ... estimates of typical device
and routing delays early in the project, and using better detailed
numbers post place and route based on the actual finished design
resources used.


Article: 98209
Subject: Atmel using Xilinx FPGAs
From: "Leon" <leon_heller@hotmail.com>
Date: 7 Mar 2006 03:12:09 -0800
Links: << >>  << T >>  << A >>
Whilst reading the current issue of Atmel's Applications Journal I was
intrigued to see that they are using Xilinx FPGAs in their SOC
emulation platform, instead of their own devices.

Leon


Article: 98210
Subject: Xilinx LVDS
From: hakan.sakman@gmail.com
Date: 7 Mar 2006 03:12:57 -0800
Links: << >>  << T >>  << A >>
Hi,

I want to findout the minimum accepted voltage difference for LVDS in
Xilinx Spartan3 FPGAs. For example is 40mV acceptable?

Many thanks for the help in advance..

H aka N


Article: 98211
Subject: Re: Xilinx LVDS
From: "Marco" <marco@marylon.com>
Date: 7 Mar 2006 03:28:39 -0800
Links: << >>  << T >>  << A >>
Hi, I think it is, as you can see from table 21 on page 23 of DS099-3
(Spartan3 datasheet), LVDS low input is (Vicm - 0.125), while LVDS high
is (Vicm + 0.125), so the difference is 25mV.
Marco


Article: 98212
Subject: Re: Xilinx LVDS
From: "Marco" <marco@marylon.com>
Date: 7 Mar 2006 03:32:00 -0800
Links: << >>  << T >>  << A >>
Sorry for the mistake, it's 250mV!


Article: 98213
Subject: Re: Xilinx LVDS
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 7 Mar 2006 11:32:00 -0000
Links: << >>  << T >>  << A >>
<hakan.sakman@gmail.com> wrote in message 
news:1141729977.923850.43780@e56g2000cwe.googlegroups.com...
> Hi,
>
> I want to findout the minimum accepted voltage difference for LVDS in
> Xilinx Spartan3 FPGAs. For example is 40mV acceptable?
>
> Many thanks for the help in advance..
>
> H aka N
>
Did you try looking in the datasheet? Search for Vid.
HTH, Syms. 



Article: 98214
Subject: Re: Xilinx LVDS
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 7 Mar 2006 11:41:09 -0000
Links: << >>  << T >>  << A >>
"Marco" <marco@marylon.com> wrote in message 
news:1141730919.700121.50560@v46g2000cwv.googlegroups.com...
> Hi, I think it is, as you can see from table 21 on page 23 of DS099-3
> (Spartan3 datasheet), LVDS low input is (Vicm - 0.125), while LVDS high
> is (Vicm + 0.125), so the difference is 25mV.
> Marco
>
Marco,
You might want to read that again. You're reading the table headed 'Test 
Methods for Timing Measurement at I/Os'. Perhaps the table 'Recommended 
Operating Conditions for User I/Os Using Differential Signal Standards' 
might be more applicable? And also, I suggest a little more practice at 
arithmetic. Or typing. 250mV is what you were looking for? ;-)
HTH, Syms. 



Article: 98215
Subject: Re: Atmel using Xilinx FPGAs
From: "Antti" <Antti.Lukats@xilant.com>
Date: 7 Mar 2006 03:51:22 -0800
Links: << >>  << T >>  << A >>
sure!

Atmel has only very small FPGA's itself, those are not suitable for SoC
system emulation

Antti


Article: 98216
Subject: Re: Terminologie/knowledge issu
From: Aurelian Lazarut <aurash@xilinx.com>
Date: Tue, 07 Mar 2006 12:13:00 +0000
Links: << >>  << T >>  << A >>
thomas.b36@gmail.com wrote:
Thomas,

most of the time "low level" means "at the bit level" and I think has 
more to do with the vhdl/verilog (hardware description languages) but in 
the same time, sometimes "low level" is used in the software land for 
(low level) drivers where C language can come into play. Some companies 
are using the FPGA not only as a prototype/verification vehicle, but for 
development of drivers, well in advance of the silicon tape out.

Not sure what you mean by "C" against "functional C"

Aurash

> Hi all,
> 
> What's that mean : "Low Level Verification of ASIC Soc"?. The SoC
> should be tested on development board containing FPGA, CPU and so. In
> this cas how would you proceed using C programming?. Do one need to be
> proficient in C prog or just fonctional C will do?.
> 
> Thank for your precious time Gentlemans and Ladies.
> 
> Thomas.
> 


Article: 98217
Subject: Re: Simulation of Xilinx Rocket IO
From: Sean Durkin <smd@despammed.com>
Date: Tue, 07 Mar 2006 13:21:45 +0100
Links: << >>  << T >>  << A >>
kedarpapte@gmail.com wrote:
> yes Modelsim SE has the swift model support, I am using that
> 
> but I am not able to get how  do I get this smart or swift models....?
> I tried everything which is listed on xilinx web site.
> but couldn't get it worked.
> 
> Please give me some info if you have it...
> 
See here:

http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=14019

and here:

http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/sim/sim0061_9.html

Last time I tried this, all I had to do was compile the libraries with
compxlib as described in the second link above, then change my
modelsim.ini as described in the first link above (i.e., set the
simulation resolution to ps, include the SWIFT-dll and so on).

Note: if you have ModelSim-Project-Files, the setting for the simulation
resolution in modelsim.ini is overridden.

What I'm not sure about is wether the SmartModels are shipped with
WebPack at all. Could be they only come with the full ISE-release, don't
know...


cu,
Sean

Article: 98218
Subject: Re: Simulation of Xilinx Rocket IO
From: "MM" <mbmsv@yahoo.com>
Date: Tue, 7 Mar 2006 07:37:02 -0500
Links: << >>  << T >>  << A >>
Kedar,

On the Xilinx web site go to Support/Download Center and then choose ISE
SmartModels. I believe it is included there, otherwise I don't remember
where I got it... With regards to getting it working I have some code
demonstrating it, which I could dig up if you want, but it was run under
Active HDL, not Modelsim...

/Mikhail


<kedarpapte@gmail.com> wrote in message
news:1141708464.611156.52840@j33g2000cwa.googlegroups.com...
> yes Modelsim SE has the swift model support, I am using that
>
> but I am not able to get how  do I get this smart or swift models....?
> I tried everything which is listed on xilinx web site.
> but couldn't get it worked.
>
> Please give me some info if you have it...
>
> Thanks & Regards,
> Kedar
>



Article: 98219
Subject: Re: Xilinx LVDS
From: hakan.sakman@gmail.com
Date: 7 Mar 2006 05:21:33 -0800
Links: << >>  << T >>  << A >>
Thanks all for your time,

I looked at the data sheet (didn't know where to look at, a search on
LVDS didn't help, so many tanks for the directions) and as far as I can
see its min 100mV and max 600mV..

Best

H aka N


Article: 98220
Subject: Xilinx ISE8.1 & MIG1.5 crash
From: peter <ask@me.de>
Date: Tue, 7 Mar 2006 05:45:21 -0800
Links: << >>  << T >>  << A >>
hello all, I just downloaded Xilinx ISE8.1 and Memory Interface Generator MIG1.5. I selected a DDR2-Sodimm to implement in a Virtex4. MIG1.5 generates a complete synthesizable testbench and the batch file "ise_flow.bat" When I start the batch file all works fine till xilinx map tool stops with an internal error: FATAL_ERROR:Map:Portability/export/Port_Main.h:127:1.24. Is there anybody with same problem on MIG1.5 thanks for help peter

Article: 98221
Subject: Re: Xilinx ISE8.1 & MIG1.5 crash
From: "Antti" <Antti.Lukats@xilant.com>
Date: 7 Mar 2006 06:00:30 -0800
Links: << >>  << T >>  << A >>
there is on very sad thing, namly as soon as you get

... Portability ... 127

error means that you need to wait for next service pack or quickpatch.

its generic error and doesnt give any hint what is actually wrong.
like a generic root of all devil by xilinx software.

the same main.h:127 just keeps coming, in each major release, in each
service pack
:(

Antti
PS if you need to quick test DDR2 then EDK 8.1 SP1 has DDR2 and that
does pass synthesis at least, no crash, havent tested the hardware if
it works also though.


Article: 98222
Subject: Re: A few questions about FPGAs
From: "selva kumar" <vkmselva@gmail.com>
Date: 7 Mar 2006 06:11:20 -0800
Links: << >>  << T >>  << A >>
hi,

FPGAs are mostly made of both PLAs and PALs .
FPGAs timing analysis is done after the code is synthesized.
we dont do timing analysis using standard cells for FPGAs.we do timing
alalysis in fpga only for the code.
in fpga the design is already freezed,so we cannot do timing alalysis
using standard cells.

regards
selva
bangalore

mahurshi@gmail.com wrote:
> I had two basic questions about FPGAs and I wanted to know what you
> guys thought about those:
>
> 1.  Are FPGAs mostly PALs and PLAs ?
>
> 2.  For large designs, how is the timing analysis done on FPGAs?  Is it
> done using the libraries for the standard cells used or is it done only
> after the code is synthesized "for" the FPGA (which makes more sense)
> 
> 
> Mahurshi Akilla


Article: 98223
Subject: Re: bscan_virtex4 device
From: Frank van Eijkelenburg <someone@work.com>
Date: Tue, 07 Mar 2006 15:17:08 +0100
Links: << >>  << T >>  << A >>
Antti wrote:
> jtag instruction codes can be found in BSDL files
> your tcl script selects USER1 (instance with jtag_chaine=1) and send
> data to user logic
> 
> basically all your assumptions seem correct
> 
> I do use the BSCAN and user logic implemented custom jtag chains all
> the time, but from our own jtag component library so I can not tell if
> your tcl code should actually work, it seems like it might
> 
> antti
> 

I am testing with the next script:

========================================
source c:/xilinx_7_1/ChipScope_Pro_7_1i/tcljtag.tcl

set handle [jtag_open]
jtag_lock $handle
jtag_autodetect $handle

puts stderr "JTAG information"
puts stderr "================"
puts stderr "Number of devices in the chain: [jtag_devicecount $handle]"
puts stderr "IR Length of device 1 is [jtag_irlength $handle 1]"

set oldir1 [jtag_shiftir $handle -buffer "01000011111111" -endstate RTI -device 1]
puts stderr $oldir1

set oldir2 [jtag_shiftir $handle -buffer "11000011111111" -endstate RTI -device 1]
puts stderr $oldir2

set oldir3 [jtag_shiftir $handle -buffer "01000111111111" -endstate RTI -device 1]
puts stderr $oldir3

set oldir4 [jtag_shiftir $handle -buffer "11000111111111" -endstate TLR -device 1]
puts stderr $oldir4

jtag_unlock $handle
jtag_close $handle

========================================
I expected a different output for oldir1, 2, 3 and 4. But they are all equal:

JTAG information
================
Jtag_DeviceCount succeeded
Number of devices in the chain: 4
Jtag_IRLength succeeded
IR Length of device 1 is 14
Jtag_ShiftIR successful
10101111111111
Jtag_ShiftIR successful
10101111111111
Jtag_ShiftIR successful
10101111111111
Jtag_ShiftIR successful
10101111111111
Jtag_Unlock succeeded
Jtag_Close successful

Could you give an explanation for this? How should I deal with the endstates? I want to shift the usercode instruction to the instruction register and 
after that shifting my own 16 bits data into the data register.

Does anybody has some example code for this? My jtag chain exists of 4 devices and device 1 (counting from 0) is the device I want to use.

I can't find much information on the internet, is this not commonly used?!

TIA,
Frank

Article: 98224
Subject: Re: Internal pull down on the FPGA.....
From: "motty" <tlassiter@rfmd.com>
Date: 7 Mar 2006 06:22:58 -0800
Links: << >>  << T >>  << A >>
You can put a PULLDOWN directive in the UCF for those pins.  Check out
the Constraints Guide, I think.  Or search for PULLDOWN on the website.
 There is also a default setting in one of the files if you are using
the EDK.  I think it has to do with bitgen options.  I can't remember
exactly where that file is though.  Sorry!  Alternately, you can put an
attribute in your HDL.  There are multiple ways to do it.

Good luck.




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2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
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2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

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