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Hi! I am looking for detailed information on implementation of multipliers on AT&T's ORCA. Please post the information on this newsgroup or email me at kadamby@caip.rutgers.edu Thanks! -VijayArticle: 1626
We are currently designing a double sided PCB for our Enable++ project. This machine is a universal FPGA processor. Its FPGA-Matrix consists out of 16 XC4013 FPGAs (240 pin QFP-cases with 0.5mm pitch), 8 I-Cube I240 FPIDs (304 pin QFP-cases with 0.5mm pitch) and 96 synchronous SRAMs. There are 11 more XC4005H (240 pin QFP) and 16 dual-ported-RAMS on the board as IO-Interface and control logic. Since any I-Cube FPID is connected to almost any FPGA there are some 4000 nets which connect all parts to some hypercube topology. This looks like quite a mess. Since we want to operate the board up to a clock of 50MHz and no correct termination of lines is possible (Xilinx won't drive the termination currents!) we tried to place SMDs on both sides of the board to keep lines short: this works but involves some extreme problems with routing without beeing to advantageous! This fact has a simple explanation. If there is no topology which allows to connect most of the pins of two QFPs which are located side by side on the outer layer then one via is needed for every pin to connect the SMD pad to the inner layers. The smallest possible via has a drill diameter of about 0.4mm (for a 20 layer board with 360x400mm size) and a minimal spacing of 1.0mm (There is not much to optimize on these figures if you don't have plenty of money and an extremely good and willing PCB manufacturer!). Spacing is needed between the vias to get through with at least two lines which computes to a typical via grid of about 1.8 to 2.0mm. Calculating the free area under a 240 or 304 pin QFP it comes out that there is enough space to fanout every pin inside the case area. And this is exactly what a good autorouter like Specctra will do: it converts the SMD-case into a virtual PGA- or BGA- (Ball Grid Array) like structure. This works perfectly with Specctra for single sided boards. Since the area inside is not sufficient for two SMDs placed on both sides of the board top on top the router has to use the outside area, too. And here trouble starts: First SMDs can't be placed any longer end to end. Plenty of room is lost and actually there is no area gain of 2.0 but only 1.2-1.5 or something like that. Secondly no via under the SMDs can be used as a test point. It is extremely difficult to perform tests with a logic analyzer or a scope on fine pitch SMDs directly but it is easy to solder a little test pin to a via! The third point is about power/ground lines. In the single sided version decoupling capacitors can be placed directly under the QFP pads, there is no space for this if a double sided board is used. It is recomended that QFPs are connected with the shortest possible lines to the power/ground-layers. The Specctra router is definitely not capable of this for double sided designs. Since it has to use both directions for fanout, inside and outside, it will put power-ground vias very close to the pads in the first step. After this the power-ground configuration has to be protected, the router isn't allowed any longer to shift any vias or lines. But then some pads can't be reached any more with lines without violating design rules. In the end there were some 100-200 errors of this kind on our board. The only possibility left was to place power/ground vias by hand. This took us a whole week but worked perfectly. Conclusion: there is not much to gain by double sided placement of fine pitch QFPs. One should use it only if it can't be avoided. This is at least my personal feeling about it and I believe it to be definitely valid for some globally connected circuit topologies. It is definitely wrong for designs with local connections of some symmetry. If there are further questions I will be glad to answer them. Jozsef Ludvig Lehrstuhl fuer Informatik V Universitaet Mannheim e-mail: ludvig@mp-sun1.informatik.uni-mannheim.deArticle: 1627
In article <3vpuc5$4b6@wsiserv.Informatik.Uni-Tuebingen.De> schmidt@ti-ibm06.informatik.uni-tuebingen.de (Marco Schmidt) writes:
>From: schmidt@ti-ibm06.informatik.uni-tuebingen.de (Marco Schmidt)
>Subject: Re: 16 bit computer on fpga's
>Date: 3 Aug 1995 07:37:41 GMT
>Peet Badenhorst (pbadenh@firga.sun.ac.za) wrote:
>: About a month ago I think I read about somebody that built a complete 16
>: bit processor with vga display and keyboard driver in 4 Xilinx FPGA's.
>: It came with GIF's showing the casing and layout. I seem to have lost the
>: files.
>: Can somebody please point me in the right direction?
>: Please e-mail me at pbadenh@firga.sun.ac.za
>: Thanks Peet
>please post !
>Thanks.
>Marco
It is not only a processor, it is a complete computer.
You can download the following files (and some gifs) from:
mistress.informatik.unibw-muenchen.de /pub/xproz
Only xproz.txt is in English, all other is in German.
xproz.zip : Documentation (Word for Windows) and schematics (WORKVIEW)
for a computer built with only 4 XILINX FPGA's
1. FPGA: 16 bit CPU (XILINX 3090 FPGA)
- 128 kByte memory-address
- 128 kByte i/o-address
- 5 Interrupt levels
- 3-address instructions
- 0.3 MIPS
2. FPGA: graphics controller (640x400)
3. FPGA: RS232, parallel port
4. FPGA: keyboard interface, SCSI controller, timer
xproz_ps.zip: Documentation and schematics in postscript format
xass.zip: Assembler for the 16 bit cpu
xmos.zip: Multitasking operating system
xproz.txt: short ascii description of the 16 bit CPU
Herbert Kleebauer
Article: 1628Hi fellow FPGAers I'm a fairly new user of Xilinx FPGAs. I'm having a few problems with my current design using a Xilinx xc4013 FPGA. With only around 84% CLB utlilzation and under 40% flip-flop utilization, the XACT software is crashing on routing. It always ends up with 70 unroutes. I'm sure I'm not pushing it to more than available routing resources when the CLB utilization is not filled. Handrouting all the signals is the last thing that I'm opting for. Any help is well appreciated _ Masood Makkar _ email :- makkarm@ipoint.vlsi.uiuc.eduArticle: 1629
Due to popular demand, I am posting the VHDL and Neocad hard macros for the
5x5 image convolver design implemented in an ORCA 2C04 FPGA. It uses a
pretty damn fast system clock of 80 Mhz. It needs a little more work in the
coefficient department, because the lookup tables don't have a 1 to 1
correspondence with the filter taps, but need to be generated by a utility
program from the filter taps. I haven't gotten around to writing the
utility yet... (uuencoded, gzipped tar file follows at bottom of this post.)
Now that I've paid my usenet dues by posting something semi-useful, I'd like
to mount my soapbox and launch a stupid question or two.
Here's a question for the VHDL experts. I really like using functions
and procedures in VHDL, probably because it's more "C" like and I find it
easier to hide complexity in something that looks like a function call.
BUT, there doesn't seem to be any simple mechanism to instantiate technology
specific hardware such as RAM cells in a procedure or function. I'd like to
define a common set of procedures with different body definitions for each
technology targeted, and use a procedure in the main entity to invoke a
technology specific component (the dreaded hard macro instantiation). The
sad fact is that no VHDL compiler will synthesize the odd technology cells
like RAMS.
Everyone is familiar with the typical dff() procedures that make it easy to
instantiate registers, but it seems to be absolutely forbidden to invoke a
component inside a procedure. Even if it is something as simple as a 1 to 1
mapping of signals from the procedure arguments to an instantiated component,
you can't do it, because procedures are sequential environments. (Is this
in the LRM?)
Even cheating and using a C preprocessor to expand predefined macros into
1 to 1 component instantiations doesn't work, since each one needs a
unique component label. Humphhh!
The upshot is that synthesizeable VHDL code sprinkled with technology
specific cell instantiations is non-portable, and difficult to simulate.
Does anybody have a better idea?
John McCluskey
J.McCluskey@ieee.org
-----------------------------cut here-------------------------------
begin 644 convolver.tar.gz
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`
end
Article: 1630husby@fnal.gov (Don Husby) writes: >Has anyone found a way to use the register input mux without having to make a >macro? (Using NeoCad 6.1.1 software). well, I have NeoCad 7.0, along with the latest ORCA viewlogic symbol libraries, and there don't seem to be any symbols in the library that use the register input muxes. A macro is the only way I have found so far. See the acc8 macro in my other post on the 5x5 image convolver. It saves a lot of hardware when you need to reset the accumulator flip flops to the new incoming value. John McCluskey J.McCluskey@ieee.orgArticle: 1631
Chuck Gollnick x196 (chuckg@arnet.com) wrote: : In <3v33ki$1328@usenetw1.news.prodigy.com> CQEM17A@prodigy.com (Jeff Wetch) writes: : >Net criticality can be done in Mentor by selecting the net in the : >schematic : >and adding a property. The property name is ALSCRT : Of course. That's exactly what I would have named that property. NOT! : Why not CRITICALITY? : Chuck Gollnick : Arnet -------------------------------------------------------- It is actually a good idea to name application specific properties with obscure names. If you pick common names then you run into all sorts of problems when you use the same capture system with other venders using the same names. John EatonArticle: 1632
n article <makkarm.807843146@ipoint> you wrote: >Hi fellow FPGAers > >I'm a fairly new user of Xilinx FPGAs. >I'm having a few problems with my current design using a Xilinx xc4013 >FPGA. With only around 84% CLB utlilzation and under 40% flip-flop >utilization, the XACT software is crashing on routing. It always ends up >with 70 unroutes. > >I'm sure I'm not pushing it to more than available routing resources when >the CLB utilization is not filled. > >Handrouting all the signals is the last thing that I'm opting for. > >Any help is well appreciated That is a very high usage for a 4013. It would be more confortable around 60 to 65%. You are probably going to have to do much more work than you would have wanted to. Are the pins frozen? If not you have a better chance. Can you shrink the logic? This would help alot. You could see if Xilinx would let you try the NeoCAD software. This may work better on this particular design. You should look into floor planning the design. This means making modules out of your logic and hand placing the modules. The next release of the XACT system will have floor planning biult in. Good luck, Tom Dillon DILLON ENGINEERING 2017 Continental Place Suite 5 Mount Vernon, WA 98273-5649 e-mail: tom@dilleng.wa.com Voice : (360) 424-3794 FAX : (360) 424-5894Article: 1633
Some weeks ago, a CFP has been posted in news.announce.conferences. Seems that I have lost it. Anybody out there knows where to get information on this event or who might even provide the CFP to me? Thanks a lot. -- ----------------------------------------------------------------------- Andre' Klindworth Universitaet Hamburg, FB Informatik klindwor@informatik.uni-hamburg.de Vogt-Koelln-Str.30, D-22527 Hamburg Phone: +49 40 54715-501, Fax: -397 GermanyArticle: 1634
makkarm@ipoint.vlsi.uiuc.edu (Masood Makkar) wrote: >Hi fellow FPGAers > >I'm a fairly new user of Xilinx FPGAs. >I'm having a few problems with my current design using a Xilinx xc4013 >FPGA. With only around 84% CLB utlilzation and under 40% flip-flop >utilization, the XACT software is crashing on routing. It always ends up >with 70 unroutes. > >I'm sure I'm not pushing it to more than available routing resources when >the CLB utilization is not filled. > >Handrouting all the signals is the last thing that I'm opting for. > >Any help is well appreciated Hi, One of the reasons XACT ends up with unrouted signals, is the name of the nets; if you give different names to the nets that are supposed to be the same net (i.e connected to each other), then each net having a different name will be considered as different and will not be connected to each other. Some schematic tools warn you, but some do not. If you are entering your design by using an HDL, HDL compilers (at least the ones that I used) warn you as well. So, if you are using a schematic tool, you might want to check your design once more against this kind of a problem. If you don't have such a connectivity problem, then you might try to optimise your design, and give constraints (placer_effort, router_effort) to the router. You might also try using a XC4025. If it fits and Xact generates no "unroutes", then I think you must check again if the available resources (number of global buffers, IO count, CLB resources) of XC4013 is sufficient for your design. If the problem remains, then either the design is really big, or ... (I don't know) Good luck, Yuce Beser.Article: 1635
Andre Klindworth (klindwor@tech17.informatik.uni-hamburg.de) wrote:
: Some weeks ago, a CFP has been posted in news.announce.conferences.
: Seems that I have lost it. Anybody out there knows where to get
: information on this event or who might even provide the CFP to me?
Hello Andre',
take a look at
http://www.cs.washington.edu/research/projects/lis/www/fpga96/
There you will find the CFP.
Markus
------------------------------------------------------------------------------
@@ @@ Markus Wannemacher
@@@ @@@ @@@@@@ @ @ FernUniversit"at Hagen
@@@@ @@@@ @ @@@ @ @ LG Informationstechnik
@@@@ @@@@ @@@@ @@@@ @ @ @ @ LGZ, Profilstr. 10b
@@@ @@@@ @@@ @ @@@@@ @ @ D-58084 Hagen, Germany
@@@@@@@@@@@@ @ @ @ @ phone +49 2331 987 4547
@@@@@@@@@@ @ @@@ @@@@ fax: +49 2331 987 375
Internet: E-Mail: Markus.Wannemacher@FernUni-Hagen.De
WWW: html://www.fernuni-hagen.de/www2bonsai/IT/team/wm.html
--------------------------------------------------------------------------------
Article: 1636
Here's even more fun e-mail I've recieved concerning the dog food drive for
Joe Costello! :^)
- John Cooley
the ESNUG guy
From: gunes@jadeite.Eng.Sun.COM (Gunes Aybay)
>Dear John,
>
>Please help advance my career. Six weeks ago my company, Sun Microsystems,
>started a new advertising campaign based around a short haired St. Bernard
>named "Network" as being our new corporate mascot. (The ads have been in
>the business press to target MIS managers.) "Network" is supposed to be
>Scott McNealy's (CEO of Sun Microsystems) dog.
>
>I grew up in Turkey. To me, St. Bernards are the dogs used for search and
>rescue operations on European mountains to find buried skiers. In cartoons,
>they're sometimes seen as drunk because they're drawn carrying small barrels
>of liquor under their collars. (What this has to do with networking I don't
>understand. I asked my co-workers & none of them associate networking with
>St. Bernards or any other dogs either. They just know that the people
>upstairs like it and that's what counts!) Inside Sun, they have a bulletin
>board with critical info like how much "Network" weighs and a message of the
>day like: "Today it was hot. Network drank a lot of water." They even put
>his dog house in front of Sun's headquarters for a while -- until they moved
>it in front of the company cafeteria. (Is this a good sign about our
>cafeteria food, John? No one here will talk about this.)
>
>John, here is how you can help me. Please take all the *gourmet* dog food
>you get from your dog food drive for Joe Costello and ship it to my CEO,
>Scott McNealy, here in California. (I'll pay for shipping.) Please add the
>following *handwritten* note:
>
> "Dear Scott,
> One of your best designers, <unreadable name>, thought you'd
> love this gourmet dogfood for Network!
> - John Cooley"
>
>When Scott phones you to find out who the unreadable name is, if he seems
>happy, tell him: "Oh, that was my good friend Gunes Aybay! Gunes Aybay is
>not only a joker, Gunes Aybay is one of your best designers! You should give
>Gunes Aybay a raise and a promotion in my opinion, Scott!" BUT, IF HE SEEMS
>ANGRY, quickly tell him: "I can't remember who wanted me to send you the dog
>food. I'm really busy now. Can't talk. Gotta go!"
>
> - Gunes Aybay
> Sun Microsystems
>
>P.S. It's OK to publish this letter on Internet. Half of Sun's management
>is busy walking "Network" around the building and the other half are on
>"pooper scooper" duty. They won't have time to find this on Internet! :^)
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 3661 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 1637Suppose I have an FPGA (xilinx 4005 specifically) with a 32 bit data path entering and a 16 bit data path exiting. Data enters, is "processed" and then exits. The processing is nothing more than a few pipelined registers and perhaps some bit shifting and masking. Would the internal routing of the design be more efficient if the external connections were very regular (i.e. 16 IPADs clustered near each other and 16 OPADs clustered near each other) or irregular (PADs just "randomly" placed all around the chip). The regular case certainly has advantages that dataflow might be able to be kept moving in just one dimension but I wonder if the noisy nature of the irregular case is good enough to overcome whatever problems the regular case implies in terms of local shared resource contention etc. Has anyone look at or thought about this problem? Thanks. -George george@cmf.nrl.navy.milArticle: 1638
>> husby@fnal.gov (Don Husby) writes: >>> anyone found a way to use the register input mux without having to make a >>> (Using NeoCad 6.1.1 software). >well, I have NeoCad 7.0, along with the latest ORCA viewlogic symbol libraries, >and there don't seem to be any symbols in the library that use the register >input muxes. A macro is the only way I have found so far. See the acc8 macro >in my other post on the 5x5 image convolver. It saves a lot of hardware >when you need to reset the accumulator flip flops to the new incoming value. >John McCluskey >J.McCluskey@ieee.org ARGHH! What a moron I am! 5 minutes of looking at the AT&T ORCA Macro library (version 3.0) would have revealed the existence of a whole class of flip flops that invoke the input multiplexers on the flip flops. Page 2 of the manual (which is available by FTP as a postscript file from ftp://orca.fast.net/orca/viewlogic/viewlogman.ps.Z) sez: Table 5-1 Flip-Flop/Latch naming conventions (name = abcdef) a= F - Static implementation b= D - D type flip flop J - J/K type flip flop L - Cells contain a positive select front end (loadable) N - Cells contain a negative select front end (loadable) S - R-S type flip flop T - Toggle typ flip flop c= Value - Number of clocks d= This parameter identifies the enable capability S - no enable input P - Positive level enable N - Negative level enable e= This parameter identifes the clock capability 1 - Positive level sense (latch) 2 - Negative edge triggered (flip flop) 3 - Positive edge-triggered (flip flop) 5 - Negative level sense (latch) f= A - No clear or preset inputs B - Positive level asynchronous preset D - Positive level asynchronous clear E - Negative level asynchronous clear G - Negative level asynchronous preset I - Positive level synchronous clear J - Positive level synchronous preset L - Negative level synchronous preset M - Negative level synchronous clear X - Standard library element where GSR asynchronously clears or presets the flip flop depending upon the function of the local clear or preset. If no local clear or preset is present (f=A) then GSR clears the register. Y - Element is preset using GSR rather than cleared Z - Element not compatible with similar elements available in the standard cell library. ------------------------------------------------------------- So, a positive edge triggered flip flop with a positive level select input mux and positive enable input would be encoded as FL1P3AZ (the Z is tacked on to indicate that there is no direct equivalent in the standard cell library. There: I've corrected myself. John McCluskey J.McCluskey@ieee.orgArticle: 1639
Repost of the VHDL convolver. CNEWS seems to have munched the
first posting. Second attempt is via Mosiac...
John McCluskey
J.McCluskey@ieee.org
-----------------------------cut here-------------------------------
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`
end
Article: 1640
If one were to implement an ISA interface (for example) which includes an
IOW- signal with lots of data setup and hold prior to/following the
rising edge, which would be the prefered implementation of a write
register.
o - Use a system clock (BCLK at 8Mhz), synchronise IOW- through 3
D-types to produce a one clock period signal which one AND's with
a Register Select signal to produce Clock Enable which is presented
to the register to be written along with the system clock and the
data.
OR
o - Use the IOW- signal as the register clock and the Register Select
signal as the Clock Enable.
I realise that the purist (synchronous) solution is the first method but
what are the drawbacks to the second method. The advantages are that I
can latch data in an ISA short cycle (92nS) whereas the first solution
requires 3 clock cycles (360nS @ 8MHz) resulting in an ISA standard
cycle (530nS). The design will be implemented in a Xilinx 52xx.
-- Alan
Article: 1641You'll need to use a hard macro to utilize the front-end 2-1 MUXes on ORCA PFU registers. This is true for both versions 6.1.1 and 7.0 of Foundry. AT&T is working on enhancing the technology mapper to automatically take advantage of this hardware. Fred Koons AT&T MicroelectronicsArticle: 1642
aweir@onsys.com (Alan Weir) writes: >If one were to implement an ISA interface (for example) which includes an >IOW- signal with lots of data setup and hold prior to/following the >rising edge, which would be the prefered implementation of a write >register. I think you are trying to make a I/O Port type interface. If so take a look at Eggebrecht's book: Interfacing to the IBM Personal Computer from Sams Publishing. It show a very simple interface which could easily be implemented in a FPGA or PALs (it's shown in 74 TTL). The interface does not use the system clock. I have built the interface and have used it without any problems, I may have a PS file laying around of the one I made. I built it with TTL. -- ******************************************************************************* * Daniel L. Moore mooredan@uiuc.edu * * University of Illinois at Urbana-Champaign -- College of Engineering * *******************************************************************************Article: 1643
We have designs using the XC4003 and have tested and perfected (to a limited extent ;) ) our design. We have heard that it is possible to take the bitstream for the XC4003 and write it to a Xilinx EPLD. Is this for real? We sure could use such an option, since it would help immensely with our final design. Alan Guyer aguyer@eecs.wsu.edu Engineering Tech II Washington State UniversityArticle: 1644
jbm@j2mont.jtechmont.login.net wrote: > Page 2 of the manual (which is available by FTP as a postscript file from > ftp://orca.fast.net/orca/viewlogic/viewlogman.ps.Z) sez: I found this file, but it didn't have anything remotely resembling the text you gave here. ??Article: 1645
fjk@nozone.cnet.att.com wrote: > You'll need to use a hard macro to utilize the front-end 2-1 MUXes on > ORCA PFU registers. This is true for both versions 6.1.1 and 7.0 of > Foundry. AT&T is working on enhancing the technology mapper to > automatically take advantage of this hardware. What is the deal with version 7.0? Has AT&T released a version 7.0 of NeoOrca? How can I get an upgrade from my NeoCad 6.1?Article: 1646
In Article <DD299t.ILH@serval.net.wsu.edu>
aguyer@eecs.wsu.edu (Al Guyer) writes:
>We have designs using the XC4003 and have tested and perfected (to a
>limited extent ;) ) our design. We have heard that it is possible to
>take the bitstream for the XC4003 and write it to a Xilinx EPLD.
>
>Is this for real? We sure could use such an option, since it would
>help immensely with our final design.
No, you can't put the bitstream into the EPLDs. There are two options that are
open to you however:
1. Use a hardwire part, which is a mask programmed version of the SRAM FPGA.
Since this has to be done in fabrication of the part, it only makes sense
if you volume supports the nre.
2. Assuming you used the unified libraries, you can change the library and
to the EPLD you are targeting and re-run PPR. This won't get you the
same timing or layout, but it is better than starting from scratch.
If your design is tight in terms of performance or size, you may need to
do some redesign to tailor it to the EPLD architecture to improve it.
While not a magic cure-all, the use of the unified library can be
helpful in circumstances like yours.
-Ray Andraka
Chairman, the Andraka Consulting Group
401/884-7930 FAX 401/884-7950
email randraka@ids.net
The Andraka Consulting Group is a digital hardware design firm specializing in
obtaining the maximum performance from FPGAs. Services include complete
design, development, simulation, and integration of these devices and the
surrounding circuits. We also evaluate, troubleshoot, and improve existing
designs. Please call or write for a free brochure.
Article: 1647george@cmf.nrl.navy.mil (George Schmitt) wrote: > > >Suppose I have an FPGA (xilinx 4005 specifically) with a 32 >bit data path entering and a 16 bit data path exiting. Data >enters, is "processed" and then exits. The processing is >nothing more than a few pipelined registers and perhaps some >bit shifting and masking. Would the internal routing of the >design be more efficient if the external connections were >very regular (i.e. 16 IPADs clustered near each other and >16 OPADs clustered near each other) or irregular (PADs just >"randomly" placed all around the chip). If you have critical time constraints that are difficult to be achieved, then it is better to specify these time constraints and leave the placement of IOs to the router. For some designs, it is not possible to satisfy both the time constraints and fixing the locations of IOs. If you leave it to the router, it usually ends up placing the data bus irregularly, and ends up with better delays. But, first I would try to achieve both, as regularity (as you define) helps board design be simple, and testing easier. Yuce Beser "speaking for myself"Article: 1648
Greetings!
I've set up an archive of some EDA related newgroups which can be browsed
and searched via a WWWeb browser (e.g. Netscape or Mosaic) at the following
URL (Uniform Resource Locator):
http://vhdl.org/~josedc/cgi/fetch.cgi
The archive was started in July and includes the following newsgroups (of
which comp.lang.vhdl is currently the most active):
comp.arch.fpga
comp.cad.cadence
comp.cad.synthesis
comp.lang.verilog
comp.lang.vhdl
comp.lsi.cad
comp.sys.mentor
This service is a personal contribution to the internet community and
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Regards,
Jose 8')
--
Jose De Castro | phone:+1(503)695-1139
Mentor Graphics Corp | mailto:josedc@teleport.com
ASIC Vendor Engineer | http://teleport.com/~josedc/
Article: 1649george@cmf.nrl.navy.mil (George Schmitt) wrote: > > >... Would the internal routing of the >design be more efficient if the external connections were >very regular (i.e. 16 IPADs clustered near each other and >16 OPADs clustered near each other) or irregular (PADs just >"randomly" placed all around the chip). I have thought about this and have some similar designs I have done that have this same kind of issue. What I have found in my specific cases is that if you let the tools randomly place ports, routability goes DOWN. I did not really expect this as I thought the tools might try to minimize routing congestion. Alas, when I place the ports in a logical fashon, the number of routing resources went down, and my delays went down, too! All in all, I use random placement for a quick way to see if my design will have a chance of fitting and running at speed, but then I take the time to think about pin assignments and "do it right." Just my $0.02 dave
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