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Helo! I'm using a newest ver. of ISE and EDK (with all SP) on Linux Ubuntu (last relese), and I expirience a problem with UART. I've created two identical basic projects, one using 9.1 (on Windows) and the other using 9.2. (on Linux). Projects contains MB processor with UART lite only (uart is set as stdin/out), and TestApp_Memory generated application. The project created on Win (EDK 9.1) is working properly (i recive a simple message on HyperTerminal), but this one built on Linux (EDK 9.2) isn't (rs-232 terminal is empty). So I decided to check if the programming file (download.bit) from one system will work on the another. Using iMPACT, I programmed the device on Linux with file generated on Win., and on Win. using file from Linux. What was happend? Device programmed on Linux (EDK9.2) is working, and this one programmend on Win.(EDK9.1) isn't. So I'm confused, for me it looks like EDK9.2 is not generating proper programming file. Any sugestion? ps. Board is EDK S3E Starter Kit Sorry for my English :) Best regards Peter.Article: 128326
Allan Herriman <allanherriman@hotmail.com> wrote: > On Tue, 22 Jan 2008 01:00:49 -0800 (PST), kislo > <kislo02@student.sdu.dk> wrote: > >... decoupling network ... > > .. i dont have the luxury of a software tool > > to help me simulate and analyse > The headers in your post suggest you are using Windows. That's good, > because you can download LTSpice and use that. > http://www.linear.com/designtools/software/switchercad.jsp Using LTSpice with wine on linux many times :-) -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 128327
On 2007=B3=E211=BF=F928=C0=CF, =BF=C0=C0=FC12=BD=C357=BA=D0, "David Spencer"= <davidmspen...@verizon.net> wrote: > "Nevo" <n...@nevo.com> wrote in messagenews:7ei2j.14507$XT.308@trnddc01...= > > Does anyone know if it's possible to convert aByteBlasterMV into a > >ByteBlasterII, and if so what the details are? > > You could convert an originalByteBlasterto aByteBlasterMV just be > changing the eight-bit buffer in it (from an LS to an HC family I think). > However, as others have said, theByteBlasterII is a different beast with > extra features. You can buy very low cost Altera Byteblaster II clone. It is only $36.95 USD. Don't waste your time and money. http://fpgaguy.110mb.com/Article: 128328
"aka" <aka@nospam.net> wrote in message news:sfYjj.1833$Rg1.336@nlpi068.nbdc.sbc.com... > I'm pretty annoyed that the iMPACT program (download/program) is > unusable under Vista/64. When will this be fixed? ISE 10.1 in March will support Vista 32 and 64. > > Also, Xilinx EDK 9.2 doesn't run under Vista (32 or 64-bit.) EDK in 10.1 will support Vista 32. Steve > (The Cygwin component seems to be the culprit.) >Article: 128329
Finally I have tried to implement my desing with Mod Operator but all the design seems to fail. This is my code: if(read = '1' and fifo_empty='0') then addr := (addr - 1)mod(2) end if; Now I have read in a news group that MOD operator is not synthesizable when: - A mod B when B is not a power of 2. - A mod B when both A and B are not constant. Exactly it says: "a mod b" means "the remainder when a is divided by b. Note that unless 'b' is a power of 2 or both a and b are constants, the mod operation is most likely not synthesizable. The first sentence is perfect, but the second one involves that the operator has not sense. Could someone tell me if this is true?? My best regards PabloArticle: 128330
On Jan 22, 11:59=A0am, Pablo <pbantu...@gmail.com> wrote: > Finally I have tried to implement my desing with Mod Operator but all > the design seems to fail. Are we supposed to guess what the failure is? > This is my code: > > if(read =3D '1' and fifo_empty=3D'0') then > addr :=3D (addr - 1)mod(2) > end if; > So addr will count from 0 to 1 and back to 0....a toggle flip flop....probably not what you want but that's what your posted code will do. I'll bet the simulator would catch that too, did you simulate? > Now I have read in a news group that MOD operator is not synthesizable > when: > > - A mod B when B is not a power of 2. Generally speaking that's true...that's why if you need a counter that counts from 0 to 17 (or any other non power of 2 modulus) and back to 0, you code it so that if it equals 17 then reset it to 0....but I digress. > - A mod B when both A and B are not constant. > > Exactly it says: > "a mod b" means "the remainder when a is divided by b. Note that > unless 'b' is a power of 2 or both a and b are constants, the mod > operation is most likely not synthesizable. > > The first sentence is perfect, but the second one involves that the > operator has not sense. > Why does it not make sense? I'm assuming that you're confused about the "or both a and b are constants" part of the second sentence (again, take the time to let people know what exactly is your confusion). If A and B are both constants, then A mod B will also be a constant and can be computed by the synthesis tool. Here's another hint, constants do not get synthesized....as logic in terms of gates....they reduce down to things that are always either '1' or '0'...which is used in the logic optomization process. Kevin JenningsArticle: 128331
On 22 ene, 18:18, KJ <kkjenni...@sbcglobal.net> wrote: > On Jan 22, 11:59 am, Pablo <pbantu...@gmail.com> wrote: > > > Finally I have tried to implement my desing with Mod Operator but all > > the design seems to fail. > > Are we supposed to guess what the failure is? > > > This is my code: > > > if(read = '1' and fifo_empty='0') then > > addr := (addr - 1)mod(2) > > end if; > > So addr will count from 0 to 1 and back to 0....a toggle flip > flop....probably not what you want but that's what your posted code > will do. I'll bet the simulator would catch that too, did you > simulate? > > > Now I have read in a news group that MOD operator is not synthesizable > > when: > > > - A mod B when B is not a power of 2. > > Generally speaking that's true...that's why if you need a counter that > counts from 0 to 17 (or any other non power of 2 modulus) and back to > 0, you code it so that if it equals 17 then reset it to 0....but I > digress. > > > - A mod B when both A and B are not constant. > > > Exactly it says: > > "a mod b" means "the remainder when a is divided by b. Note that > > unless 'b' is a power of 2 or both a and b are constants, the mod > > operation is most likely not synthesizable. > > > The first sentence is perfect, but the second one involves that the > > operator has not sense. > > Why does it not make sense? I'm assuming that you're confused about > the "or both a and b are constants" part of the second sentence > (again, take the time to let people know what exactly is your > confusion). If A and B are both constants, then A mod B will also be > a constant and can be computed by the synthesis tool. Here's another > hint, constants do not get synthesized....as logic in terms of > gates....they reduce down to things that are always either '1' or > '0'...which is used in the logic optomization process. > > Kevin Jennings Thanks kevin, I will try to explain as better as possible. Of course, my English is not perfect. My real code is this: if(read='1' and empty='0') then addr := (addr + 1)mod(64); -- So as you said, addr INCREMENTS its value until 64. In this moment it init to 0. That's the use of mod. end if; My confusion is the following: Addr is defined as an Integer Variable in the proccess body. Of course is not constant, so its value is increment in each clock cycle. So: Could I use mod in my code??? Could Mod operator be used with variables or signals?? Thanks so muchArticle: 128332
Thanks for all the creative suggestions. We will think hard about them. But here are our priorities that combined set us apart from the field: 1. extremely small ( 5" x 3" x 1"), inexpensive, and very easy to use 2. > 1 GHz with 1 Hz granularity and low jitter, on two LVDS output channels 3. rugged box and attractive display (OLED) After that we can start thinking about luxury features like calibration etc. Peter AlfkeArticle: 128333
On Tue, 22 Jan 2008 10:02:30 -0800 (PST), Pablo <pbantunez@gmail.com> wrote: >My real code is this: > >if(read='1' and empty='0') then >addr := (addr + 1)mod(64); -- So as you said, >addr INCREMENTS its value until 64. In this moment it init to 0. >That's the use of mod. >end if; > >My confusion is the following: > >Addr is defined as an Integer Variable in the proccess body. Of course >is not constant, so its value is increment in each clock cycle. >So: Could I use mod in my code??? Based on the sentence you quote B is 64 in your case and it's a power of two so mod would be synthesizable for you. In any case most of today's synthesizers can give you a divider/mode for more general case but you probably wouldn't want it. Another solution for your problem could be to declare addr as a 6 bit integer in which case it would wrap from 63 to 0 by itself without the need for mod operator.Article: 128334
On Jan 22, 1:02=A0pm, Pablo <pbantu...@gmail.com> wrote: <snip> > Thanks kevin, I will try to explain as better as possible. Of course, > my English is not perfect. > > My real code is this: > > if(read=3D'1' and empty=3D'0') then > addr :=3D (addr + 1)mod(64); =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--= So as you said, > addr INCREMENTS its value until 64. In this moment it init to 0. > That's the use of mod. > end if; > > My confusion is the following: > > Addr is defined as an Integer Variable in the proccess body. Of course > is not constant, so its value is increment in each clock cycle. > So: Could I use mod in my code??? =A0 Yes. It will synthesize just fine because you're trying to get the value of (Addr +1) mod 64 and 64 is a power of 2. > Could Mod operator be used with > variables or signals?? > Yes. Kevin JenningsArticle: 128335
On 22 ene, 19:09, mk <kal*@dspia.*comdelete> wrote: > On Tue, 22 Jan 2008 10:02:30 -0800 (PST), Pablo <pbantu...@gmail.com> > wrote: > > >My real code is this: > > >if(read='1' and empty='0') then > >addr := (addr + 1)mod(64); -- So as you said, > >addr INCREMENTS its value until 64. In this moment it init to 0. > >That's the use of mod. > >end if; > > >My confusion is the following: > > >Addr is defined as an Integer Variable in the proccess body. Of course > >is not constant, so its value is increment in each clock cycle. > >So: Could I use mod in my code??? > > Based on the sentence you quote B is 64 in your case and it's a power > of two so mod would be synthesizable for you. In any case most of > today's synthesizers can give you a divider/mode for more general case > but you probably wouldn't want it. > > Another solution for your problem could be to declare addr as a 6 bit > integer in which case it would wrap from 63 to 0 by itself without the > need for mod operator. A 6 bit integer?????. Could you tell me how could I define this kind of variable??Article: 128336
On Jan 19, 10:24 pm, John_H <newsgr...@johnhandwork.com> wrote: > winsc...@googlemail.com wrote: > > Hello, > > > I have a design where I need a couple of 16-bit shift registers, two > > bits wide. According to the "Virtex-5 FPGA User Guide", it should be > > possible to implement one of these in just one LUT6 in a SLICEM (as > > long as one doesn't need the extra flip-flop in that slice). XST does > > recognise them as 16-bit shift registers, but always uses two LUTs for > > them, instantiating two SRLC32Es. > > > Does anyone know how to create them in one slice? > > > Thanks, > > winscatt > > Isn't theSRL16x2a macro? I can't find it in the libraries guide. > Two SRLC32Es may pack the way you expect in your V5 if they're properly > constrained *and* have the same controls. > > Are you familiar with RPMs? While I usually include my critical RPMs in > the .ucf file there are ways to introduce them into the code itself, > particularly if you're using VHDL. > > How many of these SRL pairs do you have? > Can you implement each pair with its own level of hierarchy? > Are you using XST with Verilog or VHDL? > I'm not familiar with RPMs. I don't know yet how many of the srl pairs I'll have in the end, I'm still in the early stages of the desing. And I'm using XST with VHDL.Article: 128337
On 22 ene, 19:12, KJ <kkjenni...@sbcglobal.net> wrote: > On Jan 22, 1:02 pm, Pablo <pbantu...@gmail.com> wrote: > <snip> > > > > > Thanks kevin, I will try to explain as better as possible. Of course, > > my English is not perfect. > > > My real code is this: > > > if(read='1' and empty='0') then > > addr := (addr + 1)mod(64); -- So as you said, > > addr INCREMENTS its value until 64. In this moment it init to 0. > > That's the use of mod. > > end if; > > > My confusion is the following: > > > Addr is defined as an Integer Variable in the proccess body. Of course > > is not constant, so its value is increment in each clock cycle. > > So: Could I use mod in my code??? > > Yes. It will synthesize just fine because you're trying to get the > value of (Addr +1) mod 64 and 64 is a power of 2. > > > Could Mod operator be used with > > variables or signals?? > > Yes. > > Kevin Jennings I suppose so, but kevin, I think that Xilinx doesn't synthesizes this. The design fails in the moment that I include the Mod Operator. PabloArticle: 128338
On Jan 21, 1:16 pm, George <romans...@earthlink.net> wrote: > Can anyone point me to some VHDL code for decoding bi-phase mark and > space formats. > > Thanks in advance... I don't know of any code offhand, but the decoding is pretty durn simple. I believe the Mark and Space formats only differ in the polarity that is decoded. Decoding requires a time base of some sort to time the period from the beginning of the cell and the middle. It does not have to be of a known period, but that certainly makes the design simpler. The decoder circuit has to detect the mark (transition) at the boundary of each cell. If you just sample the input using your clock and watch for a difference between input and output, that will be the flag for a mark. Start by assuming this is the cell boundary. Hold the value of the current input and time a period which is approximately 3/4 of the cell period. Compare the input value to the stored value and that tells you if there was a mark mid-cell and give you your data value, 1 for a mark and 0 for a space. Then the circuit goes back to watching for the cell boundary mark. Anytime there is a space, the mid-cell mark will be absent and if the circuit will naturally sync with the next cell boundary. I believe this decoder is just two FFs and a couple of gates, plus what ever it takes to generate your 3/4 cell period. Not a lot to it! If your time base clock is not of a known period, you will have to measure the cell period and use that measurement to time your decoder. This design would be a bit more difficult since it has to align to a cell to measure it and you can't align to a cell without being able to time the mid-mark. Except that when you receive a space it will, again, naturally measure and align to the cell. Then all is good. So it will take a period of time to align to a cell, dependent on your data.Article: 128339
hi. i have made a fuzzy system in matlab. i have converted that into a c code using the real time tool box of matlab. i want to import this code and run a NIOS processor, can i do it. i tried to create a blank project in NIOS IDE and then add the files to the directory and change the make file. but i faced error. can any one tell me the procedure to import a C code to the nios processorArticle: 128340
On Jan 22, 10:51=A0am, rickman <gnu...@gmail.com> wrote: > On Jan 21, 1:16 pm, George <romans...@earthlink.net> wrote: > > > Can anyone point me to some VHDL code for decoding bi-phase mark and > > space formats. > > > Thanks in advance... > > I don't know of any code offhand, but the decoding is pretty durn > simple. =A0I believe the Mark and Space formats only differ in the > polarity that is decoded. > > Decoding requires a time base of some sort to time the period from the > beginning of the cell and the middle. =A0It does not have to be of a > known period, but that certainly makes the design simpler. > > The decoder circuit has to detect the mark (transition) at the > boundary of each cell. =A0If you just sample the input using your clock > and watch for a difference between input and output, that will be the > flag for a mark. =A0Start by assuming this is the cell boundary. =A0Hold > the value of the current input and time a period which is > approximately 3/4 of the cell period. =A0Compare the input value to the > stored value and that tells you if there was a mark mid-cell and give > you your data value, 1 for a mark and 0 for a space. =A0Then the circuit > goes back to watching for the cell boundary mark. > > Anytime there is a space, the mid-cell mark will be absent and if the > circuit will naturally sync with the next cell boundary. =A0I believe > this decoder is just two FFs and a couple of gates, plus what ever it > takes to generate your 3/4 cell period. =A0Not a lot to it! > > If your time base clock is not of a known period, you will have to > measure the cell period and use that measurement to time your > decoder. =A0This design would be a bit more difficult since it has to > align to a cell to measure it and you can't align to a cell without > being able to time the mid-mark. =A0Except that when you receive a space > it will, again, naturally measure and align to the cell. =A0Then all is > good. So it will take a period of time to align to a cell, dependent > on your data. It sounds to me like Manchester encoding. I published a 6-flip-flop design in the old XC3000 days, and we modified it 4 years ago to fit into one CLB (8 flip-flops) in Virtex. These designs assume that you know the bit rate by about plus/minus 25%, so it's pretty rugged, but not adaptive. If anybody needs it, send me an e-mail (You might also google with "Manchester Alfke" Peter Alfke, XilinxArticle: 128341
On Jan 22, 11:10=A0am, Peter Alfke <pe...@xilinx.com> wrote: > On Jan 22, 10:51=A0am, rickman <gnu...@gmail.com> wrote: > > > > > On Jan 21, 1:16 pm, George <romans...@earthlink.net> wrote: > > > > Can anyone point me to some VHDL code for decoding bi-phase mark and > > > space formats. > > > > Thanks in advance... > > > I don't know of any code offhand, but the decoding is pretty durn > > simple. =A0I believe the Mark and Space formats only differ in the > > polarity that is decoded. > > > Decoding requires a time base of some sort to time the period from the > > beginning of the cell and the middle. =A0It does not have to be of a > > known period, but that certainly makes the design simpler. > > > The decoder circuit has to detect the mark (transition) at the > > boundary of each cell. =A0If you just sample the input using your clock > > and watch for a difference between input and output, that will be the > > flag for a mark. =A0Start by assuming this is the cell boundary. =A0Hold= > > the value of the current input and time a period which is > > approximately 3/4 of the cell period. =A0Compare the input value to the > > stored value and that tells you if there was a mark mid-cell and give > > you your data value, 1 for a mark and 0 for a space. =A0Then the circuit= > > goes back to watching for the cell boundary mark. > > > Anytime there is a space, the mid-cell mark will be absent and if the > > circuit will naturally sync with the next cell boundary. =A0I believe > > this decoder is just two FFs and a couple of gates, plus what ever it > > takes to generate your 3/4 cell period. =A0Not a lot to it! > > > If your time base clock is not of a known period, you will have to > > measure the cell period and use that measurement to time your > > decoder. =A0This design would be a bit more difficult since it has to > > align to a cell to measure it and you can't align to a cell without > > being able to time the mid-mark. =A0Except that when you receive a space= > > it will, again, naturally measure and align to the cell. =A0Then all is > > good. So it will take a period of time to align to a cell, dependent > > on your data. > > It sounds to me like Manchester encoding. > I published a 6-flip-flop design in the old XC3000 days, and we > modified it 4 years ago to fit into one CLB (8 flip-flops) in Virtex. > These designs assume that you know the bit rate by about plus/minus > 25%, so it's pretty rugged, but not adaptive. > If anybody needs it, send me an e-mail (You might also google with > "Manchester Alfke" > Peter Alfke, Xilinx Here is the original article. I googled "Manchester code" XCell: http://www.daxia.com/bibis/uploadasp/flies/xl17-30.pdf Peter AlfkeArticle: 128342
"Peter Alfke" <peter@xilinx.com> wrote in message news:4466f099-36a4-4806-995d-6b01f9230b96@q39g2000hsf.googlegroups.com... > Thanks for all the creative suggestions. We will think hard about > them. > > But here are our priorities that combined set us apart from the field: > > 1. extremely small ( 5" x 3" x 1"), inexpensive, and very easy to use > 2. > 1 GHz with 1 Hz granularity and low jitter, on two LVDS output > channels > 3. rugged box and attractive display (OLED) > > After that we can start thinking about luxury features like > calibration etc. > Peter Alfke > Hi Peter, Will the hardware and HDL be open source? You might find some of us might like to add some custom features. I guess it'll have a 2x7 JTAG download, connector, right? Cheers, Syms.Article: 128343
On Jan 22, 1:21=A0pm, Pablo <pbantu...@gmail.com> wrote: <snip> > > I suppose so, but kevin, I think that Xilinx doesn't synthesizes this. > The design fails in the moment that I include the Mod Operator. > Then either - Don't use Xilinx if it doesn't support computing X mod 64 - Change the code to be of the form shown below if (addr =3D 63) then addr <=3D 0 else addr <=3D addr - 1 end if; KJArticle: 128344
On Jan 22, 12:21 pm, Pablo <pbantu...@gmail.com> wrote: > On 22 ene, 19:12, KJ <kkjenni...@sbcglobal.net> wrote: > > > > > On Jan 22, 1:02 pm, Pablo <pbantu...@gmail.com> wrote: > > <snip> > > > > Thanks kevin, I will try to explain as better as possible. Of course, > > > my English is not perfect. > > > > My real code is this: > > > > if(read='1' and empty='0') then > > > addr := (addr + 1)mod(64); -- So as you said, > > > addr INCREMENTS its value until 64. In this moment it init to 0. > > > That's the use of mod. > > > end if; > > > > My confusion is the following: > > > > Addr is defined as an Integer Variable in the proccess body. Of course > > > is not constant, so its value is increment in each clock cycle. > > > So: Could I use mod in my code??? > > > Yes. It will synthesize just fine because you're trying to get the > > value of (Addr +1) mod 64 and 64 is a power of 2. > > > > Could Mod operator be used with > > > variables or signals?? > > > Yes. > > > Kevin Jennings > > I suppose so, but kevin, I think that Xilinx doesn't synthesizes this. > The design fails in the moment that I include the Mod Operator. > > Pablo What is it doing that you don't like? Are you getting an error message from XST, or is it not simulating the way you think it should, or what? You should know that 0 <= (N mod 64) <= 63, not 64. AndyArticle: 128345
On Jan 22, 2:10 pm, Peter Alfke <pe...@xilinx.com> wrote: > On Jan 22, 10:51 am, rickman <gnu...@gmail.com> wrote: > > > > > On Jan 21, 1:16 pm, George <romans...@earthlink.net> wrote: > > > > Can anyone point me to some VHDL code for decoding bi-phase mark and > > > space formats. > > > > Thanks in advance... > > > I don't know of any code offhand, but the decoding is pretty durn > > simple. I believe the Mark and Space formats only differ in the > > polarity that is decoded. > > > Decoding requires a time base of some sort to time the period from the > > beginning of the cell and the middle. It does not have to be of a > > known period, but that certainly makes the design simpler. > > > The decoder circuit has to detect the mark (transition) at the > > boundary of each cell. If you just sample the input using your clock > > and watch for a difference between input and output, that will be the > > flag for a mark. Start by assuming this is the cell boundary. Hold > > the value of the current input and time a period which is > > approximately 3/4 of the cell period. Compare the input value to the > > stored value and that tells you if there was a mark mid-cell and give > > you your data value, 1 for a mark and 0 for a space. Then the circuit > > goes back to watching for the cell boundary mark. > > > Anytime there is a space, the mid-cell mark will be absent and if the > > circuit will naturally sync with the next cell boundary. I believe > > this decoder is just two FFs and a couple of gates, plus what ever it > > takes to generate your 3/4 cell period. Not a lot to it! > > > If your time base clock is not of a known period, you will have to > > measure the cell period and use that measurement to time your > > decoder. This design would be a bit more difficult since it has to > > align to a cell to measure it and you can't align to a cell without > > being able to time the mid-mark. Except that when you receive a space > > it will, again, naturally measure and align to the cell. Then all is > > good. So it will take a period of time to align to a cell, dependent > > on your data. > > It sounds to me like Manchester encoding. > I published a 6-flip-flop design in the old XC3000 days, and we > modified it 4 years ago to fit into one CLB (8 flip-flops) in Virtex. > These designs assume that you know the bit rate by about plus/minus > 25%, so it's pretty rugged, but not adaptive. > If anybody needs it, send me an e-mail (You might also google with > "Manchester Alfke" > Peter Alfke, Xilinx Peter, Manchester is close, but not quite the same animal. Manchester is bi- phase Level rather than bi-Phase Mark. Manchester gets its bit value from the direction of the mark and bi-Phase Mark gets its bit value from the presence or absence of a the mark. For the OP, here is a good description of these encoding schemes, but I don't agree with the way they use the term "beginning of every bit period". Marks for both of these schemes are always present in the center of the cell and are data dependent for the cell boundaries.Article: 128346
On Jan 22, 2:45 pm, rickman <gnu...@gmail.com> wrote: > On Jan 22, 2:10 pm, Peter Alfke <pe...@xilinx.com> wrote: > > > > > On Jan 22, 10:51 am, rickman <gnu...@gmail.com> wrote: > > > > On Jan 21, 1:16 pm, George <romans...@earthlink.net> wrote: > > > > > Can anyone point me to some VHDL code for decoding bi-phase mark and > > > > space formats. > > > > > Thanks in advance... > > > > I don't know of any code offhand, but the decoding is pretty durn > > > simple. I believe the Mark and Space formats only differ in the > > > polarity that is decoded. > > > > Decoding requires a time base of some sort to time the period from the > > > beginning of the cell and the middle. It does not have to be of a > > > known period, but that certainly makes the design simpler. > > > > The decoder circuit has to detect the mark (transition) at the > > > boundary of each cell. If you just sample the input using your clock > > > and watch for a difference between input and output, that will be the > > > flag for a mark. Start by assuming this is the cell boundary. Hold > > > the value of the current input and time a period which is > > > approximately 3/4 of the cell period. Compare the input value to the > > > stored value and that tells you if there was a mark mid-cell and give > > > you your data value, 1 for a mark and 0 for a space. Then the circuit > > > goes back to watching for the cell boundary mark. > > > > Anytime there is a space, the mid-cell mark will be absent and if the > > > circuit will naturally sync with the next cell boundary. I believe > > > this decoder is just two FFs and a couple of gates, plus what ever it > > > takes to generate your 3/4 cell period. Not a lot to it! > > > > If your time base clock is not of a known period, you will have to > > > measure the cell period and use that measurement to time your > > > decoder. This design would be a bit more difficult since it has to > > > align to a cell to measure it and you can't align to a cell without > > > being able to time the mid-mark. Except that when you receive a space > > > it will, again, naturally measure and align to the cell. Then all is > > > good. So it will take a period of time to align to a cell, dependent > > > on your data. > > > It sounds to me like Manchester encoding. > > I published a 6-flip-flop design in the old XC3000 days, and we > > modified it 4 years ago to fit into one CLB (8 flip-flops) in Virtex. > > These designs assume that you know the bit rate by about plus/minus > > 25%, so it's pretty rugged, but not adaptive. > > If anybody needs it, send me an e-mail (You might also google with > > "Manchester Alfke" > > Peter Alfke, Xilinx > > Peter, > > Manchester is close, but not quite the same animal. Manchester is bi- > phase Level rather than bi-Phase Mark. Manchester gets its bit value > from the direction of the mark and bi-Phase Mark gets its bit value > from the presence or absence of a the mark. > > For the OP, here is a good description of these encoding schemes, but > I don't agree with the way they use the term "beginning of every bit > period". Marks for both of these schemes are always present in the > center of the cell and are data dependent for the cell boundaries. Opps, I mistyped. The marks at cell boundaries for Mark and Level encoding are mandatory. It is only Manchester or bi-phase Level where the mandatory transition is in the cell center.Article: 128347
Hi,
I'm trying to create a "chrono" to measure the muzzle velocity of
a paintball gun. Basically, I'm just making a two gate system out of
some IR leds and photosensors which will hook into my Spartan 3E
Starter board. The FPGA will measure the time (clock ticks, really)
between gate changes and then do the division to arrive at the
velocity, which it will display on the LCD.
I'm having some problems getting the inputs into the FPGA to
register correctly. The gate circuit uses the QSE156 (http://
www.fairchildsemi.com/ds/QS/QSE156.pdf) photosensor by Fairchild which
provides a TTL/LSTTL compatible output. Following the Xilinx
guidelines for making 5V inputs safe, I've connected the TTL output to
the board through a 390Ohm series resister.
I am using pin D7 on the J4 Header as a test input for a single
gate. I have that pin specified in the UCF as follows:
NET "gateA" LOC = "D7" | IOSTANDARD = LVTTL | SLEW = SLOW |
DRIVE = 6 ;
Now, the problem I am having is that I cant get the input to be
stable on both high and low signals from the photosensor. It appears
to oscillate at a fairly high frequency (MHz range). I tried to
debounce the input (with 16 bits) and then incremented a counter on
every rising edge of the stabilized input, but using the Spartans 8
LEDs to display the counter still was a blur. So, by that, I surmised
that the input is oscillating between high and low.
I would appreciate any input on this since I'm at a loss. Do I
have my FPGA input settings correct? Must I use a wire less than X
inches to connect the output of the photosensor to the board? Etc,
etc. What am I missing?
thanks
Jay
Article: 128348On Tue, 22 Jan 2008 12:33:38 -0800 (PST), shadfc <jay.wineinger@gmail.com> wrote: <snip> > I am using pin D7 on the J4 Header as a test input for a single >gate. I have that pin specified in the UCF as follows: > > NET "gateA" LOC = "D7" | IOSTANDARD = LVTTL | SLEW = SLOW | >DRIVE = 6 ; > <snip> I'm probably not addressing the main problem here, but... for an input, do you need specify SLEW and DRIVE? (Indeed, does it make sense to do so?) Correction invited. -- Per ardua ad nauseamArticle: 128349
"Symon" <symon_brewer@hotmail.com> wrote > Hi Kim, > I've not got much time so here's a few pointers:- > > IMO, Xilinx publish excessive requirements which covers their arse if > anything should go wrong. Fair enough. However, you should know that it's > fairly difficult to get this wrong, indeed, some folks (not me!) on this > newsgroup apparently use very few bypass caps. I don't know what you mean by very few but, for the 1.2V VCCINT, I used 12 caps in my last big FPGA board ;-) For a Stratix II 180 1.2V decoupling, I have: 5 x 2.2µF LLM21 (under the FPGA) 4 x 10µF LLL31 (under the FPGA too) 2 x 100µF 1210 caps nearby 1 x 1500µF Tantalum cap farther. I'm pretty happy with that stuff. I have a glitch less than 30mV when the FPGA current goes from 2A to 25A in a few µs. http://search.murata.co.jp/Ceramy/CatalogAction.do?sHinnm=LLM0805-22X7S225M4&sNHinnm=LLM215C70G225ME11&sLang=en http://www.murata.co.jp/cgi-spara/freq.pl?file=llm21%2Fllm215c70g225me11.s2p&lang=en&gpartnum=LLM215C70G225ME11&min=1&freq=MHz&max=10000&dB=-100 I also put small coax connectors to be able to monitor the power rails at least for the prototypes: http://www.hirose.co.jp/cataloge_hp/e32124820.pdf > Free capacitor parameter stuff.:- > http://www.murata.com/designlib/mcsil/index.html I use that too. > Above a few 10's of MHz, all same sized caps have the same impedance. (See > murata thing above) Just use 0402 1uF for everything. One per pin is more > than enough. Make sure your board has a ground plane, try to use two vias > for each cap terminal. > > Here's some stuff on where to place your caps. > > http://www.sigcon.com/pubsIndex.htm#bypass%20capacitors > > Or, ignore that stuff, sooo 20th C. Better bypass here:- > http://www.x2y.com/ IMHO the LLM21 are better ;-) Marc
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