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Adam Megacz wrote:
> Hey, does anybody know if you can damage Atmel's newer FPGAs with a
> bad bitstream (ie vdd-to-ground contention)?
The same question: is it possible to damage a Cyclone with a bad bitstream?
Remark: it's a feature, not a bug. SRAM-based FPGA devices are too easy
to clone. FPGA manufacturers: why can't you mount two chips inside one
package,
one containing an FPGA and the second one with configuration flash and add
readback fuses, JTAG access fuses etc.? A small amount of EEPROM would
be great too...
Best regards
Piotr Wyderski
Article: 86051"Jan Bernauer" <taggedfordeletion@web.de> wrote in message news:0ntio2-abt.ln1@ns.paranoid.net... > Marco wrote: >> "John Williams" <jwilliams@itee.uq.edu.au> wrote in message >> news:newscache$n3rcii$ue5$1@lbox.itee.uq.edu.au... >> > >>>#define HEIGHT ... >>>#define WIDTH ... >>> >>>unsigned char *display[HEIGHT][WIDTH] = (unsigned char *)0x77200000; >>> >>>display[y][x] = ... >>> >>>Regards, >>> >>>John >> >> >> I have tried using what you told me, but during compilation, I receive >> the >> following error message: >> >> invalid initialize >> >> What could I do? >> >> Many Thanks >> Marco >> >> > > Try > > unsigned char *display[HEIGHT*WIDTH] = (unsigned char *)0x77200000; > > > display[y*WIDTH+x] = > > > I think display[][] is a pointer to a list of pointers: char **, but > that's not what you want. > > > If your WIDTH is a power of 2, use shifts instead of y*width. > > > HTH, > Jan > > I receive the same error message during compilation: invalid initialize What could I do? Many Thanks MarcoArticle: 86052
Of course one could try to write an own FIFO, it case been discussed here several times ... But my question still is why the MegaWizard says "Output register option for devices with fully synchronous RAM Would like to register the outputs to maximize performance but use more area?" --> YES (best speed) and YET the RTL viewer does not show an output register stage ? Rgds Andr=E9 Mike Treseler schrieb: > ALuPin@web.de wrote: > > > And yet I cannot see any output registers for the "best speed" > > optimized one. I can go down the hierachy until I see the > > RAM block but there are no additional flipflops between the > > RAM block and the outputs of the SCFIFO. > > Speed/Area constraints are just hints. > If you know what you want, skip the wizard > and write your own code. >=20 > -- Mike TreselerArticle: 86053
They definitely were there the other day, but there were none of the smaller devices. Now it seems to be the other way round. 8-) LeonArticle: 86054
Marco wrote:
>"Jan Bernauer" <taggedfordeletion@web.de> wrote in message
>news:0ntio2-abt.ln1@ns.paranoid.net...
>
>
>>Marco wrote:
>>
>>
>>>"John Williams" <jwilliams@itee.uq.edu.au> wrote in message
>>>news:newscache$n3rcii$ue5$1@lbox.itee.uq.edu.au...
>>>
>>>
>>>
>>>>#define HEIGHT ...
>>>>#define WIDTH ...
>>>>
>>>>unsigned char *display[HEIGHT][WIDTH] = (unsigned char *)0x77200000;
>>>>
>>>>display[y][x] = ...
>>>>
>>>>Regards,
>>>>
>>>>John
>>>>
>>>>
>>>I have tried using what you told me, but during compilation, I receive
>>>the
>>>following error message:
>>>
>>>invalid initialize
>>>
>>>What could I do?
>>>
>>>Many Thanks
>>>Marco
>>>
>>>
>>>
>>>
>>Try
>>
>>unsigned char *display[HEIGHT*WIDTH] = (unsigned char *)0x77200000;
>>
>>
>>display[y*WIDTH+x] =
>>
>>
>>I think display[][] is a pointer to a list of pointers: char **, but
>>that's not what you want.
>>
>>
>>If your WIDTH is a power of 2, use shifts instead of y*width.
>>
>>
>>HTH,
>>Jan
>>
>>
>>
>>
>
>I receive the same error message during compilation:
>
>invalid initialize
>
>What could I do?
>
>Many Thanks
>Marco
>
>
>
>
Hi Marco,
I'm far from being good at C, but I have some hobby-interest in
MicroBlaze and C in general...
What you are trying to do is not specifically MicroBlaze related - try
the same code in a linux gcc compiler, for example, and you will get the
same error.
When you write something like:
unsigned char *display[HEIGHT][WIDTH] = (unsigned char *)0x77200000;
What I think you are trying to say is "I want a pointer to a 2-D array,
which has a base address of 0x77200000"
But the compiler sees this as an attempt to initalize the contents of
the memory - and says "invalid initalizer"
In order to memory map a perpherial, I have used my own simple hack
which is the following:
volatile unsigned char *ptr_to_mem;
int main()
{
ptr_to_mem = (unsigned char *) 0x77200000;
ptr_to_mem[address] = data;
}
This is a simple and vaild way to access byte-wise any memory starting
at the base address shown abloe. you delcare the pointer as just a
pointer to memory, and you access successive bytes by using it as an array.
(Note: the volaitle is important - as it forces the memory access to occur)
(Note: If you try this on a linux machine, it will have a segmentation
fault, as it doesn't want you to assign the memory addesses!! - works
fine in a microblaze without an OS though)
To implement a 2-D array, it can be done as anohter poster suggested, by
having a power of 2 width, hardware barrel shifter, and calculating the
address from that, and using a single-subscripted array.
This is probably far from the recommended way to do this but it works! -
maybe for the real answer it might be worth checking out some C related
newsgroups?
Cheers,
John
--
***********************************************************************
/ /\/ John McGrath
\ \ Xilinx Inc.
Mixed Signal IC Design Engineer
\_\/\
Telephone: +353 21 4355 704
FAX:
John.McGrath@xilinx.com
X I L I N X I N C.
***********************************************************************
Article: 86055BRAMs are "free" if you have no other use for them. The chip has a cetain number of BRAMs, and if you do not use them, they just sit there and do nothing for you. So, they are free until you need more than you have, then they are precious. Peter Alfke, XilinxArticle: 86056
Hi,
Do you have experience with nios2 and a specific terminal (hyperterminal,
tera pro, or others) ?.
I have problem to only have an easy printf message !!....
I 'm using Stratix(10) Altera Develop KIT with UART "console" DB9.
I'm using example 'standart' (this example have an uart)
In the Nios software I'm using example 'hello_word".
jtag_uart is OK, I receive this message 'hello_word' in the NIOS IDE
console.
How could I obtain this result with "uart" and a terminal.
How can I do choices ('jtag_uart' and/or 'uart') to write this message ('IDE
console' and/or 'terminal') ?.
(for example options in properties of system library => std_out, std_err,
std_in)
When I'm trying this example with UART, I have two result :
=> if I don't connect first the COM of the terminal:
nios2-terminal: connected to hardware target using UART on
/dev/com1 at 115200 baud
nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)
=> if I connect first the COM of the terminal :
nios2-terminal: can't open uart: Permission denied
(So I'm using COM2 as terminal, and I connect the cable to this COM2, and I
configure the properties of system library as COM1. )
(no hardware problem with RS232 cāble, loopback test is OK with pin 2 and 3
of DB9).
Regards,
H.
Article: 86057
"Marco" <marcotoschi@_no_spam_email.it> wrote in message
news:d992kv$ml5$1@news.ngi.it...
> >>>unsigned char *display[HEIGHT][WIDTH] = (unsigned char *)0x77200000;
> > unsigned char *display[HEIGHT*WIDTH] = (unsigned char *)0x77200000;
> > display[y*WIDTH+x] =
> > <various other things trimmed>
There is a lot of confusion here about pointers and arrays in C.
The declaration:
unsigned char *display[HEIGHT][WIDTH];
...means "display is a two-dimensional array with elements
of type 'pointer to character'."
Similarly:
unsigned char *display[HEIGHT*WIDTH];
...means "display is a one-dimensional array with elements
of type 'pointer to character'."
Consequently, trying to initialize either of these "display" variables
with an 'unsigned char *', that is, a 'pointer to character', will not work
because the types of the variable and the initializer are different.
Now, a variable of pointer type in C can be initialized to point
somewhere (like to the 1,998,585,856th location in memory, in
this example), but an array (of any dimension) cannot. Your best
bet is to make "display" into a variable of type "pointer to a
two-dimensional array of characters", which is probably what
you were trying to do in the first place. The syntax for this is:
unsigned char (*display)[HEIGHT][WIDTH];
Note that the brackets are vital, because [] has higher precedence
than * (see K&R p53).
To initialize this variable "display" to point to the screen buffer, do this
(I'm omitting 'unsigned' from now on for brevity):
char (*display)[HEIGHT][WIDTH] = (char (*)[HEIGHT][WIDTH])0x77200000;
Now, to write to location (x,y), do this:
(*display)[y][x] = value;
As a previous poster pointer out, you might be better off with a
one-dimensional array. For a start, you'll probably get more efficient
code than for the multiple indirection above.
As an aside: you can dispense with the [HEIGHT] part if you like,
and just write:
char (*display)[][WIDTH] = (char (*)[][WIDTH])0x77200000;
Also, a typedef might make your code more readable:
typedef char display_buffer_t[HEIGHT][WIDTH];
display_buffer_t *display = (display_buffer_t*)0x77200000;
Good luck!
-Ben-
Article: 86058Lattice XP? One die is much better than two. Cheers, JonArticle: 86059
You can use -- #define WIDTH 640 #define HEIGHT 480 unsigned char (*display)[WIDTH] = (unsigned char (*)[WIDTH]) 0x77200000; -- or to make it more readable -- #define WIDTH 640 #define HEIGHT 480 typedef unsigned char (*dtype)[WIDTH]; dtype display = (dtype) 0x77200000; --- In both cases you can later access the display with display[i][j] = 0; // clear pixel - Peter Marco wrote: > Hallo, > I must create a memory for a display lcd. This is part of a microcontroller > based on microblaze. > > I thought to do it using a variable, a matrix: display[X][Y] (the software > video memory). > > This variable should exaclty stay into microblaze address space where I have > mapped a blockram (the hardware video memory) from 0x77200000 to 0x7720FFFF. > > In this way, working with my variable I could edit hardware video memory. > > But I'm not able... how may I do it? > > Many Thanks in Advance > Marco Toschi > > >Article: 86060
Jon Beniston wrote:
> Lattice XP?
Or Actel ProASIC. But what about Altera and Xilinx? :-)
> One die is much better than two.
Sure, but I've been told that it is hard to produce flash and FPGA cores
on a single piece of silicon because of technological differences.
Best regards
Piotr Wyderski
Article: 86061"Peter Ryser" <peter.ryser@xilinx.com> wrote in message news:42B82B03.9040900@xilinx.com... > You can use > > -- > #define WIDTH 640 > #define HEIGHT 480 > > unsigned char (*display)[WIDTH] = (unsigned char (*)[WIDTH]) 0x77200000; > -- > > or to make it more readable > > -- > #define WIDTH 640 > #define HEIGHT 480 > > typedef unsigned char (*dtype)[WIDTH]; > dtype display = (dtype) 0x77200000; > --- > > In both cases you can later access the display with > display[i][j] = 0; // clear pixel > > > - Peter > > > > Marco wrote: >> Hallo, >> I must create a memory for a display lcd. This is part of a >> microcontroller >> based on microblaze. >> >> I thought to do it using a variable, a matrix: display[X][Y] (the >> software >> video memory). >> >> This variable should exaclty stay into microblaze address space where I >> have >> mapped a blockram (the hardware video memory) from 0x77200000 to >> 0x7720FFFF. >> >> In this way, working with my variable I could edit hardware video memory. >> >> But I'm not able... how may I do it? >> >> Many Thanks in Advance >> Marco Toschi >> >> >> > If instead I would access not only 1 pixel at a time, but 8 pixels at a time, so a byte, what should I do? Many Thanks MarcoArticle: 86062
Guys I'm trying to Time Division Multiplex virtual channels onto a rocketio system that is allready using Aurora. Everything is easy untill I come to add flow control, the receiving end saying it can't accept any more data (preferably on a clock by clock basis). This is easily done with the Aurora as standard but with TDM some of the virtual channels do have valid data in them so I can't stop the Aurora, I need the transmitting end to stop putting data into its time slice. The problem is the time delay between the receiving end saying stop and the transmitting end stopping. The only solution I have at the moment uses an awfull lot of FIFOs Any thoughts appreciated. KatherineArticle: 86063
Hi Andre, The outp[ut registers are an optional component in the M4K blocks. To illustrate this, create a dual-port memory using the Plug-in manager. At a certain point you get to the page where you can select which ports to register. One of them is the Q output. These output registers are inside the M4Ks, so you won't see them. If you look at the parameter with which the SCFIFO instantiates the M4K, you should see a difference. If not... Best regards, BenArticle: 86064
All, The hiccup was changing over from the older mixed 12" and 8" wafer stock to the newer 12" only wafer stock. We like to notify our customers when we change something .... even it is just a matter of simple book-keeping. Austin Leon wrote: > They definitely were there the other day, but there were none of the > smaller devices. Now it seems to be the other way round. 8-) > > Leon >Article: 86065
hello Is there any example of how to add JTAG port support into own non-SOPC builder design like I can directly access SPI config port? For example I want to read/set own register word from an own JTAG tool. thx rickArticle: 86066
Hi Ed, where do I find the webserver design source of "webserver using Hard Tri-Mode Ethernet MAC . ML403". I tried to design it myself and got strucked with clock placement constraints errors in PAR. Hope there must be some guidelines to run webserver application similar to the one in ML403 tutorials. Can u please give some info or hints to use TEMAC in my design to run webserver application on ML403 board. thanks in advanceArticle: 86067
So, the IOB in V2PRO has two tristate pins, T1 and T2. As far as I can tell, they're interchangeable in standard, i.e. non DDR, modes. In one of my designs it would help if I could get the tools to use T2 rather than the T1 it defaults too. There's slightly faster direct routing available to the T2 pin, saving 200ps from my timing budget. Sadly, the tools don't want to swap the T1 and T2 pins. Directed routing doesn't work; the route to T2 fails. I'm using ISE6.3. (waiting for SP3 before moving to ISE7.1!!) I'm not using any of the FFs in the IOB. Questions. 1) Is it true that the T1 and T2 pins are interchangeable in this mode? 2) How can I get the tools to swap the pins? 3) Is there an IOB instantiation component that includes the T2 pin? Any thoughts gratefully received. TIA, Syms.Article: 86068
Assuming that you use 1 bit per pixel a display[i][j] = 0; actually clears 8 pixels at a time. - Peter Marco wrote: > "Peter Ryser" <peter.ryser@xilinx.com> wrote in message > news:42B82B03.9040900@xilinx.com... > >>You can use >> >>-- >>#define WIDTH 640 >>#define HEIGHT 480 >> >>unsigned char (*display)[WIDTH] = (unsigned char (*)[WIDTH]) 0x77200000; >>-- >> >>or to make it more readable >> >>-- >>#define WIDTH 640 >>#define HEIGHT 480 >> >>typedef unsigned char (*dtype)[WIDTH]; >>dtype display = (dtype) 0x77200000; >>--- >> >>In both cases you can later access the display with >>display[i][j] = 0; // clear pixel >> >> >>- Peter >> >> >> >>Marco wrote: >> >>>Hallo, >>>I must create a memory for a display lcd. This is part of a >>>microcontroller >>>based on microblaze. >>> >>>I thought to do it using a variable, a matrix: display[X][Y] (the >>>software >>>video memory). >>> >>>This variable should exaclty stay into microblaze address space where I >>>have >>>mapped a blockram (the hardware video memory) from 0x77200000 to >>>0x7720FFFF. >>> >>>In this way, working with my variable I could edit hardware video memory. >>> >>>But I'm not able... how may I do it? >>> >>>Many Thanks in Advance >>>Marco Toschi >>> >>> >>> >> > > If instead I would access not only 1 pixel at a time, but 8 pixels at a > time, so a byte, what should I do? > > Many Thanks > Marco > >Article: 86069
Peter Alfke wrote: > BRAMs are "free" if you have no other use for them. I have lots of other uses for them :-) > The chip has a cetain number of BRAMs, and if you do not use them, they > just sit there and do nothing for you. So, they are free until you need > more than you have, then they are precious. I need them in other applications that will use the same FPGA, this filter is only a little part of the whole project, so I'm investigating the causes of the large amount of BRAM used by the MAC_FIR. Maybe my question was not so clear, I just wanted to know if these BRAMS that shares routing resources with the Multipliers will be available for other cores that need them (like the FFT i.e.).Article: 86070
Dear Valentin, It depends on whether the synthesized logic is FF with asynchronous reset or not, as using SRL stuff can give some advantages as well. It also depends on how many states are in your the state machine, and its implementation. If you are going to use one-hot encoding, then "clock enable"-less design is likely to run faster, otherwise it may not. If you could give more details... Hope this helps Vladislav "valentin tihomirov" <spam@abelectron.com> wrote in message news:42b41cca$0$181$bb624dac@diablo.uninet.ee... > Lets consider an abstract machine generating a new word from in a finite > space at every its step in a deterministic way. We have a golden word (a > key). The goal is to get its index in the sequence of the words. That is, > once the generator has produced the key word, the machine stops and the > word > counter keeps the resulting index. > > The implementation of the design involves a "clock enable" MUX at each FF. > That is, the running generator will load next state on every clk while > stopped FSM will persist it state. The MUXes in this architure will be > controlled by the feedback signal > > done = (current_word = golden_key) > > Well, my question is about "clocked enable" efficiency in the ordinary > FPGAs. I am considering a design avoiding the feedback in order to > maximize > generator's speed (and reduce hardware demands). We could start the > generator by pushing its reset input. Once the generator produces the > anticipated word at its output at some moment of time, we would latch the > index (result of computation) letting the machine rush further. We are not > interested in the machine anymore, we have obtained the result and can let > it blow up. How advantageous would be this 2nd design? > >Article: 86071
This is common to have a gate-level problems whi;le the design is working on the board. If your design is not high-speed and your statis timing analysis is alright, then running gate-level simulation is really almost meaningless, as this is FPGA and not ASIC. Vladislav <yaseenzaidi@NETZERO.com> wrote in message news:1119327236.103890.308980@g14g2000cwa.googlegroups.com... > Greetings, > > I have a situation where Post Translate timing is significantly > different from behavioral/RTL simulation. I am not not speaking of > simple delays, the outputs/data are different than what they should be. > > > What is interesting is that the design works on the FPGA board. > I implemented a serial port in loopback mode in Xilinx, if I type a > character on Hyperterm I get the same returned from the FPGA. > > I have set timing constraints but to no effect. > > YZ >Article: 86072
"Patrick" <patrick.melet@dmradiocom.fr> schrieb im Newsbeitrag news:54b3002.0506202349.2d016709@posting.google.com... > We add a RC circuit beetween the reset from the Stratix circuit to the > MAX circuit. So the MAX is resetted after the 3.3V is ON and sometimes > the program from the flash don't boot !!! > This is a big problem for our system which uilizes 3 boards... > My Support from Altera don't explain me what's happen... So why to safe a buck to get a REAL voltage monitor. Do it and try. And see. Regards FalkArticle: 86073
> I am using a MAX II part in a new design with 3.3V supplies. > I understand why the inputs might not be 5 volt tolerant. Be careful with your terms. 5 volt tolerant means that the device can survice and operate connected to other 5 volt devices. Typically it's used when a 3.3 or lower voltage device is connected to a 5 volt device and means that the 5 vold device won't damage the 3.3 volt device. 5 volt compatible means that the 3.3 volt device will receive and transmit 5 volt voltage levels ignals. TTL compatible means TTL signal levels and CMOS compatible means CMOS voltage levels > Altera states that the outputs are not 5 volt tolerant when driving CMOS > but are OK for TTL. Since TTL is essentially dead, I'm not sure this is of > any real benefit, however this is not my main concern. Change your word tolerant to compatible and perhaps your sentence becomes clearer. > I don't see why there would be any problem driving a CMOS input provided > that the CMOS input will accept 3.3V signals as high. There certainly isn't > going to be any significant current flow into the CMOS gate. Hope this helped. gmArticle: 86074
Valentin, an FPGA is a fixed structure where many (but not all) connections can be programmed. The CE multiplexer is fixed, you cannot eliminate or bypass it. You can only decide to use it, or leave it permanently connecting the input directly to the flip-flop's D input. Therefore, I do not undestand your question. Peter Alfke, Xilinx
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