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Messages from 86000

Article: 86000
Subject: Re: ISE 7.1 Service Pack 2 - Ready yet?
From: "Marc Randolph" <mrand@my-deja.com>
Date: 20 Jun 2005 04:55:11 -0700
Links: << >>  << T >>  << A >>

Jeremy Stringer wrote:
> I'm starting a new project at the moment, and I'm looking at upgrading
> to ISE 7.1, since I prefer not to change synth/par tool versions
> mid-project.  I noted that a number of people complained about 7.1 when
> it first came out, but also noted that Service Pack 2 is out now.  Can
> anybody comment on the state of ISE 7.1 at the moment?

Howdy Jeremy,

I don't use Linux, but Windoze based 7.1i has stablized enough that
chances are slim you'd run into any problems with it - and even if you
do, they are likely fixed in SP3 (due out in the next week or so).

Have fun,

   Marc


Article: 86001
Subject: Re: Microblaze address space and variables
From: "Marco" <marcotoschi@_no_spam_email.it>
Date: Mon, 20 Jun 2005 14:57:37 +0200
Links: << >>  << T >>  << A >>

"John Williams" <jwilliams@itee.uq.edu.au> wrote in message 
news:newscache$n3rcii$ue5$1@lbox.itee.uq.edu.au...
> Hi Marco,
>
> Marco wrote:
>
>> I must create a memory for a display lcd. This is part of a 
>> microcontroller
>> based on microblaze.
>>
>> I thought to do it using a variable, a matrix:  display[X][Y]  (the 
>> software
>> video memory).
>>
>> In this way, working with my variable I could edit hardware video memory.
>>
>> But I'm not able... how may I do it?
>
> #define HEIGHT ...
> #define WIDTH ...
>
> unsigned char *display[HEIGHT][WIDTH] = (unsigned char *)0x77200000;
>
> display[y][x] = ...
>
> Regards,
>
> John

I have tried using what you told me, but during compilation, I receive the 
following error message:

invalid initialize

What could I do?

Many Thanks
Marco 



Article: 86002
Subject: Re: Microblaze address space and variables
From: Jan Bernauer <taggedfordeletion@web.de>
Date: Mon, 20 Jun 2005 15:42:27 +0200
Links: << >>  << T >>  << A >>
Marco wrote:
> "John Williams" <jwilliams@itee.uq.edu.au> wrote in message 
> news:newscache$n3rcii$ue5$1@lbox.itee.uq.edu.au...
> 

>>#define HEIGHT ...
>>#define WIDTH ...
>>
>>unsigned char *display[HEIGHT][WIDTH] = (unsigned char *)0x77200000;
>>
>>display[y][x] = ...
>>
>>Regards,
>>
>>John
> 
> 
> I have tried using what you told me, but during compilation, I receive the 
> following error message:
> 
> invalid initialize
> 
> What could I do?
> 
> Many Thanks
> Marco 
> 
> 

Try

unsigned char *display[HEIGHT*WIDTH] = (unsigned char *)0x77200000;


display[y*WIDTH+x] =


I think display[][] is a pointer to a list of pointers: char **, but
that's not what you want.


If your WIDTH is a power of 2, use shifts instead of y*width.


HTH,
	Jan



Article: 86003
Subject: Xilinx MacFir5.0 - Block Ram requirenments
From: "Nemesis" <nemesis2001@gmx.it>
Date: 20 Jun 2005 06:53:42 -0700
Links: << >>  << T >>  << A >>
Hi all,
I implemented a fir filter using the MacFir5.0 core from Xilinx.
The filter 2 coefficient sets of 33 taps, with 14 bit
coefficients and data.

I was looking at the resouces utilization and I found a strange data,
the filter requires 33 multipliers and 33 block ram.

I can't understand why it requires so much block rams! Each block ram
should store 1k x 18bits!
If I set the core to use the distributed ram for coefficients or
for data this number doesn't change, of course it goes to zero when
I set the core to use the distributed ram for both coefficients and
data.

I read on the User Guide that multipliers and block ram shares routing
resources,
is that the cause of the great number of bram used?


Article: 86004
Subject: BIG PROBLEM : Configuration Boot Problem Stratix
From: patrick.melet@dmradiocom.fr (Patrick)
Date: 20 Jun 2005 07:05:46 -0700
Links: << >>  << T >>  << A >>
hi,

we've got some Stratix DSP development kit EP1S25 where at the
power-on don't load the flash memory to the FPGA !!!

We've seen that the EPLD MAX 7064 often fail the programmation of the
FPGA...

We've seen that the RESET of this EPLD is in the same time that the
3.3 V power-on...

Did someone have this this problem yet... and how to boot at any time
on power-on ?

Perhaps it's be better if the RESET is after the 3.3V power-on ?

We utilizes 3 board in a big system and we have this problem now of
non programming at boot..

Thanks

Article: 86005
Subject: Re: Lean Ethernet on Digilent board?
From: "Alfredo" <iluvfpgas@yahoo.ca>
Date: 20 Jun 2005 07:45:18 -0700
Links: << >>  << T >>  << A >>
I already have the Spartan3 board and as I can tell from your reply, I
should be able to do something challeging and usefull once I get the
Ethernet add-on.

Thanks,

***
Alfredo.


Article: 86006
Subject: Speeding up FPGA designs
From: Tommy Thorn <foobar@nowhere.void>
Date: Mon, 20 Jun 2005 15:07:43 GMT
Links: << >>  << T >>  << A >>
I'm looking for recommended practices for tuning my FPGA design.  Merly 
cranking up the constraints and eyeballing the TA output doesn't seem to 
work very well for non-trivial problems (I find it very hard to relate 
back to my RTL).

Presumedly the better approach is to work on submodules though timing 
estimates for individual modules are highly likely to be too optimistic 
as they do not account for inter-module connections and competition for 
resources.

I vaguely remember reading about in a Xilinx app note how they had two 
versions of a particular module (an SDRAM controller?), one for real use 
and one for estimating the performance.  The difference IIRC was that 
input and output were registered.

Any suggestions?

Thanks,
Tommy -- fpga at numba-tu dot com

Article: 86007
Subject: Re: Speeding up FPGA designs
From: "Symon" <symon_brewer@hotmail.com>
Date: Mon, 20 Jun 2005 08:55:35 -0700
Links: << >>  << T >>  << A >>
"Tommy Thorn" <foobar@nowhere.void> wrote in message 
news:3ZAte.1390$p%3.10763@typhoon.sonic.net...
> I'm looking for recommended practices for tuning my FPGA design.  Merly 
> cranking up the constraints and eyeballing the TA output doesn't seem to 
> work very well for non-trivial problems (I find it very hard to relate 
> back to my RTL).
>
Tommy,
Well, that's the way I normally do it. Look at the paths that fail in the TA 
and then pipeline the paths. After a while you learn to pipline everything 
anyway, the FFs are free and don't use that much power.
I guess this doesn't really help, but there you go!
Cheers, Syms. 



Article: 86008
Subject: Re: Speeding up FPGA designs
From: Paul Hartke <phartke@Stanford.EDU>
Date: Mon, 20 Jun 2005 09:21:11 -0700
Links: << >>  << T >>  << A >>
If you haven't already, check out PlanAhead:
http://www.xilinx.com/ise/optional_prod/planahead.htm

Tommy Thorn wrote:
> 
> I'm looking for recommended practices for tuning my FPGA design.  Merly
> cranking up the constraints and eyeballing the TA output doesn't seem to
> work very well for non-trivial problems (I find it very hard to relate
> back to my RTL).
> 
> Presumedly the better approach is to work on submodules though timing
> estimates for individual modules are highly likely to be too optimistic
> as they do not account for inter-module connections and competition for
> resources.
> 
> I vaguely remember reading about in a Xilinx app note how they had two
> versions of a particular module (an SDRAM controller?), one for real use
> and one for estimating the performance.  The difference IIRC was that
> input and output were registered.
> 
> Any suggestions?
> 
> Thanks,
> Tommy -- fpga at numba-tu dot com

Article: 86009
Subject: Re: Lattice LFEC
From: "cas7406@yahoo.com" <cas7406@yahoo.com>
Date: 20 Jun 2005 10:38:07 -0700
Links: << >>  << T >>  << A >>

have set the respective timing constraints? ispLEVER P&R tool is a
timing driven tool.

rgds,

c

Jedi wrote:
> Hello..
>
> Is this normal that same core which performs well
> for Altera Cyclone device can only run at half speed
> on a LFEC20-5 device?
>
> Tried with several CPU cores from opencores.org
> and LAttice LFEC20 shows mostly half the performance
> as Cyclone...
> 
> 
> rick


Article: 86010
Subject: [SPARTAN-3]: Parts Back on Xilinx Online Store (www.xilinx.com/store)
From: "Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com>
Date: Mon, 20 Jun 2005 10:47:59 -0700
Links: << >>  << T >>  << A >>
As promised last week, Xilinx Spartan-3 FPGAs (XC3S50 through XC3S400) are
back on the Xilinx online store and in stock.
http://www.xilinx.com/store

My apologies for any inconvenience that this might have caused.  The devices
available online are all from the new 300 mm wafer production line.  The
change-over caused a momentary hiccup in the store data base.
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/-3E FPGAs
http://www.xilinx.com/spartan3e
---------------------------------
The Spartan(tm)-3 Generation:  The World's Lowest-Cost FPGAs.




Article: 86011
Subject: Re: Idea exploration - Image stabilization by means of software.
From: Anton Erasmus <nobody@spam.prevent.net>
Date: Mon, 20 Jun 2005 19:51:53 +0200
Links: << >>  << T >>  << A >>
On Sun, 19 Jun 2005 21:43:20 -0700, "Jon Harris"
<jon_harrisTIGER@hotmail.com> wrote:

>"Anton Erasmus" <nobody@spam.prevent.net> wrote in message
>news:1119169974.ea68157269af093d1f453f607f949e3c@teranews...
>> On Sun, 19 Jun 2005 00:57:12 -0700, "Jon Harris"
>> <jon_harrisTIGER@hotmail.com> wrote:
>>
>> >> "Anton Erasmus" <nobody@spam.prevent.net> wrote in message
>> >> news:1119000420.d54828b53b9bcd51f76b2b5b640103a6@teranews...
>> >> >>
[Snipped]
>>
>> Yes one would need a sensor with a low noise floor. The lower the
>> better. AFAIK the more pixels they pack into a sensor, the higher the
>> noise floor. Currently the whole emphasis is on producing sensors with
>> more pixels. If the emphasis was on producing sensors with very low
>> noise floor, I am sure a suitable sensor can be developed.
>
>Yes, if you only required, say a 1MP image, this would certainly help, both in
>terms of noise and ability to read out the data quickly.
>

1MP is quite adequite for a postcard size image or for a newspaper
photo. I think there is at least a niche market for a 1MP digital
camera that can take a photo without flash that is not blurred in
conditions where other cameras would produce a blurred photo.
If the sensor technology keeps improving as it had over the last 5
years or so, then the 1MP would go up to 3 or 5MP quite quickly.


Regards
  Anton Erasmus


Article: 86012
Subject: Re: BIG PROBLEM : Configuration Boot Problem Stratix
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Mon, 20 Jun 2005 20:06:06 +0200
Links: << >>  << T >>  << A >>

"Patrick" <patrick.melet@dmradiocom.fr> schrieb im Newsbeitrag
news:54b3002.0506200605.3dadb7cc@posting.google.com...

> Perhaps it's be better if the RESET is after the 3.3V power-on ?

Use a voltage monitor that releases the reset after ALL voltages are valid.

Regards
Falk




Article: 86013
Subject: Re: Lattice LFEC
From: Jedi <me@aol.com>
Date: Mon, 20 Jun 2005 18:57:31 GMT
Links: << >>  << T >>  << A >>
cas7406@yahoo.com wrote:
> have set the respective timing constraints? ispLEVER P&R tool is a
> timing driven tool.
> 

No...as I don't see the point in doing so when under default
settings Lattice LFEC is at least 50 % slower...


rick

Article: 86014
Subject: Design tools comparison between Xilinx, Altera and Lattice for FPGA designs
From: Luc <lb.edc@pandora.be>
Date: Mon, 20 Jun 2005 21:21:38 +0200
Links: << >>  << T >>  << A >>
Guys,

I'm trying to compare Altera, Xilinx and Lattice tools (free version)
Can Xilinx, Altera and Lattice supporters comment?
I found:
Lattice starter has included Leonardo/Precision RTL and Synplify, no
ModelSim
Xilinx ISE WebPack : XST, no Leonardo/Precision, no Synplify, no
ModelSim
Altera QuartusII Web Edition: support for Synplify, Precision and
Modelsim?

I know it's a simple comparison, but I would like to be clear on this.

Best regards,

Luc

Article: 86015
Subject: Re: Design tools comparison between Xilinx, Altera and Lattice for FPGA designs
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Mon, 20 Jun 2005 21:37:05 +0200
Links: << >>  << T >>  << A >>

"Luc" <lb.edc@pandora.be> schrieb im Newsbeitrag
news:kn4eb1p4g60qn0pvpkgamknj6q2nlt2e3p@4ax.com...
> Guys,
>
> I'm trying to compare Altera, Xilinx and Lattice tools (free version)
> Can Xilinx, Altera and Lattice supporters comment?
> I found:
> Lattice starter has included Leonardo/Precision RTL and Synplify, no
> ModelSim
> Xilinx ISE WebPack : XST, no Leonardo/Precision, no Synplify, no
> ModelSim

For Xilinx, Modelsim comes in a seperate module, but its also free (AFAIK
full simulation speed up to 10000 VHDL lines, wow)

Regards
Falk




Article: 86016
Subject: Re: Lattice LFEC
From: Luc <lb.edc@pandora.be>
Date: Mon, 20 Jun 2005 21:38:30 +0200
Links: << >>  << T >>  << A >>
Rick,

I can't speak for LatticeEC in specific, but I know that some
designers tend to write their VHDL very specific for one family. Than
it will be hard to get the same performance from another device.

I.e. does the compiled design make use of the IO cell? Switching this
option of can save quite some time (Clock to Out).

Regards,

Luc

On Mon, 20 Jun 2005 18:57:31 GMT, Jedi <me@aol.com> wrote:

>cas7406@yahoo.com wrote:
>> have set the respective timing constraints? ispLEVER P&R tool is a
>> timing driven tool.
>> 
>
>No...as I don't see the point in doing so when under default
>settings Lattice LFEC is at least 50 % slower...
>
>
>rick


Article: 86017
Subject: Re: Lattice LFEC
From: Jedi <me@aol.com>
Date: Mon, 20 Jun 2005 19:42:39 GMT
Links: << >>  << T >>  << A >>
Luc wrote:
> Rick,
> 
> I can't speak for LatticeEC in specific, but I know that some
> designers tend to write their VHDL very specific for one family. Than
> it will be hard to get the same performance from another device.
> 
> I.e. does the compiled design make use of the IO cell? Switching this
> option of can save quite some time (Clock to Out).
> 
> Regards,
> 
> Luc

Actually I test with an out-of-the-box t80 design...

I know that Altera Quartus does some good job in
using RAM blocks instead of registers automatically
since version 4.1 or 4.2 8and old 2.2 I think) whereas
the backend tools in ispLever and Actel Libero don't.

A simple comparison would be to use a small binary
counter and see how fast they can go...


rick

Article: 86018
Subject: Re: Design tools comparison between Xilinx, Altera and Lattice for FPGA designs
From: "amko" <sinebrate@yahoo.com>
Date: 20 Jun 2005 13:28:55 -0700
Links: << >>  << T >>  << A >>
ISE Webpack is definitly better choice than Altera Web Edition. Web
Edition does not generate image files (pof. and sof.). In additional
ISE Webpcack has minimal limitations and only big disadvantage is core
generator which is not included in the  Webpack. It means you can not
use Xilinx FIFO, DP RAM,... but anywhere you have PLL (DCM)...
Synthisiser XST is also very good and in most case you dont need it
Leonardo or Synplify...
Free Simulator tool (Xilinx Modelsim ) is also avaiable with  ISE
Webpack....

In the other words you can do it much more with  ISE Webpack...

Regards ,

Amir


Article: 86019
Subject: Re: FPGAs: Where will they go?
From: Rene Tschaggelar <none@none.net>
Date: Mon, 20 Jun 2005 22:32:34 +0200
Links: << >>  << T >>  << A >>
lovesinghal wrote:

> If you are not as optimistic about FPGAs as I am sounding, what major
> bottlenecks do you think will check FPGA growth?
> 
> I am starting my PhD in FPGAs (and looking for topics of research!?!)
> and thus interested in knowing the future uses of FPGAs.

You're basing a PhD on a few guys comments in a newsgroup ?
Impressive...

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

Article: 86020
Subject: Re: Spartan 3 availability
From: "xilinx_user" <barrinst@ix.netcom.com>
Date: 20 Jun 2005 13:37:10 -0700
Links: << >>  << T >>  << A >>
Yes. I think we owe a big round of thanks to Peter Alfke and his crew
for making this happen.

Mike Harrison wrote:
> Further to recent discussiuons here, I Just noticed That S3s have appeared in the Xilinx web store.
> A few are even shown as in stock....


Article: 86021
Subject: Re: : Parts Back on Xilinx Online Store (www.xilinx.com/store)
From: "xilinx_user" <barrinst@ix.netcom.com>
Date: 20 Jun 2005 13:40:35 -0700
Links: << >>  << T >>  << A >>
A big thanks for everyone at Xilinx to make this happen. I can now be
comfident in moving forward with my design.


Article: 86022
Subject: Re: Design tools comparison between Xilinx, Altera and Lattice for FPGA designs
From: kempaj@yahoo.com
Date: 20 Jun 2005 13:43:18 -0700
Links: << >>  << T >>  << A >>
Actually Quartus web edition does allow you to generate programming
files, for certain Altera devices. An exact list can be seen here:
http://www.altera.com/products/software/products/quartus2web/sof-quarwebmain.html

Also there is no limitation to the cores you can use with the free
Altera tools.. if you want a  RAM you've got it.. if you want a PLL
you've got it. The SOPC Builder system integration/bus generation tool
is included for free.

There is also the Nios II evaluation download that includes a lot of
free-IP,  and a time-limited (or unlimited-time-but-tethered-to-host)
Nios II core for your evaluation.

Jesse Kempa
Altera
jkempa -at- altera --dot-- com


Article: 86023
Subject: Re: Design tools comparison between Xilinx, Altera and Lattice for
From: Jedi <me@aol.com>
Date: Mon, 20 Jun 2005 20:58:13 GMT
Links: << >>  << T >>  << A >>
Luc wrote:
> Guys,
> 
> I'm trying to compare Altera, Xilinx and Lattice tools (free version)
> Can Xilinx, Altera and Lattice supporters comment?
> I found:
> Lattice starter has included Leonardo/Precision RTL and Synplify, no
> ModelSim
> Xilinx ISE WebPack : XST, no Leonardo/Precision, no Synplify, no
> ModelSim
> Altera QuartusII Web Edition: support for Synplify, Precision and
> Modelsim?
> 
> I know it's a simple comparison, but I would like to be clear on this.

May I suggest also another approach?

Do a comparison of the distributors as well...

Here in this country (live abroad now for 3 years ;o) the best support
I got was from:

- Altera distributor
- Actel distributor
- Lattice (direct country office)

Worst experience with Xilinx distributor...after 2 - 3 years
of hearing them always talking that they are better than Altera.

At the end the stomach decides as well...and I prefer the distributor
who can provide good support/samples...as nowadays most support is
forwarded to local FAE's.


rick

Article: 86024
Subject: Re: FPGAs: Where will they go?
From: Kris Vorwerk <kpvorwer@engmail.uwaterloo.ca>
Date: Mon, 20 Jun 2005 17:18:32 -0400
Links: << >>  << T >>  << A >>
> I am starting my PhD in FPGAs (and looking for topics of research!?!)
> and thus interested in knowing the future uses of FPGAs.


Some well-thought-out responses to the majority of the questions that
you've posed can be found in panel sessions or keynote addresses in
conferences like FPGA and FPL from the past couple of years.  (For some
reason, keynote speakers at these conferences just *love* to rattle the
"ASIC vs. FPGA" debate.)

As a PhD student, you should have access to the speakers' PowerPoint
slides through your university ...


cheers,
Kris



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