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Messages from 90875

Article: 90875
Subject: verilog code
From: "hirenshah.05@gmail.com" <hirenshah.05@gmail.com>
Date: 24 Oct 2005 09:09:32 -0700
Links: << >>  << T >>  << A >>
Hi,

I am new in VLSI field. I have written one verilog code to calulate
evenparity of two input data.

EX: input data1
     input data2
     output eparity
     output overflow
  output code

whenevr either data1 or data2 are with evenparity increment eparity, if
eparity reaches FF , increment overflow.  if data1 = AA or data2 = 55
increment code.

following is code which i have written , i just want to know is this
efficient code, or i can still improve code.

-------------------------------------------------------------------


module assg (clock,clear,reset, datain1, datain2,
evenparity,overflow,greycode);


input clock;
input reset;
input clear;
input  [7:0] datain1;
input  [7:0] datain2;

output [7:0] evenparity;
output overflow;
output [7:0] greycode;
reg [7:0] evenparity;
reg overflow;
reg [7:0] greycode;
always @(posedge clock or negedge reset)

begin
if(!reset)
begin
evenparity=0;
overflow=0;
greycode=0;
end
else
begin
if(clear)
   begin
   	evenparity = 0;
   	greycode = 0;
   	overflow = 0;
   end
   else
   begin
    if(~^datain1) evenparity= evenparity + 1;
    if(~^datain2) evenparity= evenparity + 1;
   if(evenparity==8'b11111111) overflow = overflow + 1;
   if(datain1==8'b10101010) greycode = greycode + 1;
    if(datain2==8'b01010101) greycode = greycode + 1;
  end
  end

end


endmodule

-------------------------------------------------------------------


if anyone can suggest any improvement in design


Article: 90876
Subject: Re: SoC Processor design at gate level for edu
From: "Antti Lukats" <antti@openchip.org>
Date: Mon, 24 Oct 2005 18:38:21 +0200
Links: << >>  << T >>  << A >>
"raph" <raphael.ponsard@ac-grenoble.fr> schrieb im Newsbeitrag 
news:435ca17a$0$20868$636a55ce@news.free.fr...
> Hi Folks,
>
> For educational purpose (Von Neumann demo), I am looking for a System On 
> Chip Processor :
> - very simple
> - gate level design (no VHDL, only gates AND,NAND, and low level boxes as 
> shifter, ...)
> - running system (spartan 3 or other low cost xilinx or altera demo board)
>
> regards
> Raph

there is no such thing, not directly.

some OOOLD desing may have been done on the level you wish, but none of 
those designs has been ported to any modern FPGA as S-3.

what means you are stick to use VHDL code - BTW Xilinx picoblaze is pretty 
low level already, still being in VHDL

and... a shifter is not generically a low level box. low level primitives 
are LUT and FF, pretty much everthing else is higher level already. xilinx 
SRL16 od low level shiftrt but is in xilinx only. there is no vendor neutral 
low level box as shifter (shift register).

so if you need basic gates only then you need to translate some HDL code 
into the primitives...

antti 



Article: 90877
Subject: Re: verilog code
From: "JJ" <johnjakson@gmail.com>
Date: 24 Oct 2005 10:02:06 -0700
Links: << >>  << T >>  << A >>
I won't even try to understand that.

Do you know about the Verilog reduction operators.

I believe that for a wire w of any width, ^w gives the total xor over
all bits, same for most bitwise operators. Kind of APLish, can be very
powerful, should synthesize.

Read the language book again.

And please everyone, I is spelt uppercase, and my English grades were
not that good, even I can manage that.

John


Article: 90878
Subject: Re: verilog code
From: "John_H" <johnhandwork@mail.com>
Date: Mon, 24 Oct 2005 17:32:17 GMT
Links: << >>  << T >>  << A >>
Okay, I'll add some *constructive* criticism since you haven't gotten any 
yet.

1) You're using blocking operators (=) rather than non-blocking operators 
(<=) which can give you unexpected results if your RTL is good hardware 
code.  The blocking operator will make the assignments in sequence within 
your always block such that {begin b = a; c = b; end} will result in c 
getting the value of a on every clock.

2) It may be "legal" to have different if statements to assign a single 
variable, but it's much cleaner and less prone to error to code with if/else 
if/else structures.  Do you intend for evenparity to increment by 2 when 
both data1 and data2 have even parity?  If so, the blocking operators are 
doing the right thing but a simple adder might be a better approach: to 
count both, evenparity <= evenparity + ~^data1 + ~^data2;.

Aside from those comments, nothing is glaring.  I find it convenient to 
stick to indenting guidelines to keep the nested if/for/always blocks 
straight in my mind.

- John_H


<hirenshah.05@gmail.com> wrote in message 
news:1130170172.495166.168010@g43g2000cwa.googlegroups.com...
> Hi,
>
> I am new in VLSI field. I have written one verilog code to calulate
> evenparity of two input data.
>
> EX: input data1
>     input data2
>     output eparity
>     output overflow
>  output code
>
> whenevr either data1 or data2 are with evenparity increment eparity, if
> eparity reaches FF , increment overflow.  if data1 = AA or data2 = 55
> increment code.
>
> following is code which i have written , i just want to know is this
> efficient code, or i can still improve code.
>
> -------------------------------------------------------------------
>
>
> module assg (clock,clear,reset, datain1, datain2,
> evenparity,overflow,greycode);
>
>
> input clock;
> input reset;
> input clear;
> input  [7:0] datain1;
> input  [7:0] datain2;
>
> output [7:0] evenparity;
> output overflow;
> output [7:0] greycode;
> reg [7:0] evenparity;
> reg overflow;
> reg [7:0] greycode;
> always @(posedge clock or negedge reset)
>
> begin
> if(!reset)
> begin
> evenparity=0;
> overflow=0;
> greycode=0;
> end
> else
> begin
> if(clear)
>   begin
>   evenparity = 0;
>   greycode = 0;
>   overflow = 0;
>   end
>   else
>   begin
>    if(~^datain1) evenparity= evenparity + 1;
>    if(~^datain2) evenparity= evenparity + 1;
>   if(evenparity==8'b11111111) overflow = overflow + 1;
>   if(datain1==8'b10101010) greycode = greycode + 1;
>    if(datain2==8'b01010101) greycode = greycode + 1;
>  end
>  end
>
> end
>
>
> endmodule
>
> -------------------------------------------------------------------
>
>
> if anyone can suggest any improvement in design
> 



Article: 90879
Subject: Re: low power design and unused i/os
From: "fpgabuilder" <fpgabuilder-news@yahoo.com>
Date: 24 Oct 2005 10:33:05 -0700
Links: << >>  << T >>  << A >>
Thanks.  Can you please elaborate on "by using a NAND instead of an
inverter"?  I am guessing that you are implying that the IO would be
designed in this fashion?  Or do you mean to actually write rtl logic
to target into the fpga?


Article: 90880
Subject: Re: evaluation edk in Spartan-3 starter kit
From: "Leon" <leon_heller@hotmail.com>
Date: 24 Oct 2005 11:21:27 -0700
Links: << >>  << T >>  << A >>
You can use it with the free WebPack software. I bought mine from
Digilent (they actually make them for Xilinx) with a 400 S3 and it
didn't come with any software.

Leon


Article: 90881
Subject: Re: SoC Processor design at gate level for edu
From: Jim Granville <no.spam@designtools.co.nz>
Date: Tue, 25 Oct 2005 07:45:38 +1300
Links: << >>  << T >>  << A >>
raph wrote:
> Hi Folks,
> 
> For educational purpose (Von Neumann demo), I am looking for a System On 
> Chip Processor :
> - very simple
> - gate level design (no VHDL, only gates AND,NAND, and low level boxes 
> as shifter, ...)
> - running system (spartan 3 or other low cost xilinx or altera demo board)

The second one is quite an ask....
I'd suggest you look at the Mico8 core from Lattice, which is open 
source & can run on their MachXO devices.

You can then
a) recode the HDL, so it 'reads' to the students as lower level.
b) rewrite the HDL in ABEL, which is more direct HW mapping
   ( but is less portable - IIRC Lattice and Xilinx still have Abel,
& unclear if that is more than CPLD only tool flow )

Xilinx Abel flows, last time I checked, also output
a low level VHDL, which can also be used for teaching/and or
learning how to write low level HDL :)

-jg


Article: 90882
Subject: Re: RS232 Uart for Virtex-II Pro
From: Ray Andraka <ray@andraka.com>
Date: Mon, 24 Oct 2005 15:34:52 -0400
Links: << >>  << T >>  << A >>
Eric wrote:

>Does anyone know if there's a ready-to-use rs232 uart in vhdl for the
>Virtex-II pro fpga? We have done some designs in ISE, and hope to
>display results in a terminal window. Thanks.
>
>  
>
If it is transmit only, the design is very simple:  you need a shift 
register that gets reloaded every 10/11 bit times with the byte, and 
fixed start and stop bits.  The shift enable for the shift register has 
to be at the correct timing for the baud rate.  For that, you can use a 
DDFS, which is nothing more than an accumulator which adds a fixed 
increment to itself on each clock   The msb of the accumulator is your 
baud clock: synchronous edge detect that to obtain a shift enable for 
the shift register and your bit counter.  Here's a vhdl snippet:

             --DDFS generates bit clock from 50M clock
            ddfs<= ddfs + to_unsigned(ddfs_inc,20);     
            ddfs_z<= ddfs(ddfs'left);
            ddfs_re<= ddfs(ddfs'left) and not ddfs_z; --rising edge of  
bit clock
                  
            --UART transmitter
            if ddfs_re='1' then
                 --bit counter downcounts 9 downto -1
                if ubit(4)='1' or stopped='1' then --negative
                    ubit<= "01001";
                else
                    ubit<= ubit-1;
                end if;
               
                --uart shift register       
                --data output is start bit then data lsb first then 2 
stop bits.  Assuming driver inverts
                if ubit(4)='1' then
                    tx_register<= "11" & read_data & '0';
                else
                    tx_register<= '1' & tx_register(10 downto 1);
                end if;
            end if;

            serial_data_out<= tx_register(0);

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 90883
Subject: Re: evaluation edk in Spartan-3 starter kit
From: aholtzma@gmail.com
Date: 24 Oct 2005 12:47:14 -0700
Links: << >>  << T >>  << A >>
Indeed, you can use WebPack. However, I bought the board to try the
EDK, for which there is no free download.

cheers,
aaron


Article: 90884
Subject: Re: RPM reference for xilinx
From: Ray Andraka <ray@andraka.com>
Date: Mon, 24 Oct 2005 15:47:56 -0400
Links: << >>  << T >>  << A >>
Rick North wrote:

>Thank you for the pointers. Do you cover any of this in your
>forthcomming book?
>/rick
>
>  
>
I do, but not as a step by step treatment because the steps would likely 
be obsolete due to new versions of the tools by the time the book hits 
the bookshelves.

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 90885
Subject: Re: SoC Processor design at gate level for edu
From: "Kunal" <kunal.shenoy@gmail.com>
Date: 24 Oct 2005 12:48:07 -0700
Links: << >>  << T >>  << A >>
Once you synthesize you vhdl/verilog coded processor, view the rtl
schematic or technology schematic. That will give you a good enough
representation of the HDL in basic blocks / Xilinx primitives. If you
double click on a single LUT in the technology schematic, it'll give
you a gate implementation representation, k-map, and truth table.
RTL schematic / technology schematic can be viewed by double clicking
the 'view RTL schematic' / 'view technology schematic' in the process
window in ISE.
The schematic can be difficult to trace for larger designs. Synplicity
gives more readable schematics.

Kunal


Article: 90886
Subject: Re: evaluation edk in Spartan-3 starter kit
From: aholtzma@gmail.com
Date: 24 Oct 2005 12:49:02 -0700
Links: << >>  << T >>  << A >>
There is no download location for EDK on linux or anything else (as far
as I can tell, I would love to be proven wrong).

cheers,
aaron


Article: 90887
Subject: a few questions
From: Gert Baars <g.baars13@chello.nl>
Date: Mon, 24 Oct 2005 23:24:54 +0200
Links: << >>  << T >>  << A >>
Hello,

I am experienced with Electronics and programming but never had anything
to do with FPGA. I want to start with an FPGA from Altera and have 
installed their Quartus II.
Now my guess is I have to learn a language like VHDL or Verilog. What
language is easiest/fastest to learn or what other programming-language
can you recommend?

All hints/advice appreciated,

Gert Baars

Article: 90888
Subject: Re: a few questions
From: Jan Panteltje <pNaonStpealmtje@yahoo.com>
Date: Mon, 24 Oct 2005 22:18:37 GMT
Links: << >>  << T >>  << A >>
On a sunny day (Mon, 24 Oct 2005 23:24:54 +0200) it happened Gert Baars
<g.baars13@chello.nl> wrote in <b212$435d5121$3ec235b6$29794@news.chello.nl>:

>Hello,
>
>I am experienced with Electronics and programming but never had anything
>to do with FPGA. I want to start with an FPGA from Altera and have 
>installed their Quartus II.
>Now my guess is I have to learn a language like VHDL or Verilog. What
>language is easiest/fastest to learn or what other programming-language
>can you recommend?
>
>All hints/advice appreciated,
>
>Gert Baars
If you know C, verilog looks a bit like it (but is not).
Always think hardware, not procedural languages.
There are however C to HDL converters.

_________________________________________
Usenet Zone Free Binaries Usenet Server
More than 140,000 groups
Unlimited download
http://www.usenetzone.com to open account

Article: 90889
Subject: Re: a few questions
From: Phil Hays <Spampostmaster@comcast.net>
Date: Mon, 24 Oct 2005 15:22:56 -0700
Links: << >>  << T >>  << A >>
Gert Baars wrote:

>I am experienced with Electronics and programming but never had anything
>to do with FPGA. I want to start with an FPGA from Altera and have 
>installed their Quartus II.
>Now my guess is I have to learn a language like VHDL or Verilog. What
>language is easiest/fastest to learn or what other programming-language
>can you recommend?

VHDL.

Having said that, there is almost as strong of case for Verilog.  VHDL
is somewhat harder to learn the basics of, and Verilog is harder to
master.  The area under the learning curves is similar.  There have
been religious wars over this in the past.  At minimum, learning how
to read both is good.

One hint, don't think of it as programming.  You are specifying
hardware.  Try to work out what hardware will implement what you write
as you write it.


-- 
Phil Hays to reply solve: phil_hays at not(coldmail) dot com  
 If not cold then hot


Article: 90890
Subject: Re: a few questions
From: Gert Baars <g.baars13@chello.nl>
Date: Tue, 25 Oct 2005 01:10:00 +0200
Links: << >>  << T >>  << A >>
Phil Hays wrote:
> Gert Baars wrote:
> 
> 
>>I am experienced with Electronics and programming but never had anything
>>to do with FPGA. I want to start with an FPGA from Altera and have 
>>installed their Quartus II.
>>Now my guess is I have to learn a language like VHDL or Verilog. What
>>language is easiest/fastest to learn or what other programming-language
>>can you recommend?
> 
> 
> VHDL.
> 
> Having said that, there is almost as strong of case for Verilog.  VHDL
> is somewhat harder to learn the basics of, and Verilog is harder to
> master.  The area under the learning curves is similar.  There have
> been religious wars over this in the past.  At minimum, learning how
> to read both is good.
> 
> One hint, don't think of it as programming.  You are specifying
> hardware.  Try to work out what hardware will implement what you write
> as you write it.
> 
> 


Fine, thanks for reply. I am aware that VHDL is a matter of specifying.
If you can recommend documents or books, please don't hesitate.


Article: 90891
Subject: Re: using i2c core
From: "John_H" <johnhandwork@mail.com>
Date: Mon, 24 Oct 2005 23:34:01 GMT
Links: << >>  << T >>  << A >>
So I asked if you were sure you had your output hooked up to the .i and the 
input hooked up to the .o for the IOBUF and I believe that was where you 
started talking about "not enough signals."

It's easy to get confused and hook the .o to the output and the .i to the 
input which would result in complaints from the tools.


"CMOS" <manusha@millenniumit.com> wrote in message 
news:1129958142.375163.39160@g43g2000cwa.googlegroups.com...
> hi,
> sure, that is exactly what im doing ( using the IOBUF) . i just
> explained the structure of IOBUF, as it looks like one OBUF and one
> IBUF connected together.
>
> the problem with the IOBUF is translation error "ERROR:924". ( which
> made me to try various other combinations. ) .
> i dont even understand that error and there are no xilinx answers
> associated with it.
>
> CMOS
> 



Article: 90892
Subject: Re: Doubt in using CD22M3494
From: alan@nishioka.com
Date: 24 Oct 2005 16:44:01 -0700
Links: << >>  << T >>  << A >>
I have never used this part, but from the datasheet:
http://www.intersil.com/data/fn/fn2793.pdf


praveen.kantharajapura@gmail.com wrote:
>  We are using CD22M3494(16 X 8 audio switch).Which has 128 switches.
>  Now initially i connect switch X0 to switch Y0 , this particular
> switch is closed(commected) now.
> Now if i need to connect X1 to Y0 , should i open(disconnect) the
> connection between X0 and Y0.

Yes, you need to break the connection first.


> What happens if i do not open the switch
> X0 to Y0.
> Will the Y0 output be superimposed version of X0 and X1.

You will short X0 to X1 to Y0.  If the source impedance is low (like a
digital cmos output) you could damage the source or the switch.  If the
source impedance is high (like a capacitor coupled audio output) it may
simply superimpose the signals.

Alan Nishioka
alan@nishioka.com


Article: 90893
Subject: Re: 24 to 32 8-bit PWM outputs
From: David Brooks <davebXXX@iinet.net.au>
Date: Tue, 25 Oct 2005 07:47:05 +0800
Links: << >>  << T >>  << A >>
Can you further tell us:
1. What pulse repetition frequency you want
2. How many bits accuracy in the duty cycle
3. Must the outputs be synchronised?
4. Are they to drive model-control servos? (Those often respond not to 
the average energy in the signal, but to the actual width. You can have 
a very long interval between pulses, & still have them work).

Emtech wrote:
> I have an application where I need to implement 24 or up to 32 PWM outputs 
> (8-bit) and
> am considering using a small CPLD to handle the PWMs instead of doing it all 
> in software.
> This does add a CPLD to the design, but frees the micro do to other things.
> 
> Any recommendations on the CPLD & CPLD size without completing the VHDL 
> first?
> 
> 

Article: 90894
Subject: Re: a few questions
From: Tim Wescott <tim@seemywebsite.com>
Date: Mon, 24 Oct 2005 17:22:20 -0700
Links: << >>  << T >>  << A >>
Gert Baars wrote:

> Phil Hays wrote:
> 
>> Gert Baars wrote:
>>
>>
>>> I am experienced with Electronics and programming but never had anything
>>> to do with FPGA. I want to start with an FPGA from Altera and have 
>>> installed their Quartus II.
>>> Now my guess is I have to learn a language like VHDL or Verilog. What
>>> language is easiest/fastest to learn or what other programming-language
>>> can you recommend?
>>
>>
>>
>> VHDL.
>>
>> Having said that, there is almost as strong of case for Verilog.  VHDL
>> is somewhat harder to learn the basics of, and Verilog is harder to
>> master.  The area under the learning curves is similar.  There have
>> been religious wars over this in the past.  At minimum, learning how
>> to read both is good.
>>
>> One hint, don't think of it as programming.  You are specifying
>> hardware.  Try to work out what hardware will implement what you write
>> as you write it.
>>
>>
> 
> 
> Fine, thanks for reply. I am aware that VHDL is a matter of specifying.
> If you can recommend documents or books, please don't hesitate.
> 
"The Verilog Hardware Description Language" by Thomas & Moorby is fair 
to good.  It describes the language, it's written in a tutorial format, 
but unless you have a pointer to 
http://www.sutherland-hdl.com/on-line_ref_guide/vlog_ref_top.html you'll 
be constantly frustrated.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Article: 90895
Subject: Re: MAC Architectures
From: Rich Grise <rich@example.net>
Date: Tue, 25 Oct 2005 00:39:00 GMT
Links: << >>  << T >>  << A >>
On Mon, 24 Oct 2005 13:41:27 +1000, Alex Gibson wrote:

[whole bunch really useful Xilinx links snipped :-) ]

Thanks! This is a keeper!

Cheers!
Rich



Article: 90896
Subject: Xilinx ML403 Many warnings
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Mon, 24 Oct 2005 18:00:18 -0700
Links: << >>  << T >>  << A >>
Hello,

I thought I would load this ML403 board with a program that turns an LED on, 
which I did, but on the way I encountered numerous Warnings saying Unknown 
General Data for parts, or sites, that I never instantiated.  How do I turn 
these warnings off? I used the ISE 7.1 software and used Impact to download 
a .BIT file.

Brad Smallridge
aivision.com



Article: 90897
Subject: Re: a few questions
From: "Gary Pace" <xxx@yyy.com>
Date: Tue, 25 Oct 2005 01:26:29 GMT
Links: << >>  << T >>  << A >>
"Gert Baars" <g.baars13@chello.nl> wrote in message 
news:b212$435d5121$3ec235b6$29794@news.chello.nl...
> Hello,
>
> I am experienced with Electronics and programming but never had anything
> to do with FPGA. I want to start with an FPGA from Altera and have 
> installed their Quartus II.
> Now my guess is I have to learn a language like VHDL or Verilog. What
> language is easiest/fastest to learn or what other programming-language
> can you recommend?
>
> All hints/advice appreciated,
>
> Gert Baars

Gert :

I'm not saying you should - but you could use schematic capture in Quartus.

Using the MegaWizard (which hides some parameterized HDL behind schematic 
symbols), hierarchical schematics and a well thought out library you can get 
some complex designs in a reasonably concise (and beautifully 
self-documenting form)

I know there are a million and one reasons not do this - but you could.





Article: 90898
Subject: Xilinx ISERDES
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Mon, 24 Oct 2005 19:54:19 -0700
Links: << >>  << T >>  << A >>
How many ISERDES are there in an FX12?



Article: 90899
Subject: Re: Xilinx ISERDES
From: "unfrostedpoptart" <david@therogoffs.com>
Date: 24 Oct 2005 20:17:36 -0700
Links: << >>  << T >>  << A >>
http://www.xilinx.com/products/tables/selector/index.htm




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1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

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