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Messages from 92100

Article: 92100
Subject: Re: Patient Monitors: Reading RS232 output w/ an FPGA
From: Kolja Sulimma <news@sulimma.de>
Date: Tue, 22 Nov 2005 18:10:22 +0100
Links: << >>  << T >>  << A >>
Mark schrieb:
> We currently use a software application (called DataCaptor) to read the MIB-RS232 output of a patient monitor (the Philips MP30). We are considering replacing the DataCaptor software with an FPGA but this has probably never been attempted.
> 
> Does anyone have any experience interfacing an FPGA to patient monitors?

While an FPGA is more fun, a uC ist probably a lot more useful unless
another part of your application requires an FPGA.

Kolja Sulimma

Article: 92101
Subject: Re: Patient Monitors: Reading RS232 output w/ an FPGA
From: "Andy Peters" <Bassman59a@yahoo.com>
Date: 22 Nov 2005 09:32:28 -0800
Links: << >>  << T >>  << A >>

Mark wrote:
> We currently use a software application (called DataCaptor) to read the MIB-RS232 output of a patient monitor (the Philips MP30). We are considering replacing the DataCaptor software with an FPGA but this has probably never been attempted.
>
> Does anyone have any experience interfacing an FPGA to patient monitors?

I'm not quite sure how you can replace software ("DataCaptor software
application") with hardware (the FPGA).

Perhaps you can rephrase this?

=a


Article: 92102
Subject: Re: How do I find the datasheet of this device "TIOPA 690 3BZL9"?
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 22 Nov 2005 09:35:04 -0800
Links: << >>  << T >>  << A >>

"Simon Peacock" <simon$actrix.co.nz> wrote in message 
news:4382ea2a$1@news2.actrix.gen.nz...
> What happened to the text on the front of the chip.. if its been "erased"
> then you are trying to reverse engineer a design.. that will void the
> warrantee :-)
>
Voiding the warrantee could be much more serious to his own health than 
reverse engineering the part!

http://www.answers.com/warrantee

;-)

Cheers, Syms. 



Article: 92103
Subject: Re: Newbie: Problems with clocks
From: "Andy Peters" <Bassman59a@yahoo.com>
Date: 22 Nov 2005 09:46:57 -0800
Links: << >>  << T >>  << A >>
Andreas wrote:
> Hello,
> I just got a new FPGA board (from Avnet, Xilinx Virtex4). The problem is
> that I never programmend a FPGA before. I use VHDL for programming and
> Precision from Mentor for synthesis. Xilinx ISE 7.1 is used for
> place-and-route. On the FPGA board is a push button. Within my VHDL code I
> defined a process, which is sensitive to the rising edge of the signal
> associated with that push button (I want to know, when the button is
> pushed).
>
>         pb_proc: process (push_button) is
>         begin
>          if push_button'event and push_button='1' then
>           ....
>
> The problem is, that Precision recognizes that signal and the associated pad
> as a clock input and the during place-and-route operation, ISE produces the
> following error message:
>
> ERROR:Place:645 - A clock IOB  clock component is not placed at an optimal
> clock IOB site  The clock IOB component <push_button> is placed at site
> IOB_X2Y112. The clock IO site can use the fast path between the IO and the
> Clock buffer/GCLK if the IOB is placed in the master Clock IOB Site. If
> this sub optimal condition is acceptable for this design you may set the
> environmentvariable XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING to demote this
> message to a WARNING and allow your design to continue.

You got this error because your VHDL instantiates a flip-flop whose
clock is the signal push_button, and your constraints told the tools to
put the signal push_button onto a pin that's not a global clock pin.

You should spend some quality time with the XST manual, especially the
sections that detail how certain structures are inferred from VHDL.

> My questions are:
> 1) Is every input signal, to whose signal flanks the VHDL code is sensitive
> to, automatically a clock?

I'm not quite sure what you mean by "whose signal flanks the VHDL code
is sensitive to."  My English parser threw a rod on that one.

> What's the best way to prevent this during synthesis? Do I actually have to prevent it?

As I said above, your VHDL process above creates a clocked flip-flop.
Write proper code and the error will go away.

> 2) How can I set the environmentvariable XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING?
> I'm using the Linux version of ISE and using ISE from within Precision. I'm
> sure that there is a menu entry to set that variable, but I don't start ISE
> direct, but from within Precision. So I'd like to know in which
> configuration file I can place that variable setting. Also I'd like to know
> which additional environmentvaribles exist. I couldn't find a list or
> anything in the documentation.

Environment variables can be set from the shell command-line, or
through a .bashrc or .cshrc or other script.  The syntax is
shell-dependent, so you should probably check the documentation for
your particular shell.


> P.S.: another question of topi: When I setup my Design, I have to chose
> technology(Virtex-IV), Device(4vlx25ff668) and Speed Grade(-10 or -11).
> Which speed grade do I have to choose?

Choose the speed grade that matches the device installed on your board.

> Does the board support -10 and -11?

Dunno, look at the chip, or read the documents that came with your
board.

> Whats better? What is the speed grade exactly?

Speed grade roughly indicates the FPGA's maximum speed.  Read the
Virtex docs to determine whether the higher number (-11 versus -10) is
faster or slower.  If your design doesn't require the highest clock
frequency, you can save money by choosing a slower part.  This is
relevant if you're building your own boards.

> Do I have to/Can I determine the supported speed grades of my board somehow?

You must know the speed grade of the parts with which you're designing.
 And to determine the speed grade of the part on your board, RTFM.

-a


Article: 92104
Subject: Re: Patient Monitors: Reading RS232 output w/ an FPGA
From: Duane Clark <dclark@junkmail.com>
Date: Tue, 22 Nov 2005 18:06:52 GMT
Links: << >>  << T >>  << A >>
Andy Peters wrote:
> Mark wrote:
>> We currently use a software application (called DataCaptor) to read
>> the MIB-RS232 output of a patient monitor (the Philips MP30). We
>> are considering replacing the DataCaptor software with an FPGA but
>> this has probably never been attempted.
>> 
>> Does anyone have any experience interfacing an FPGA to patient
>> monitors?
> 
> I'm not quite sure how you can replace software ("DataCaptor software
>  application") with hardware (the FPGA).
> 

Assuming the data monitor serial protocol is not terribly complicated, 
it is fairly easy to write FPGA code that will send commands, and handle 
responses and returned data. On the other hand, it is not real clear in 
this case how this is intended to be used. And it might be a bit more 
involved proving to whoever that it meets patient safety criteria (I'm 
assuming some such thing will be required).

Article: 92105
Subject: Re: Quartus Problem
From: Mike Treseler <mike_treseler@comcast.net>
Date: Tue, 22 Nov 2005 10:13:52 -0800
Links: << >>  << T >>  << A >>
Manfred Balik wrote:
> I have changed from Quartus II 4.2 to 5.1. Now I am getting much more 
> warnings ;-). My design works normally but the warning of the fitter I do 
> not understand:

To rule out a logical problem, I would run:
  Processing, Start, Start Analysis and Synthesis
And when that is done:
   Tools, RTL viewer

If this looks clean I would open a case with Altera.

     -- Mike Treseler

Article: 92106
Subject: Xst optimizes almost everything away
From: Adrian Knoth <adi@thur.de>
Date: Tue, 22 Nov 2005 18:14:45 +0000 (UTC)
Links: << >>  << T >>  << A >>
Hi,

this is my first real VHDL project, so it's perhaps more a
beginner's question than a problem with Xst.

I have some components for my module two_pc, but when I
translate it in ISE, both "translate" and "Place&Route"
have warnings (system report says 308 warnings).

The problem: xst claims that some signals are connected
but never used. For one component it even says there
isn't any connection:

Xst:524 - All outputs of the instance <bild> of the block
          <bildspeicher> are unconnected in block <two_pc>.

I don't think that's true:

      bild : bildspeicher
      port map (reset => reset,
                                         clk => clk_i,
                                         addra => bildaddr1,
                                         addrb => bildaddr2,
                                         DOA => bilddaten1,
                                         DOB => bilddaten2
       );


(DOA and DOB are outputs) and there is a process using them:

   chooser : process (clk_i, reset) --, update_input)
           variable links,rechts : std_logic_vector (31 downto 0);
        begin
           if (reset='1') then
              input <= (others => '0');
           elsif (clk_i'event and clk_i='1') then
              if (update_input'event and update_input='1') then
                  rechts := bilddaten1;
                  case spalte is
                         when "00" =>                            
                            input (31) <= '0';
                            input (30 downto 24) <= rechts (31 downto 25);
                            input (23 downto 16) <= rechts (26 downto 19);
                            input (15 downto 08) <= rechts (20 downto 13);
                            input (07 downto 00) <= rechts (14 downto 07);
                       when "01" =>
                            bildaddr2 (1 downto 0) <= "00";
                            links := bilddaten2;
                            input (31 downto 24) <= links (8 downto 1);
                            input (23 downto 21) <= links (2 downto 0);
                            input (20 downto 16) <= bilddaten1 (31 downto 27);
                            input (15 downto 08) <= bilddaten1 (28 downto 21);
                            input (7 downto 0)  <= bilddaten1 (22 downto 15);
                       when "10" =>
                            bildaddr2 (1 downto 0) <= "01";
                            links := bilddaten2;
                            input (31 downto 24) <= links (16 downto 9);
                            input (23 downto 16) <= links (10 downto 3);
                            input (15 downto 11) <= links ( 4 downto 0);
                            input (10 downto  8) <= bilddaten1 (31 downto 29);
                            input ( 7 downto  0) <= bilddaten1 (30 downto 23);
                        when "11" =>
                            bildaddr2 (1 downto 0) <= "10";
                            links := bilddaten2;
                            input (31 downto 24) <= links (24 downto 17);
                            input (23 downto 16) <= links (18 downto 11);
                            input (15 downto  8) <= links (12 downto  5);
                            input (7 downto 1)  <= links (6 downto 0);
                            input (0  downto 0)   <= bilddaten1 (31 downto 31);
                       when others => input <= (others => '0');
                    end case;
                 end if;
                end if;
        end process chooser;

There are more of such "warnings":

Xst:1291 - FF/Latch <outbuf_D_7> is unconnected in block <two_pc>.

(and _D_6 .. -D_0, 8bit-std-logic-vector)

but I have:

   output_ff : process (clk_i, reset)
        begin
           if (reset='1') then
                        outbuf_A <= (others => '0');
                        outbuf_B <= (others => '0');
                        outbuf_C <= (others => '0');
                        outbuf_D <= (others => '0');
                elsif (clk_i'event and clk_i='1') then
                   if (write_A = '1') then
                          outbuf_A <= output_A;
                          outbuf_B <= output_B;
                          outbuf_C <= output_C;
                          outbuf_D <= output_D;
                        end if;
                end if;
        end process output_ff;

and

        output (31 downto 24) <= outbuf_A (7 downto 0);
        output (23 downto 16) <= outbuf_B (7 downto 0);
        output (15 downto 8) <= outbuf_C (7 downto 0);
        output (7 downto 0) <= outbuf_D (7 downto 0);

Xst: FF/Latch  <inbuf_A_6> (without init value) has a constant value of 0 
     in block <two_pc>.

   input_ff : process (clk_i, reset)
        begin
           if (reset='1') then
                        inbuf_A <= (others => '0');
                        inbuf_B <= (others => '0');
                        inbuf_C <= (others => '0');
                        inbuf_D <= (others => '0');
           elsif (clk_i'event and clk_i='1') then
               if (read_A = '1') then
                        inbuf_A <= input (31 downto 24);
                        inbuf_B <= input (23 downto 16);
                        inbuf_C <= input (15 downto 8);
                        inbuf_D <= input (7 downto 0);
                  end if;
                end if;
        end process input_ff;


(input itself is assigned by the chooser-process).

All my important logic gets optimized away ;) What's the
problem? All signals in question (for which Xst claims
they are never assigned) are assigned by processes.

TIA

-- 
mail: adi@thur.de  	http://adi.thur.de	PGP: v2-key via keyserver

Geld allein macht nicht glücklich - es muß dir auch gehören

Article: 92107
Subject: Disabling Xilinx clock enable usage...
From: "johnp" <johnp3+nospam@probo.com>
Date: 22 Nov 2005 10:19:16 -0800
Links: << >>  << T >>  << A >>
I'm working on a high speed design in a Xilinx V2Pro and I'm running
into a timing
problem.  Instead of packing logic into LUTs, XST wants to use the
Enable
signal in the CLB.  To use the Enable, it needs to use an extra LUT to
create
the Enable signal, so I get routing delays and an extra CLB delay.

Here's some sample code:

req   [3:0] sig4;
wire  [3:0] sig3;

always @(posedge clk)
    if (sig1 & ~sig2)
        sig4 <= sig3;

Xilinx could fit this into 4 CLBs total by simply using the 4 LUTs and
the 4 flip-flops.
Each LUT would handle one bit of sig4.

Instead, XST uses a LUT to create (sig1 & ~sig2), then feeds that
output to the
Enable pins on 4 flip-flops.  I now get the delay through the LUT and
routing delays
to my flip-flops.

Any way to tell XST to not use the Enable signal and force it to use
the LUTs for
this section of logic?

Thanks!

John Providenza


Article: 92108
Subject: Re: Disabling Xilinx clock enable usage...
From: allanherriman@hotmail.com
Date: 22 Nov 2005 10:26:43 -0800
Links: << >>  << T >>  << A >>
johnp wrote:
> I'm working on a high speed design in a Xilinx V2Pro and I'm running
> into a timing
> problem.  Instead of packing logic into LUTs, XST wants to use the
> Enable
> signal in the CLB.  To use the Enable, it needs to use an extra LUT to
> create
> the Enable signal, so I get routing delays and an extra CLB delay.
>
> Here's some sample code:
>
> req   [3:0] sig4;
> wire  [3:0] sig3;
>
> always @(posedge clk)
>     if (sig1 & ~sig2)
>         sig4 <= sig3;
>
> Xilinx could fit this into 4 CLBs total by simply using the 4 LUTs and
> the 4 flip-flops.
> Each LUT would handle one bit of sig4.
>
> Instead, XST uses a LUT to create (sig1 & ~sig2), then feeds that
> output to the
> Enable pins on 4 flip-flops.  I now get the delay through the LUT and
> routing delays
> to my flip-flops.
>
> Any way to tell XST to not use the Enable signal and force it to use
> the LUTs for
> this section of logic?


Your coding style exactly matches the template for clock enable
synthesis:

always @(posedge clk)
    if (condition)
        sig4 <= sig3;

You can work around this by coding the 'no change' action as an
explicit feedback, as follows:

always @(posedge clk)
    sig4 <= (sig1 & ~sig2) ? sig3 : sig4;


(There really should be an attribute to support this.)

Regards,
Allan


Article: 92109
Subject: Re: Disabling Xilinx clock enable usage...
From: allanherriman@hotmail.com
Date: 22 Nov 2005 10:32:33 -0800
Links: << >>  << T >>  << A >>

allanherri...@hotmail.com wrote:
> johnp wrote:
> > I'm working on a high speed design in a Xilinx V2Pro and I'm running
> > into a timing
> > problem.  Instead of packing logic into LUTs, XST wants to use the
> > Enable
> > signal in the CLB.  To use the Enable, it needs to use an extra LUT to
> > create
> > the Enable signal, so I get routing delays and an extra CLB delay.
> >
> > Here's some sample code:
> >
> > req   [3:0] sig4;
> > wire  [3:0] sig3;
> >
> > always @(posedge clk)
> >     if (sig1 & ~sig2)
> >         sig4 <= sig3;
> >
> > Xilinx could fit this into 4 CLBs total by simply using the 4 LUTs and
> > the 4 flip-flops.
> > Each LUT would handle one bit of sig4.
> >
> > Instead, XST uses a LUT to create (sig1 & ~sig2), then feeds that
> > output to the
> > Enable pins on 4 flip-flops.  I now get the delay through the LUT and
> > routing delays
> > to my flip-flops.
> >
> > Any way to tell XST to not use the Enable signal and force it to use
> > the LUTs for
> > this section of logic?
>
>
> Your coding style exactly matches the template for clock enable
> synthesis:
>
> always @(posedge clk)
>     if (condition)
>         sig4 <= sig3;
>
> You can work around this by coding the 'no change' action as an
> explicit feedback, as follows:
>
> always @(posedge clk)
>     sig4 <= (sig1 & ~sig2) ? sig3 : sig4;
>
>
> (There really should be an attribute to support this.)
>
> Regards,
> Allan

Another approach could be to pipeline the (sig1 & ~sig2) calculation,
so the enable path doesn't need to pass through a LUT.  (You may need
to make other changes to get the logic correct.)

Regards,
Allan


Article: 92110
Subject: Re: Disabling Xilinx clock enable usage...
From: "Antti Lukats" <antti@openchip.org>
Date: Tue, 22 Nov 2005 19:37:59 +0100
Links: << >>  << T >>  << A >>

"johnp" <johnp3+nospam@probo.com> schrieb im Newsbeitrag 
news:1132683556.070517.8010@g44g2000cwa.googlegroups.com...
> I'm working on a high speed design in a Xilinx V2Pro and I'm running
> into a timing
> problem.  Instead of packing logic into LUTs, XST wants to use the
> Enable
> signal in the CLB.  To use the Enable, it needs to use an extra LUT to
> create
> the Enable signal, so I get routing delays and an extra CLB delay.
>
> Here's some sample code:
>
> req   [3:0] sig4;
> wire  [3:0] sig3;
>
> always @(posedge clk)
>    if (sig1 & ~sig2)
>        sig4 <= sig3;
>
> Xilinx could fit this into 4 CLBs total by simply using the 4 LUTs and
> the 4 flip-flops.
> Each LUT would handle one bit of sig4.
>
> Instead, XST uses a LUT to create (sig1 & ~sig2), then feeds that
> output to the
> Enable pins on 4 flip-flops.  I now get the delay through the LUT and
> routing delays
> to my flip-flops.
>
> Any way to tell XST to not use the Enable signal and force it to use
> the LUTs for
> this section of logic?
>
> Thanks!
>
> John Providenza
>

Hi John,

in your example XST does exactly what it should do given your code.

if you want the synthesis to avoid using clock enable then you should 
rewrite your code

antti













Article: 92111
Subject: Re: Sounds or other means to indicate end of compilation in Xilinx ISE
From: jaxato@gmail.com
Date: 22 Nov 2005 11:55:58 -0800
Links: << >>  << T >>  << A >>
What I usually do is to start Windows Task Manager and make it into the
minimize mode, which goes to my tray bar. When PAR or any other CPU
intensive application is running, task manager goes all the way to
bright green. This works very well for my single thread P4 CPU but I
cant guarantee that it will work on other systems. Works only on
windows systems too....

That's my two cents..

Simon Peacock wrote:
> If the Xilinx widow is minimized.. you should notice the window you are
> working in become responsive again :-)
> pop up windows are a strict no no.. Protel hates them, I have also had them
> pop up behind other windows... if you happen to click at the wrong time...
> or you just press return as the window pops up.. :-)
>
> Simon
>
>
> "Gabor" <gabor@alacron.com> wrote in message
> news:1132584267.548807.155370@f14g2000cwb.googlegroups.com...
> >
> > Fred wrote:
> > > "Jan Panteltje" <pNaonStpealmtje@yahoo.com> wrote in message
> > > news:dlskc7$610$1@news.datemas.de...
> > > > On a sunny day (Mon, 21 Nov 2005 12:48:13 -0000) it happened "Fred"
> > > > <fred@nowhere.com> wrote in
> <4381c20e$0$23287$db0fefd9@news.zen.co.uk>:
> > > >
> > > >>I find it frustrating that there is no way or telling if a compilation
> has
> > > >>ended or not.  I can't find any feature in ISE which makes a sound
> when
> > > >>it's
> > > >>finished.  I am aware that some might find this an annoying feature
> but
> > > >>would save me periodically checking to see if it's finished or come to
> an
> > > >>end early due to a mistake.
> > > >>
> > > >>Any ideas?
> > > > I'd think that hanging a themocouple with level detector on the
> processor,
> > > > or heat exhaust, was a nice lunch 'time project ;-)
> > > >
> > > > In Linux you could use grep or awk on the output of 'top':
> > > >
> > > > CPU states:  0.5% user,  2.7% system, 15.4% nice, 81.1% idle
> > > >
> > > > look for > X percentage idle, and use keyboard beep:
> > > > echo -e "\a"
> > > >
> > > > ....
> > > >
> > >
> > > A utility to see if a file had been modified would be a possible method.
> >
> > I usually start the build by double-clicking "Generate PROM, ACE, or
> > JTAG File"
> > which will pop up an iMPACT window when finished.  Sound would be
> > nicer, though
> > because I'm usually typing something when the window pops up and takes
> > over
> > the focus...
> >


Article: 92112
Subject: Re: Xst optimizes almost everything away
From: "Andy Peters" <Bassman59a@yahoo.com>
Date: 22 Nov 2005 11:59:03 -0800
Links: << >>  << T >>  << A >>
Adrian Knoth wrote:
> this is my first real VHDL project, so it's perhaps more a
> beginner's question than a problem with Xst.
>
> I have some components for my module two_pc, but when I
> translate it in ISE, both "translate" and "Place&Route"
> have warnings (system report says 308 warnings).
>
> The problem: xst claims that some signals are connected
> but never used. For one component it even says there
> isn't any connection:
>
> Xst:524 - All outputs of the instance <bild> of the block
>           <bildspeicher> are unconnected in block <two_pc>.
>
> I don't think that's true:

>    chooser : process (clk_i, reset) --, update_input)
>            variable links,rechts : std_logic_vector (31 downto 0);
>         begin
>            if (reset='1') then
>               input <= (others => '0');
>            elsif (clk_i'event and clk_i='1') then
>               if (update_input'event and update_input='1') then
                    ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

This statement completely confuses the synthesizer.

I assume you wish to look for the edge of update_input?  You can't do
it this way.  You'll need to use a delay flip-flop (clocked by clk) and
then test the state of both update_input and update_input_delayed.  If
update_input is true and update_input_delayed is false, then you've got
the edge of update_input.

-a


Article: 92113
Subject: Re: Xst optimizes almost everything away
From: "JustJohn" <john.l.smith@titan.com>
Date: 22 Nov 2005 12:08:57 -0800
Links: << >>  << T >>  << A >>
Yo Adrian,

(I assume that it's not something simple, like the signals not making
it to an output pin on the device)

Take a close look at the beginning of your 'chooser' process:

  chooser : process (clk_i, reset) --, update_input)
           variable links,rechts : std_logic_vector (31 downto 0);
        begin
           if (reset='1') then
              input <= (others => '0');
           elsif (clk_i'event and clk_i='1') then
              if (update_input'event and update_input='1') then
                  rechts := bilddaten1;

The elsif predicate is a normal enough rising edge clock condition on
"clk_i". But then it is followed by an if predicate that indicates a
rising edge clock condition on "update_input". What you've coded is a
detector that looks for simultaneous rising edges, and this is not
realistic for synthesis (not realistic period, the two signals come in
on separate pins, and as Einstein observed, there is no simultaneity
for separated points. I suspect you had to use the "--, update_input)"
in the sensitivity list in order to get the simulation to work, but the
synthesis tool complained so you commented it out. Well, keep it out,
but change your if statement to read:
             if update_input='1' then
which is the standard construction for a clock enable.

HTH,
John


Article: 92114
Subject: Re: Verilog Editor.
From: "electro" <yildirimalper@gmail.com>
Date: 22 Nov 2005 12:14:07 -0800
Links: << >>  << T >>  << A >>
Try Pspad, it is one of the best, unfortunately there is no code
folding

http://www.pspad.com


Article: 92115
Subject: Re: Disabling Xilinx clock enable usage...
From: "John_H" <johnhandwork@mail.com>
Date: Tue, 22 Nov 2005 20:46:49 GMT
Links: << >>  << T >>  << A >>
"Antti Lukats" <antti@openchip.org> wrote in message 
news:dlvoi7$5kq$1@online.de...
>
> "johnp" <johnp3+nospam@probo.com> schrieb im Newsbeitrag 
> news:1132683556.070517.8010@g44g2000cwa.googlegroups.com...
>> I'm working on a high speed design in a Xilinx V2Pro and I'm running
>> into a timing
>> problem.  Instead of packing logic into LUTs, XST wants to use the
>> Enable
>> signal in the CLB.  To use the Enable, it needs to use an extra LUT to
>> create
>> the Enable signal, so I get routing delays and an extra CLB delay.
>>
>> Here's some sample code:
>>
>> req   [3:0] sig4;
>> wire  [3:0] sig3;
>>
>> always @(posedge clk)
>>    if (sig1 & ~sig2)
>>        sig4 <= sig3;
>>
>> Xilinx could fit this into 4 CLBs total by simply using the 4 LUTs and
>> the 4 flip-flops.
>> Each LUT would handle one bit of sig4.
>>
>> Instead, XST uses a LUT to create (sig1 & ~sig2), then feeds that
>> output to the
>> Enable pins on 4 flip-flops.  I now get the delay through the LUT and
>> routing delays
>> to my flip-flops.
>>
>> Any way to tell XST to not use the Enable signal and force it to use
>> the LUTs for
>> this section of logic?
>>
>> Thanks!
>>
>> John Providenza
>>
>
> Hi John,
>
> in your example XST does exactly what it should do given your code.
>
> if you want the synthesis to avoid using clock enable then you should 
> rewrite your code
>
> antti

I would respectfully disagree.

A decent synthesizer should *not* produce an extra level of logic with an 
actual increase in area unless - and it's hard to see this as the case - the 
extra fanout for a heavily loaded signal causes timing problems elsewhere in 
the design.

In a properly constrained design, a decent synthesizer should *not* produce 
logic that violates the timing constraints if there's an available solution 
that meets the timing.  Unfortunately we have to spend much of our time 
tuning things manually to get the "obvious" to happen. 



Article: 92116
Subject: Stupid reset question
From: Nick <nick@no-domain>
Date: Tue, 22 Nov 2005 22:14:00 +0100
Links: << >>  << T >>  << A >>
Hello,

I'm in the final phase of a design in VHDL on a Cyclon, and i am
really puzzled by something. 
I do not have an external reset pin, so how can i ensure that my
states machines start at the right state, that all values are well
initialized and everything ?

It seems to work as it is now, but i couldn't find any litterature on
this subject.

Many thanks
Nick

Article: 92117
Subject: Re: Disabling Xilinx clock enable usage...
From: "Antti Lukats" <antti@openchip.org>
Date: Tue, 22 Nov 2005 23:53:25 +0100
Links: << >>  << T >>  << A >>
"John_H" <johnhandwork@mail.com> schrieb im Newsbeitrag 
news:ZsLgf.36$LT5.98@news-west.eli.net...
> "Antti Lukats" <antti@openchip.org> wrote in message 
> news:dlvoi7$5kq$1@online.de...
>>
>> "johnp" <johnp3+nospam@probo.com> schrieb im Newsbeitrag 
>> news:1132683556.070517.8010@g44g2000cwa.googlegroups.com...
>>> I'm working on a high speed design in a Xilinx V2Pro and I'm running
>>> into a timing
>>> problem.  Instead of packing logic into LUTs, XST wants to use the
>>> Enable
>>> signal in the CLB.  To use the Enable, it needs to use an extra LUT to
>>> create
>>> the Enable signal, so I get routing delays and an extra CLB delay.
>>>
>>> Here's some sample code:
>>>
>>> req   [3:0] sig4;
>>> wire  [3:0] sig3;
>>>
>>> always @(posedge clk)
>>>    if (sig1 & ~sig2)
>>>        sig4 <= sig3;
>>>
>>> Xilinx could fit this into 4 CLBs total by simply using the 4 LUTs and
>>> the 4 flip-flops.
>>> Each LUT would handle one bit of sig4.
>>>
>>> Instead, XST uses a LUT to create (sig1 & ~sig2), then feeds that
>>> output to the
>>> Enable pins on 4 flip-flops.  I now get the delay through the LUT and
>>> routing delays
>>> to my flip-flops.
>>>
>>> Any way to tell XST to not use the Enable signal and force it to use
>>> the LUTs for
>>> this section of logic?
>>>
>>> Thanks!
>>>
>>> John Providenza
>>>
>>
>> Hi John,
>>
>> in your example XST does exactly what it should do given your code.
>>
>> if you want the synthesis to avoid using clock enable then you should 
>> rewrite your code
>>
>> antti
>
> I would respectfully disagree.
>
> A decent synthesizer should *not* produce an extra level of logic with an 
> actual increase in area unless - and it's hard to see this as the case - 
> the extra fanout for a heavily loaded signal causes timing problems 
> elsewhere in the design.
>
> In a properly constrained design, a decent synthesizer should *not* 
> produce logic that violates the timing constraints if there's an available 
> solution that meets the timing.  Unfortunately we have to spend much of 
> our time tuning things manually to get the "obvious" to happen.

Dear John (and John),

I am glad to see someone to disagree with me once in a while, but the issue 
isnt that simple

the way XST does synthesize the example in the original posting DOES NOT add 
extra delay
and is in most cases the most effective coding. The flip flops are feed 
either by direct connect
bypassing the LUT in their slices, or from feeding logic that is packed into 
the slice where
the FF is, in what case the delay before the FF is absolutly minimal (LUT to 
FF in same slice).
In most cases the timing delays in clock enable and data path will somewhat 
overlay and
cancel out a bit from timing budget so the clock enable version would be 
faster, that is
implementing the clock enable emulation in the D input would make one delay 
path longer
and overall timing worse.

OTOH in some cases the no clock enable version may yield to better overall
timing depending where the critical path is, but here my bet is that there 
is no
"decent" synthesizer that would optimize the clock enable out from the 
sample
code based on critical path analyze alone. It would be possible, yes - but I 
would
be surprised to see some synthesis tool to actually do that without explicit
coding or constraining. Hm, maybe am wrong and some synthesis tool is
as smart already :)

I do AGREE that the syntesis tools do not the best and in cases where
solution to meet timing is available, that solution is not used 
automatically
and needs manual 'tuning'.

Antti


































Article: 92118
Subject: Re: Disabling Xilinx clock enable usage...
From: "johnp" <johnp3+nospam@probo.com>
Date: 22 Nov 2005 15:22:05 -0800
Links: << >>  << T >>  << A >>
All -

Of course, I realize that my code sample REALLY wants to map to the
Enable pin:
always @(posedge clk)
    if (condition)
        sig4 <= sig3;

The suggestion to recode the Verilog to look like:
always @(posedge clk)
    sig4 <= (sig1 & ~sig2) ? sig3 : sig4;

concerns me since a smart synthesizer would recognize this to be
EXACTLY
the sime code, just written in an odd way.

The safest approach (which I've change to) is to add another level of
pipelining.

It just seems sad that even when the LUTs are available, the
synthesizer put
in an extra logic level so it could use the Enable pin.

BTW, this is with XST 6.2.03.  It could be that the newer versions are
better.

John Providenza


Article: 92119
Subject: Re: Setting the environment variable in ISE 7.1?
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Tue, 22 Nov 2005 15:47:54 -0800
Links: << >>  << T >>  << A >>
And then there is this:

 cam1_dcmfx2 : dcmfx2
 port map(
  clkin_n_in   => gpio_exp_hdr2(6), -- cam1_xclk,
  clkin_p_in   => gpio_exp_hdr2(7), -- cam1_xclk,
  rst_in       => reset,
  clkfx_out    => cam1_clk7x,
  clkin_ibufgds_out  => open,
  clk0_out     => cam1_xclk,
  locked_out   => cam1_lock7x );

generated clock with external differential inputs selected

 



Article: 92120
Subject: Re: Setting the environment variable in ISE 7.1?
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Tue, 22 Nov 2005 15:48:24 -0800
Links: << >>  << T >>  << A >>
And this:

cam1_dcmfx2 : dcmfx2
 port map(
  clkin_n_in   => gpio_exp_hdr2(6), -- cam1_xclk,
  clkin_p_in   => gpio_exp_hdr2(7), -- cam1_xclk,
  rst_in       => reset,
  clkfx_out    => cam1_clk7x,
  clkin_ibufgds_out  => open,
  clk0_out     => cam1_xclk,
  locked_out   => cam1_lock7x );




Article: 92121
Subject: Re: Stupid reset question
From: Austin Lesea <austin@xilinx.com>
Date: Tue, 22 Nov 2005 15:55:00 -0800
Links: << >>  << T >>  << A >>
Nick,

I assume that Cyclone works similarly to our own FPGAs in that all flip 
flops are inti tally set to 0 by the house-cleaning (initialization 
prior to configuration) at power on.

You can check this by reading their manual on what happens during power 
on and configuration.

Then, during configuration, the state of the flip flops for logic may 
(or may not) be set, or reset to a state as specified by the bitstream 
(depends on the device, and its options when being configured).

If you have designed the state machine with no hidden states, and in 
such a way that it will always return to a known state given a set of 
good inputs, there is no need for a reset.

In the case of a 1-hot state machine (very popular in FPGAs) this also 
means that detection of having more than one state set (more than one 
flip flop) must decode and send you back to a known state of having only 
one state active!

Austin

Nick wrote:

> Hello,
> 
> I'm in the final phase of a design in VHDL on a Cyclon, and i am
> really puzzled by something. 
> I do not have an external reset pin, so how can i ensure that my
> states machines start at the right state, that all values are well
> initialized and everything ?
> 
> It seems to work as it is now, but i couldn't find any litterature on
> this subject.
> 
> Many thanks
> Nick

Article: 92122
Subject: Re: Disabling Xilinx clock enable usage...
From: Duane Clark <dclark@junkmail.com>
Date: Wed, 23 Nov 2005 00:20:11 GMT
Links: << >>  << T >>  << A >>
johnp wrote:
> All -
> 
> Of course, I realize that my code sample REALLY wants to map to the
> Enable pin:
> always @(posedge clk)
>     if (condition)
>         sig4 <= sig3;
> 
> The suggestion to recode the Verilog to look like:
> always @(posedge clk)
>     sig4 <= (sig1 & ~sig2) ? sig3 : sig4;
> 
> concerns me since a smart synthesizer would recognize this to be
> EXACTLY the sime code, just written in an odd way.

That would require that the synthesis tool specifically look for the 
default value on the right be the same signal as is being assigned to. 
While I suppose it is possible that a synthesis tool might do that, I 
kind of doubt it. That would seem to me to require that the tool 
designer deliberately coded the tool to de-optimize (is that a word ;) 
the code.


Article: 92123
Subject: data encryption standard
From: "hirenshah.05@gmail.com" <hirenshah.05@gmail.com>
Date: 22 Nov 2005 16:30:50 -0800
Links: << >>  << T >>  << A >>
hi,

I am implementing data encryption standard using verilog. can anyone
suggest efficient algorith to implemnt data encryption standard (
especially S-box).


Article: 92124
Subject: Re: CLK input DOES NOT use clk pin ( Altera Stratix II)
From: "huangjie" <huangjielg@gmail.com>
Date: 22 Nov 2005 17:05:32 -0800
Links: << >>  << T >>  << A >>
I have understood your idea, and know why yours work but mine cann't .
Just because your slow clock is  slow ,and  mine is very fast.
How can I deal with 125M clocks  just as it is 2M ? How fast my
"reference"  for 125M ?
Perhaps I can use a group of some phase-shift clocks to get a clk
enable signals.
Thank you again!




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