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Messages from 92150

Article: 92150
Subject: Re: Question on 2048 point FFT( Basic)
From: backhus <nix@nirgends.xyz>
Date: Wed, 23 Nov 2005 08:37:06 +0100
Links: << >>  << T >>  << A >>
aj schrieb:
> Hello FFT guru's
> 
> I am implementing 2048 point FFT on Virtex as a part of my small 
> project at uni. i want to put couple of questions.. please help me to
>  your best as i am a starter...:)
> 
> I have gone through couple of IEEE papers and i have found that i 
> should use (Mixed Radix alg).i.e. like Radix4 and Radix2 butterflies 
> to implement this algorithm. i have an understanding to use total of 
> 6 stages...i.e. 5 stages of Radix-4 and 1 stage of Radix-2 
> operations.
> 
> Question 1. Is the aforementioned technique the best in terms of 
> speed and area that operation will acquire.?
> 
  Ans----> That depends. Do you need the speed? What is the required
number of Transforms per second? What is your Clock frequency? If you
are not going for maximum speed you can save a lot of area by
implementing just a single stage and some RAM and a controller that puts
the data sequentially through that single butterfly stage. That will
cost several clocks to run through the full transformation but you save
a LOT of area consuming multipliers.
> 
> Question 2. I am very much confused about the Which ARCHITECTURE that

  Answer----> again That depends :-) You should know where you want to
connect your FFT-core to. If you know how the Data Is feeded from your
data source and you know how you are going to store this data...go ahead
and design the interface.
> 
> Quetion 3.----> my tutor also asked me to start my project with 

  Ans-------> Well, I guess he means one butterfly stage. If you have one
of these running you can decide wether you age going to implement
something massive parallel or something sequential as mentioned above.
> 
> Question 4....----> (Most important for me)----------------> can i 

  Ans---------> Yes you can! RTFM :-)
> 
> Question 5....Can any one tell me any website for getting  source 

  Answer -----> Bad excuse.. Use UltimateZIP for instance. Or install
cygwin. :-)
Also the cf_fft will not be really useful for you because
it's originally written in Confluence which outputs verilog code (maybe
vhdl as well if you are using the confluence compiler) which I expect
hard to read, sice it is machine generated stuff.

Better have a look here :

http://tech-www.informatik.uni-hamburg.de/vhdl/models/fft/

It's the first result when you are googeling for: FFT VHDL

Now get busy!  :-)

   have a nice synthesis
      Eilert


Article: 92151
Subject: Re: Aurora over Rocket IO and EDk
From: "sjulhes" <t@aol.fr>
Date: Wed, 23 Nov 2005 08:42:05 +0100
Links: << >>  << T >>  << A >>
Hi,

I did real time image transmission on 2Gbits fiber, using 2 boards 2VP20's
rocket IOs.
I followed what was in the aurora's documentation for reset and clocks and
it worked without much problems.
It won't be too difficult to drive aurora with your application.

Read carefully aurora's specification and examples, and then ask precise
questions.


<beeraka@gmail.com> a écrit dans le message de news:
1132712671.237906.203310@z14g2000cwz.googlegroups.com...
> Hi ,
>       Has anyone implemented a design using Aurora over Rocket IO in
> EDK...If so please point me to the correct document....
>        What I am trying to do is to hook up a BRAM in an OPB core to
> send data to the Rocket I/O through Aurora and then on the Receiver
> side, use a BRAM to receieve the data...
>        I wrote the code but I have lots of questions regarding
> generating the differential clock and the RESET..So if anyone can help
> me out, then that would be great..
>        Thanks in advance....
>
> --
> Parag
>



Article: 92152
Subject: Re: Patient Monitors: Reading RS232 output w/ an FPGA
From: "Mike Treseler" <mike_treseler@comcast.net>
Date: Tue, 22 Nov 2005 23:51:10 -0800
Links: << >>  << T >>  << A >>
Mark wrote:

> Does anyone have any experience interfacing an FPGA to patient monitors?

http://www.fda.gov/cdrh/comp/designgd.html

Looks like there might be
a few fussy regulations.

      -- Mike Treseler

Article: 92153
Subject: Simulating PLB DDR in EDK 7.1 SP2 using ModelSim 6.0a
From: "Nju Njoroge" <njoroge@stanford.edu>
Date: 23 Nov 2005 00:08:18 -0800
Links: << >>  << T >>  << A >>
Hello,

Is there an existing flow for simulating PLB DDR in ModelSim using EDK
7.1 SP2 in a full system (PPCs, pcores,etc)? The instructions are being
stored in BRAMs, as to avoid DDR initialization hassles. I have been
simulating the data-only DDR using BRAMs, however, to get a more
accurate depiction of the system, I would like to use DDR in
simulation.

Thanks,

NN


Article: 92154
Subject: Re: Newbie: Problems with clocks
From: Andreas <AndreasN@gmx.de>
Date: Wed, 23 Nov 2005 09:12:36 +0100
Links: << >>  << T >>  << A >>
backhus wrote:

> Hi Andreas,
> I don't know how to do it in Precision but in XST you can tell the tool
> to use no GlobalClockBuffer at all (Xilinx Specific Options Tab). Then
> any Input can be (ab)used as a Clock input using normal routing
> resoources instead the global clock net.
> For one FF and Testing this might be OK. In a large design you will get
> into big trouble.
> 
> Now, If you are a newbie you brobably intend to use the button for
> manual clocking, to allow single stepping of your design. Beware!!!
> 
> Just imagine a simple counter driving some LEDs. What you expect is that
> it increments with every press on the button. But what happens will be
> random outputs to appear on your LEDs. Why is that? Because your Button
> bounces several times each time you press it and/or release it. Not very
> usefull, is it?

Thank you for that information. The example you describe is exact the test
case I wanted to use in my first FPGA test design.


Greetings,
Andreas



> 
> To overcome this problem you need two things: One is a clock divider
> driven by the onboard Clock Oscillator. The Output can be something
> about 100Hz and needs only to create an impulse of a single clocks length.
> 
> This signal can be used as a clock enable for a debouncing circuit which
> is described in the Xilinx synthesis template. Then you can use your
> button(s) for Input, and even (ab)use this Output signal as a Clock
> Signal. But remember: Only for testing SMALL designs! You also need to
> constrain the number of GCLK Buffers to 1.
> 
> Have a nice Synthesis
> 
>    Eilert


Article: 92155
Subject: Re: Microblaze and custom peripherals
From: "ssirowy@gmail.com" <ssirowy@gmail.com>
Date: 23 Nov 2005 01:21:13 -0800
Links: << >>  << T >>  << A >>
Is there a way to extend the connectivity to allow X amount of
peripherals access to the local BRAM's for the processor? Say for
simplicity I have 16 custom dividers that I want to instantiate and all
require single cycle access to the local processor memory.  Is there
any way to accomplish this with a Microblaze system? Thanks for your
help,


   Scott


Article: 92156
Subject: FPGA and metastability once again
From: v_mirgorodsky@yahoo.com
Date: 23 Nov 2005 01:38:02 -0800
Links: << >>  << T >>  << A >>
Hello ALL,

I have a design with two global clocks. I have data I need to transfer
from one clock domain to another. I am aware of existence of FIFO
blocks :), but it seems to be too expensive to spend a block-ram and
other resources for every boundary crossing. To avoid using FIFO blocks
we created a handshake schematic, based on some triggers and small FSM.
This solution is proven to work in hardware error-free for almost 40
hours. First domain clock frequency is 25MHz or 125MHz (depending on
mode); second domain clock frequency is 166MHz.

Naturally, some triggers in out design are metastable. Is it possible
to get some intermediate voltage level at the output of trigger in FPGA
if input signal on its Data input violates setup or hold times? In my
design I assume I don't get any intermediate level voltages at the
trigger outputs. What about signal I input into FPGA from outside? Is
it possible to get some intermediate voltage levels on the trigger
outputs by violating setup-hold times and/or IO standard voltage
levels?

With best regards,
Vladimir S. Mirgorodsky


Article: 92157
Subject: Re: Stupid reset question
From: =?ISO-8859-1?Q?Johan_Bernsp=E5ng?= <xjohbex@xfoix.se>
Date: Wed, 23 Nov 2005 10:51:57 +0100
Links: << >>  << T >>  << A >>
Nick wrote:
> Hello,
> 
> I'm in the final phase of a design in VHDL on a Cyclon, and i am
> really puzzled by something. 
> I do not have an external reset pin, so how can i ensure that my
> states machines start at the right state, that all values are well
> initialized and everything ?
> 
> It seems to work as it is now, but i couldn't find any litterature on
> this subject.
> 
> Many thanks
> Nick


Nick,

I don't know about Cyclone FPGAs but I suppose that they have some sort 
of digital clock manager, DCM, as the Xilnx FPGAs have. In some designs 
I have used the inverse of the DCM lock signal as global reset signal. 
In that way all flip-flops in the design are reset simultaneously when 
the clock is stable. (The DCM lock signal is asserted when all outputs 
from the component are locked).

I don't know if this is considered good or bad practise, but it is 
working quite good. Hasn't failed yet.

-- 
-----------------------------------------------
Johan Bernspång, xjohbex@xfoix.se
Research engineer

Swedish Defence Research Agency - FOI
Division of Command & Control Systems
Department of Electronic Warfare Systems

www.foi.se

Please remove the x's in the email address if
replying to me personally.
-----------------------------------------------

Article: 92158
Subject: Re: Microblaze and custom peripherals
From: =?ISO-8859-1?Q?G=F6ran_Bilski?= <goran.bilski@xilinx.com>
Date: Wed, 23 Nov 2005 11:24:54 +0100
Links: << >>  << T >>  << A >>
ssirowy@gmail.com wrote:
> Is there a way to extend the connectivity to allow X amount of
> peripherals access to the local BRAM's for the processor? Say for
> simplicity I have 16 custom dividers that I want to instantiate and all
> require single cycle access to the local processor memory.  Is there
> any way to accomplish this with a Microblaze system? Thanks for your
> help,
> 
> 
>    Scott
> 
Hi,

On MicroBlaze can be master on the LMB bus.
You can have peripherals but no other master.
If you want modules to access the BRAM, it can't be done using the LMB.


I would out all these accelerators on the FSL interface.

Göran

Article: 92159
Subject: XST vs Synplify
From: francesco_poderico@yahoo.com
Date: 23 Nov 2005 02:31:02 -0800
Links: << >>  << T >>  << A >>
Hi all,
I wish to have an idea about how many people here uses Synlify or
Leonardo and how many people uses XST.
The purpose of that is undesrtand how many people here beleave that XST
is a mature product and it can be trusted or not.
At moment I'm tryng to use XST for a small FPGA (spartan 2E 150) and
I'm having a lot of trouble.
(I have several years of experience and I made design very complex)

For example the xapp807 has source file in VHDL and in Verilog. when I
use the verilog version it works fine, but when I use the VHDL version
it is unrelaible. 

Hope to have feedback from you.
Francesco


Article: 92160
Subject: We need to program several thousands Xilinx flashes XCF025...
From: "zlyh" <zlyh@yandex.ru>
Date: 23 Nov 2005 03:32:25 -0800
Links: << >>  << T >>  << A >>
Please advise me.

We need to program several thousands Xilinx flashes XCF025...
(Data sheet http://direct.xilinx.com/bvdocs/publications/ds123.pdf)
They support IEEE 1532. On our board we make JTAG connectors to the
flash chip. The flashes will be soldered to board. There are one flash
per board.
Xilinx offers tools to program XCF... - MultiPRO Desktop Tool
(Data sheet http://direct.xilinx.com/bvdocs/publications/ds114.pdf)
but it's look like only for Xilinx. At my desk I use Parallel cable,
it's too enough (for one PCB :-) ).
1. Our first target is to program flash.
But I would like to have some more universal tool, not only for ISP,
but to test our designs (PCBs) too.
2. We don't know what is better: to program flash chip and then to
solder it or to solder it and then program. May be ask Xilinx to
program flashes at factory and then solder?
Anyway we need to keep the design reconfigurable.

I look to www.universalscan.com . It looks universal and not expensive.


Article: 92161
Subject: Re: CLK input DOES NOT use clk pin ( Altera Stratix II)
From: "huangjie" <huangjielg@gmail.com>
Date: 23 Nov 2005 03:37:37 -0800
Links: << >>  << T >>  << A >>
Thanks for Betz  and Simon.
To  Simon, my design have some clock at 125M without any phase and
frequence relations
but not only one, so which one should be the reference  ?
To Betz, my trouble is NOT too many clocks but tow many interface
clocks not connected to the
dedicated clock pin.Although some clocks slow eg:33M PCI,but some of
very fast 125M.
I know I can use global clock,but how to calculate the delay of global
clock?
 Interface has a valid data window about 4ns, how can I or how many ns
I should  shift the global ?
My problem is skew between chip internal and chip external ,but not
skew in chip internal.


Article: 92162
Subject: Case expression?
From: "Fred" <fred@nowhere.com>
Date: Wed, 23 Nov 2005 12:05:56 -0000
Links: << >>  << T >>  << A >>
For simplicity I would like to do the following

CASE (bit1 & bit2 & bit3) IS
    when "000" =>
        var <= something;
        .....
    when "000" =>
        var <= somethingelse;

    when others =>
END CASE

bit1 to 3 are "std_logic".  How do I concatenate these "bits" in a CASE 
statement without having an intermediate array?

Many thanks in advance. 



Article: 92163
Subject: Re: Case expression?
From: allanherriman@hotmail.com
Date: 23 Nov 2005 04:27:57 -0800
Links: << >>  << T >>  << A >>
Fred wrote:
> For simplicity I would like to do the following
>
> CASE (bit1 & bit2 & bit3) IS
>     when "000" =>
>         var <= something;
>         .....
>     when "000" =>
>         var <= somethingelse;
>
>     when others =>
> END CASE
>
> bit1 to 3 are "std_logic".  How do I concatenate these "bits" in a CASE
> statement without having an intermediate array?

You either wait for the next rev of VHDL (and then wait a couple of
years for the tools to catch up), or you use a temporary variable.  I
don't know of any other way.

  tmp := bit1 & bit2 & bit3;
  case tmp is
      when ...


BTW, you shouldn't have parentheses around the case expression.

Regards,
Allan


Article: 92164
Subject: Re: Case expression?
From: allanherriman@hotmail.com
Date: 23 Nov 2005 04:34:43 -0800
Links: << >>  << T >>  << A >>
allanherri...@hotmail.com wrote:
> You either wait for the next rev of VHDL (and then wait a couple of
> years for the tools to catch up), or you use a temporary variable.  I
> don't know of any other way.

Another way would be to use Verilog.


Article: 92165
Subject: Re: We need to program several thousands Xilinx flashes XCF025...
From: backhus <nix@nirgends.xyz>
Date: Wed, 23 Nov 2005 14:06:25 +0100
Links: << >>  << T >>  << A >>
zlyh schrieb:
> Please advise me.
> 
> We need to program several thousands Xilinx flashes XCF025...
> (Data sheet http://direct.xilinx.com/bvdocs/publications/ds123.pdf)
> They support IEEE 1532. On our board we make JTAG connectors to the
> flash chip. The flashes will be soldered to board. There are one flash
> per board.
> Xilinx offers tools to program XCF... - MultiPRO Desktop Tool
> (Data sheet http://direct.xilinx.com/bvdocs/publications/ds114.pdf)
> but it's look like only for Xilinx. At my desk I use Parallel cable,
> it's too enough (for one PCB :-) ).
> 1. Our first target is to program flash.
> But I would like to have some more universal tool, not only for ISP,
> but to test our designs (PCBs) too.
> 2. We don't know what is better: to program flash chip and then to
> solder it or to solder it and then program. May be ask Xilinx to
> program flashes at factory and then solder?
> Anyway we need to keep the design reconfigurable.
> 
> I look to www.universalscan.com . It looks universal and not expensive.
> 
Hi,
there are two ways you can go
You can look for one a company that does the mass-programming of the 
chips before soldering. Then equip the pcb, but don't forget to 
implement a means for updates of the flash rom.

This way you have a fast and economic production chain. BUT!

If your board is more complex and your boardmanufacturer has to run 
electrical tests anyway then he surely has the equipment to program the 
flash roms at the end of the test phase.

Conclusion:
Provide your pcb with a JTAG connector, and decide which way to go 
according to the possibilities of your board manufacturer.
Since you need to manufacture several thousands of PCBs as well you 
surely will contact a more powerful facility for that job.

Besides...When the real FPGA bitstream is progammed at the end of 
testing, you can provide the manufacturer with a special testing 
bitstream thad accelerates the electrical tests. Talk to the specialists 
there about their board testing strategy. They should know, otherwise 
change the manufacturer ;-)

   regards
      Eilert

Article: 92166
Subject: Re: Xst optimizes almost everything away
From: Adrian Knoth <adi@thur.de>
Date: Wed, 23 Nov 2005 13:42:31 +0000 (UTC)
Links: << >>  << T >>  << A >>
Andy Peters <Bassman59a@yahoo.com> wrote:

>>    chooser : process (clk_i, reset) --, update_input)
>>            variable links,rechts : std_logic_vector (31 downto 0);
>>         begin
>>            if (reset='1') then
>>               input <= (others => '0');
>>            elsif (clk_i'event and clk_i='1') then
>>               if (update_input'event and update_input='1') then
>                     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>
> I assume you wish to look for the edge of update_input?  You can't do

Yes.

> it this way.  You'll need to use a delay flip-flop (clocked by clk) and
> then test the state of both update_input and update_input_delayed.  If
> update_input is true and update_input_delayed is false, then you've got
> the edge of update_input.

Wouldn't rising_edge (update_input) do the job? Or falling_edge (),
if I need to know whether a signal was once set and is now off
(write_A indicates that my processor core has written its result
 and I now can use the value of the output-FFs to write it to
 vga.)

How do I synchronize these processes in VHDL? I have the output-FFs
containing the current value and need to bitwise store the content
in the VGA-RAM every time my write_A indicates that there are new
data. I currently use a process for this but I don't know if it
really stops after executing the for-loops, how many clock cycles
are used for each loop iteration, if every statement in the
loop-body is executed in one clock cycle and so on:

  to_video : process (clk_i, reset)
     variable tmp_vga : std_logic_vector (31 downto 0);
  begin
    if (reset='1') then
       addr_vga <= (others => '0');
       web_i <= '0';
    elsif (falling_edge (write_A)) then
       tmp_vga := output;
       for j in 3 downto 0 loop
          for i in 6 downto 1 loop
             web_i <= '1';
             dib_i (0 downto 0) <= tmp_vga (j * 8 + i downto j * 8 + i);
             web_i <= '0';
             addr_vga <= addr_vga + 1;
          end loop;
       end loop;
     end if;
  end process to_video;

(web_i enables the vga input, addr_vga should be the bitaddress in
 the VGA RAM)

Let's say write_A goes up for two cycles every 24 clocks (assumption,
I don't know the real amount of clocks between these two pulses),
indicating that there is now new information available at the
output (output is DFF-buffered (but currently optimized away ;)).

Does the process above would poke the selected bits to dib_i or
do I have to keep track of write_A by something like a state machine?


-- 
mail: adi@thur.de  	http://adi.thur.de	PGP: v2-key via keyserver

Internet nach 1996 ist ohnehin nur noch verkommerzialisierte Scheiße
							(Christian Anger)

Article: 92167
Subject: Re: Xst optimizes almost everything away
From: Adrian Knoth <adi@thur.de>
Date: Wed, 23 Nov 2005 13:52:02 +0000 (UTC)
Links: << >>  << T >>  << A >>
JustJohn <john.l.smith@titan.com> wrote:

> (I assume that it's not something simple, like the signals not making
> it to an output pin on the device)

I think so, too.

>            elsif (clk_i'event and clk_i='1') then
>               if (update_input'event and update_input='1') then
>                   rechts := bilddaten1;
>

> for separated points. I suspect you had to use the "--, update_input)"
> in the sensitivity list in order to get the simulation to work, but the
> synthesis tool complained so you commented it out. Well, keep it out,
> but change your if statement to read:
>              if update_input='1' then
> which is the standard construction for a clock enable.

Thanks, this sounds reasonable to me. Unfortunately it doesn't
change a thing ;) I also removed some other statements of this
kind.

Perhaps the problem is in the generation of update_input?
I have to wait with new input until the core has read it,
so I have a read_A going from 0 to 1 for two cycles if the
data was captured:

   addrgen : process (clk_i, reset) -- , read_A)
   begin
      if (reset='1') then
         zeile <= "0000000";
         spalte <= "00";
      elsif (clk_i'event and clk_i='1') then
         for i in 0 to 3 loop
            spalte <= spalte + 1;
            for j in 0 to 127 loop
               zeile <= zeile + 1;
               -- wait for core to read input
               update_input <= '1';
               while (read_A = '0') loop
                  null;  -- read_A is low until core has captured data
               end loop;
               update_input <= '0';
            end loop;
            reset_trig <= '1';
            reset_trig <= '0';
         end loop;
      end if;
   end process addrgen;


I think the while-loop is more or less stupid, all I want to do
is to wait for read_A going up and down, indicating that the
new input data was captured by the processing core.


-- 
mail: adi@thur.de  	http://adi.thur.de	PGP: v2-key via keyserver

Lieber Erstattung als Bestattung

Article: 92168
Subject: Re: Case expression?
From: "Fred" <fred@nowhere.com>
Date: Wed, 23 Nov 2005 14:05:39 -0000
Links: << >>  << T >>  << A >>

<allanherriman@hotmail.com> wrote in message 
news:1132748877.058204.324060@g47g2000cwa.googlegroups.com...
> Fred wrote:
>> For simplicity I would like to do the following
>>
>> CASE (bit1 & bit2 & bit3) IS
>>     when "000" =>
>>         var <= something;
>>         .....
>>     when "000" =>
>>         var <= somethingelse;
>>
>>     when others =>
>> END CASE
>>
>> bit1 to 3 are "std_logic".  How do I concatenate these "bits" in a CASE
>> statement without having an intermediate array?
>
> You either wait for the next rev of VHDL (and then wait a couple of
> years for the tools to catch up), or you use a temporary variable.  I
> don't know of any other way.
>
>  tmp := bit1 & bit2 & bit3;
>  case tmp is
>      when ...
>
>
> BTW, you shouldn't have parentheses around the case expression.
>
> Regards,
> Allan
>

Many thanks.

I've used a temporary variable but it's not so readable.  Shame really to 
have to do it. 



Article: 92169
Subject: Re: Case expression?
From: "Fred" <fred@nowhere.com>
Date: Wed, 23 Nov 2005 14:07:09 -0000
Links: << >>  << T >>  << A >>

<allanherriman@hotmail.com> wrote in message 
news:1132749283.568506.23210@g49g2000cwa.googlegroups.com...
> allanherri...@hotmail.com wrote:
>> You either wait for the next rev of VHDL (and then wait a couple of
>> years for the tools to catch up), or you use a temporary variable.  I
>> don't know of any other way.
>
> Another way would be to use Verilog.
>

Unfortunately in the UK you're more employable if you know VHDL.  I have 
written in Verilog and quite like the C type structure.  Since I'd like to 
pay my bills I feel tied to VHDL.



Article: 92170
Subject: Re: Case expression?
From: allanherriman@hotmail.com
Date: 23 Nov 2005 06:17:13 -0800
Links: << >>  << T >>  << A >>
Fred wrote:
> <allanherriman@hotmail.com> wrote in message
> news:1132749283.568506.23210@g49g2000cwa.googlegroups.com...
> > allanherri...@hotmail.com wrote:
> >> You either wait for the next rev of VHDL (and then wait a couple of
> >> years for the tools to catch up), or you use a temporary variable.  I
> >> don't know of any other way.
> >
> > Another way would be to use Verilog.
> >
>
> Unfortunately in the UK you're more employable if you know VHDL.  I have
> written in Verilog and quite like the C type structure.  Since I'd like to
> pay my bills I feel tied to VHDL.

You're even more employable if you have a strong knowedge of both.

Regards,
Allan


Article: 92171
Subject: Design Implementation in Xilinx XST
From: Jeremy Wood <serith2@charter.net>
Date: Wed, 23 Nov 2005 08:19:54 -0600
Links: << >>  << T >>  << A >>
Greetings everyone,

I've recently started working on FPGA designs and was wondering if
there is a way to get timing reports and synthesis results from the
Xilinx software that don't include I/O pin mapping. I'm trying to
constrain several blocks for testing purposes, but these modules will
all be internal to the design and won't be connected directly to the
pins. However, it seems the tools automaically assume these
connections, which is adding extra delay than what will really be
there. Is there a way to tell the tool to ignore physical pin
connections and use, say, simulated register I/O connections instead?

Sorry if this seems like a silly question, I'm still getting the hang
of synthesis yet.

Thanks in advance,
Jeremy

Article: 92172
Subject: Re: Case expression?
From: allanherriman@hotmail.com
Date: 23 Nov 2005 06:21:11 -0800
Links: << >>  << T >>  << A >>
allanherri...@hotmail.com wrote:
> Fred wrote:
> > <allanherriman@hotmail.com> wrote in message
> > news:1132749283.568506.23210@g49g2000cwa.googlegroups.com...
> > > allanherri...@hotmail.com wrote:
> > >> You either wait for the next rev of VHDL (and then wait a couple of
> > >> years for the tools to catch up), or you use a temporary variable.  I
> > >> don't know of any other way.
> > >
> > > Another way would be to use Verilog.
> > >
> >
> > Unfortunately in the UK you're more employable if you know VHDL.  I have
> > written in Verilog and quite like the C type structure.  Since I'd like to
> > pay my bills I feel tied to VHDL.
>
> You're even more employable if you have a strong knowedge of both.

... and even more employable if you can spell.


Article: 92173
Subject: Re: Design Implementation in Xilinx XST
From: Tim Good <elp04trg@sheffield.ac.uk>
Date: Wed, 23 Nov 2005 15:18:15 +0000
Links: << >>  << T >>  << A >>
Jeremy Wood wrote:
> Greetings everyone,
> 
> I've recently started working on FPGA designs and was wondering if
> there is a way to get timing reports and synthesis results from the
> Xilinx software that don't include I/O pin mapping. I'm trying to
> constrain several blocks for testing purposes, but these modules will
> all be internal to the design and won't be connected directly to the
> pins. However, it seems the tools automaically assume these
> connections, which is adding extra delay than what will really be
> there. Is there a way to tell the tool to ignore physical pin
> connections and use, say, simulated register I/O connections instead?
> 
> Sorry if this seems like a silly question, I'm still getting the hang
> of synthesis yet.
> 
> Thanks in advance,
> Jeremy

Hi Jeremy,

Under Synthesis properties (right hand click synthesis in the tool chain 
view), select the Xilinx Specific Options tab then untick "Add I/O 
buffers" and you should be where you want to be!

As a note you may also wish to select "Advanced options" to allow more 
control over the tools (from the menu bar Edit > Preferences > Processes 
 > PropertyDisplayLevel change to Advanced).

However, more realistic timing can often be obtained by placing you 
design unit (presumably will ultimately be located deep within your 
design, eg a super fast multiplier) between registers, adding timing 
constraints and use the static timing report....

All the best,

Tim

Article: 92174
Subject: Re: Aurora over Rocket IO and EDk
From: Duane Clark <dclark@junkmail.com>
Date: Wed, 23 Nov 2005 16:01:37 GMT
Links: << >>  << T >>  << A >>
beeraka@gmail.com wrote:
> Hi ,
>       Has anyone implemented a design using Aurora over Rocket IO in
> EDK...If so please point me to the correct document....
>        What I am trying to do is to hook up a BRAM in an OPB core to
> send data to the Rocket I/O through Aurora and then on the Receiver
> side, use a BRAM to receieve the data...
>        I wrote the code but I have lots of questions regarding
> generating the differential clock and the RESET..So if anyone can help
> me out, then that would be great..
>        Thanks in advance....
> 

When you generate the aurora core with coregen, the generated files 
include not only a decent document explaining that in quite a bit of 
detail, but also an example top level file showing in detail how to make 
those connections.



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