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I am using the following code to test the Ken Chapman's UART. When I
run the following code and see the FIFO data at the 'command' output,
I do not get 'A' as intended by the design. Instead, I get some other
bit patterns that doesn't make sense. Can anyone see what I am doing
wrong with the testbench. Also, I am assuming that I do not need to
tamper with the underlying Ken Chapman UART!
module behavioural_UART_Tx
#(parameter bit_time = 104000) // nanoseconds @ 9600 bps
(output reg line);
initial
line = 1'b1; // line idles true
task send(input [7:0] data);
reg [9:0] uart_frame;
begin
// construct the whole frame with start and stop bit
// STOP data START
uart_frame = {1'b1, data, 1'b0};
repeat (10) // number of bit-symbols to send
begin
line = uart_frame[0]; // drive line to correct level
uart_frame = uart_frame >> 1; // prepare next bit
#(bit_time); // hold output for one bit time
end
end
endtask
endmodule
module TB;
wire line;
// And any other signals you need for your DUT
// such as clock, reset, data-bus...
reg clk;
reg xreset;
wire buffer_full;
wire present;
wire baud;
wire [7:0] command;
// And any clock generators, etc...
// declared inside RX and TX module
always #3.2 clk = ~clk; //155.52 Mhz input
// Here's the UART signal generator...
behavioural_UART_Tx DUT0(.line(line));
Top_Rx DUT1(
.serial_in(line),
.data_out_rx(command),
.read_buffer_rx(1'b0), //read buffer enabled
.en_16_x_baud(baud),
.clk(clk),
.buffer_present_rx(present),
.buffer_full_rx(buffer_full),
.xreset(xreset));
baud_timer DUT2(
.clk(clk),
.reset(xreset),
.en_16_x_baud(baud));
initial begin: StimGen
// Hang around for a while...
clk = 0;
//reset_buffer = 1;
#50;
xreset = 1;
#50 xreset = 0;
// Use the Tx model to send a few characters to the DUT:
#200000;
DUT0.send("B"); //reset device
// Idle awhile:
#200000;
// Send a newline character (LF = 10)
//tx_model.send(10);
end
endmodule
Article: 141401I am very new to working on the microblaze and the XPS environment. Can anybody please guide me on how to interface my 512 mb kingston RAM with microblaze using xps?? i am working on a digilent board.Article: 141402
Gabour, Should there be any relation between SYSTEM CLK and SCL if we have to apply debouncing ckt?Article: 141403
>Gabour, >Should there be any relation between SYSTEM CLK and SCL if we have to >apply debouncing ckt? > > > > > Gabor, One more question. have u taken care of repeated start condition in the above code?Article: 141404
On Jun 23, 7:54=A0am, "Vikas" <vikas.lakhan...@kpitcummins.com> wrote: > Gabour, > Should there be any relation between SYSTEM CLK and SCL if we have to > apply debouncing ckt? Assuming that the system clock is much faster than SCL, there is no need to assume any synchronization between the two. In fact the rise time of SCL under worst case condition could span more than one cycle of the system clock. This was the purpose of adding the de-glitch circuit. In my code I used the same debounce / de-glitch circuit for both SCL and SDA so the delays would be the same going into the state machine. Regards, GaborArticle: 141405
On Jun 23, 8:23=A0am, "Vikas" <vikas.lakhan...@kpitcummins.com> wrote: > >Gabour, > >Should there be any relation between SYSTEM CLK and SCL if we have to > >apply debouncing ckt? > > Gabor, > =A0One more question. have u taken care of repeated start condition in th= e > above code? The code makes no distinction between a normal start and a repeated start. As far as I know it should work in either case. Regards, GaborArticle: 141406
On 23 June, 13:32, gabor <ga...@alacron.com> wrote: > On Jun 23, 7:54=A0am, "Vikas" <vikas.lakhan...@kpitcummins.com> wrote: > > > Gabour, > > Should there be any relation between SYSTEM CLK and SCL if we have to > > apply debouncing ckt? > > Assuming that the system clock is much faster than SCL, there is no > need to assume any synchronization between the two. =A0In fact the > rise time of SCL under worst case condition could span more than > one cycle of the system clock. =A0This was the purpose of adding > the de-glitch circuit. =A0In my code I used the same debounce / > de-glitch circuit for both SCL and SDA so the delays would be the > same going into the state machine. > > Regards, > Gabor When the rise time is known, as it generally is, I use a sample period approximately equal to the rise time. Then you don't need de- glitching logic.Article: 141407
On Jun 23, 12:51 am, rickman <gnu...@gmail.com> wrote: > On Jun 22, 6:33 pm, Mike Treseler <mtrese...@gmail.com> wrote: > > > rickman wrote: > > > I used that in an > > > earlier design and it uses about 300 LUTs for the multiplier. I have > > > lots of clock cycles, so I can generate the partial products > > > sequentially using much less logic. > > > Less than 200 LUTs? > > > -- Mike Treseler > > Are you joking? I expect it to be on the order of 40 LUTs for a 16 x > 16 multiplier. Maybe I am not making myself clear. I am calculating > one partial product at a time and adding them to the product > sequentially using the same hardware, but multiple clock cycles. Sort > of like a bit serial adder, but this is a partial product serial > multiplier or maybe you could call it a multiplier bit serial > multiplier. A truely bit serial multiplier could be done in a dozen > to twenty LUTs I expect, but a 16x16 multiply would take 256 clock > cycles. > > I actually considered this on an earlier design, but it turned out I > didn't need to push on the LUTs used and the X*Y multiplier took some > 300 LUTs. So going down to 40 or 50 LUTs is a big improvement. I > should have this done later this week and I'll post the results. > > Rick My estimate was off by a little as I forgot to account for the extra rank of muxes required to load the initial values. So the total for a 16 x 16 add and shift sequential multiplier is 60 LUTs as reported by the Lattice tools. This drops by about 10 LUTs if the counter is removed. In my design the timing may be controlled by logic elsewhere. Yes, somehow Synplify is using 10 LUTs to build a four bit counter! It seems to want to duplicate three of the four FFs. RickArticle: 141408
Hello everybody, is it possible to implement a 10Gbit ethernet phy interface in a simple spartan3 device? As far as I know, the XAUI uses 4 x 3.2 Gbps line, this is undoubtedly highly above the capabilities of a spartan chip, but maybe it can be done with external serializers/ deserializers? I think XGMII wouldn't work because of 156.25 MHz DDR data rate, but I'm not absolutely sure.. What do you think about that? Is that a crazy idea? Why? Let assume that the sent and received data can be processed if the phy connection is solved.. DaveArticle: 141409
On Tue, 23 Jun 2009 07:52:07 -0700, David Fejes wrote: > Hello everybody, > > is it possible to implement a 10Gbit ethernet phy interface in a simple > spartan3 device? As far as I know, the XAUI uses 4 x 3.2 Gbps line, this > is undoubtedly highly above the capabilities of a spartan chip, but > maybe it can be done with external serializers/ deserializers? I think > XGMII wouldn't work because of 156.25 MHz DDR data rate, but I'm not > absolutely sure.. > > What do you think about that? Is that a crazy idea? Why? Let assume that > the sent and received data can be processed if the phy connection is > solved.. > > Dave You would have to use an external SerDes with a Spartan3. The Virtex5LXT has built in SerDes. I think Spartan6 will have SerDes but they don't exist yet. The Altera ArriaII GX will also have built in SerDes, some of those parts are available now.Article: 141410
Hallo I'm trying to realise an index access to an array within a process environment. It looks like this: s_lcd_data <= ROM(i), where i is the index, declared as variable integer. But it doesn't work. When I write the number instead of i, no problem. Are there any restriction for a variable use within a process? TomArticle: 141411
On Tue, 23 Jun 2009 18:59:30 +0200, "Dr. Thomas Ansorg" wrote: >I'm trying to realise an index access to an array within a process >environment. It looks like this: >s_lcd_data <= ROM(i), where i is the index, declared as variable integer. So far, so good. >But it doesn't work. Could you be even a little bit more specific? The set of non-working code examples is rather large. Does it compile? Elaborate? Simulate? Synthesize? Does it build hardware that then doesn't perform as you expect? Sheesh, any one of those might "not work". Please do us the courtesy of asking yourself what your question looks like to a reader. Also, it looks as though the example is VHDL, so you would probably do better to take the question to comp.lang.vhdl since it's a language question rather than an FPGA implementation issue. >When I write the number instead of i, no problem. So it seems likely that the value of 'i' is out of range when you make the access. > Are there any restriction for a > variable use within a process? Of course there are some places where you can use a constant but not a variable; similarly, there are places where only a signal will do. But an integer variable is perfectly legal as an array subscript if the array is indexed by integer. Indeed, any expression that yields an integer result is OK. But of course the integer value must be within bounds. Are you aware that VHDL integers are initialized to a large negative value, not to zero? If the process is to be synthesized, there will be further restrictions to do with the fact that your code must represent implementable hardware. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 141412
> > Could you be even a little bit more specific? > The set of non-working code examples is rather large. > Does it compile? Elaborate? Simulate? Synthesize? > Does it build hardware that then doesn't perform > as you expect? Sheesh, any one of those might > "not work". Please do us the courtesy of > asking yourself what your question looks like > to a reader. Compile, syntesize and implementation is no problem. Btw, I use a Spartan3E-Board > > Also, it looks as though the example is VHDL, so > you would probably do better to take the question > to comp.lang.vhdl since it's a language question > rather than an FPGA implementation issue. > >>When I write the number instead of i, no problem. > > So it seems likely that the value of 'i' is out of > range when you make the access. No. I put a condition in the source code that i cannot be greater than 39, and the array has 40 elements (0 to 39). > >> Are there any restriction for a >> variable use within a process? > > Of course there are some places where you can use > a constant but not a variable; similarly, there > are places where only a signal will do. But > an integer variable is perfectly legal as an array > subscript if the array is indexed by integer. > Indeed, any expression that yields an integer > result is OK. But of course the integer value > must be within bounds. Are you aware that VHDL > integers are initialized to a large negative > value, not to zero? Yes, I am. So i is initialized with 0. The whole code is for putting out characters from the array to the onboard lcd. s_lcd_data is the 8 bit vector to be sent to the lcd. The code for itself works: s_lcd_data <= x"65" puts out the character defined by ascii code 65h (no idea which one that is) TomArticle: 141413
On Tue, 23 Jun 2009 19:56:28 +0200, "Dr. Thomas Ansorg" wrote: >Compile, syntesize and implementation is no problem. What happens in simulation? Without simulation you are guessing - groping around in the dark. Surely it must be clear to you by now: if you announce "I have a problem", without saying rather precisely what that problem is, then no matter how skilful or well-meaning we may be, we will be be utterly unable to help you. Extra-sensory perception is not one of the RFCs supported by my ISP. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 141414
On Jun 23, 1:56=A0pm, "Dr. Thomas Ansorg" <dl7...@online.de> wrote: > No. I put a condition in the source code that i cannot be greater than 39= , > and the array has 40 elements (0 to 39). Could i be less than 0? Does your code work as expected in simulation? Do you see any warnings during synthesis about things being optimized away and removed, which seems like they shouldn't be removed? What behavior are you seeing when the code doesn't work? Please be specific. DaveArticle: 141415
Dr. Thomas Ansorg wrote: > I'm trying to realise an index access to an array within a process > environment. It looks like this: > s_lcd_data <= ROM(i), where i is the index, declared as variable > integer. see that address input in this example: http://mysite.verizon.net/miketreseler/sync_rom.vhdArticle: 141416
On Jun 23, 7:23=A0am, rickman <gnu...@gmail.com> wrote: > On Jun 23, 12:51 am, rickman <gnu...@gmail.com> wrote: > > > > > > > On Jun 22, 6:33 pm, Mike Treseler <mtrese...@gmail.com> wrote: > > > > rickman wrote: > > > > I used that in an > > > > earlier design and it uses about 300 LUTs for the multiplier. =A0I = have > > > > lots of clock cycles, so I can generate the partial products > > > > sequentially using much less logic. > > > > Less than 200 LUTs? > > > > =A0 =A0 =A0 -- Mike Treseler > > > Are you joking? =A0I expect it to be on the order of 40 LUTs for a 16 x > > 16 multiplier. =A0Maybe I am not making myself clear. =A0I am calculati= ng > > one partial product at a time and adding them to the product > > sequentially using the same hardware, but multiple clock cycles. =A0Sor= t > > of like a bit serial adder, but this is a partial product serial > > multiplier or maybe you could call it a multiplier bit serial > > multiplier. =A0A truely bit serial multiplier could be done in a dozen > > to twenty LUTs I expect, but a 16x16 multiply would take 256 clock > > cycles. > > > I actually considered this on an earlier design, but it turned out I > > didn't need to push on the LUTs used and the X*Y multiplier took some > > 300 LUTs. =A0So going down to 40 or 50 LUTs is a big improvement. =A0I > > should have this done later this week and I'll post the results. > > > Rick > > My estimate was off by a little as I forgot to account for the extra > rank of muxes required to load the initial values. =A0So the total for a > 16 x 16 add and shift sequential multiplier is 60 LUTs as reported by > the Lattice tools. =A0This drops by about 10 LUTs if the counter is > removed. =A0In my design the timing may be controlled by logic > elsewhere. =A0Yes, somehow Synplify is using 10 LUTs to build a four bit > counter! =A0It seems to want to duplicate three of the four FFs. > > Rick- Hide quoted text - > > - Show quoted text - Hi Rick, Can you show me where I can find the schematics of Lattice doing 16x16 for 60 LUT? Do 60 LUTs include 32-bit flip-flops to store output data? WengArticle: 141417
Hi all
Just curious about the EPM7064 Altera CPLD. I designed a small
system around it and I am curious how necessary it is to tie down
Oe1 and Oe2 to ground and Gclr to Vcc.
Currently I only have Oe1 grounded the others left floating and Gclk1
connected to my oscillator.
My code is simple and clean but the outputs (after downloading to the
device) appear to be floating ... which leads me to believe I may need
to ground Oe2 and tie Gclr to a pullup
Anyone here with knowledge/experience working with Altera CPLD's?
Thanks in advance
Article: 141418Aldorus wrote: > My code is simple and clean but the outputs (after downloading to the > device) appear to be floating ... which leads me to believe I may need > to ground Oe2 and tie Gclr to a pullup Yes.Article: 141419
Hello: I have a XUPV2P board and I am using EDK 10.1 trying to boot the FPGA board from the compact flash driver using the uClinux executable file. After I change the Project Peripheral Repository in the Project Options window, rescan user repository, and select uclinux from the dropdown list of OS, I can not find the main_memory name in the OS and Libraries window. Dose any one knows how I can fix this. ThanksArticle: 141420
I have read through this thread and was hoping to solicit some help. Here is my problem. Impact does not find USB II cable using libusb. It works fine for me with ISE 10.1.03. -My OS is Suse Linux 64 bit Enterprise Desktop 11 -I have libusb and fxload packages installed (works fine with ISE 10.1.03) -I have run the setup_pcusb script -I have tried setting XIL_IMPACT_USE_LIBUSB env var to 0, 1, and not defined. -I have tried creating a soft link in my home directory named libusb.so in my home directory to /usr/lib/libusb-0.1.so.4.4.4 -I have tried creating a soft link in my home directory named libusb.so in my home directory to /usr/lib64/libusb-0.1.so.4.4.4 -The USB cable LED turns green when it is plugged into computer -USB II cable and target are proven good because it works when I switch back to ISE 10.1.03 Any ideas or thoughts would be most appreciated. I am a Linux newbie and not sure what else to try.Article: 141421
>On 23 June, 13:32, gabor <ga...@alacron.com> wrote:
>> On Jun 23, 7:54=A0am, "Vikas" <vikas.lakhan...@kpitcummins.com> wrote:
>>
>> > Gabour,
>> > Should there be any relation between SYSTEM CLK and SCL if we have
to
>> > apply debouncing ckt?
>>
>> Assuming that the system clock is much faster than SCL, there is no
>> need to assume any synchronization between the two. =A0In fact the
>> rise time of SCL under worst case condition could span more than
>> one cycle of the system clock. =A0This was the purpose of adding
>> the de-glitch circuit. =A0In my code I used the same debounce /
>> de-glitch circuit for both SCL and SDA so the delays would be the
>> same going into the state machine.
>>
>> Regards,
>> Gabor
>
>When the rise time is known, as it generally is, I use a sample period
>approximately equal to the rise time. Then you don't need de-
>glitching logic.
>
Thanks for the Help Gabor!
Mine SCL frequency is 1 Mhz. What should be the frequency of system clock
on which I should debounce it?Is 8 Mhz enough?
// Debounce, then delay debounced signals for edge detection
begin
sda_sr <= {sda_sr[2:0], sda_in};
if (sda_sr == 4'b0000) sda <= 0;
else if (sda_sr == 4'b1111) sda <= 1;
was_sda <= sda;
scl_sr <= {scl_sr[2:0], scl_in};
if (scl_sr == 4'b0000) scl <= 0;
else if (scl_sr == 4'b1111) scl <= 1;
was_scl <= scl;
end
One more doubt in above code.. Why r u checking for 0000 and 1111 values
only. As per me if the four bit registers hold three 1's, SDA should be 1
and if three bits are 0 then SDA should 0.
Can I have your Personal Email ID as well?
Thanks for the help sir!!!
Article: 141422Hi, i'm using the Virtex 4 MB LX60 development Board from Memec. (http://em.avnet.com/ctf_shared/evk/df2df2usa/Xilinx_Virtex-4_LX- SX_MB_Development_Kit-Product_Brief.pdf) I would like to use multiple bit-files that can be choosen with jumpers for flashing the FPGA. With Impact from Xilinx I generate the prom files. Some hints how you do this typically would be great.Article: 141423
Chet <chetferry@comcast.net> wrote: > I have read through this thread and was hoping to solicit some help. Here > is my problem. > Impact does not find USB II cable using libusb. It works fine for me with > ISE 10.1.03. > > -My OS is Suse Linux 64 bit Enterprise Desktop 11 > -I have libusb and fxload packages installed (works fine with ISE > 10.1.03) > -I have run the setup_pcusb script > -I have tried setting XIL_IMPACT_USE_LIBUSB env var to 0, 1, and not > defined. > -I have tried creating a soft link in my home directory named libusb.so in > my home directory to > /usr/lib/libusb-0.1.so.4.4.4 > -I have tried creating a soft link in my home directory named libusb.so in > my home directory to > /usr/lib64/libusb-0.1.so.4.4.4 > > -The USB cable LED turns green when it is plugged into computer > -USB II cable and target are proven good because it works when I switch > back to ISE 10.1.03 > Any ideas or thoughts would be most appreciated. I am a Linux newbie and > not sure what else to try. What does 'lsusb' report? How are the permissions on the node set? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 141424
hi all,
As promised many weeks ago, I'm building what I
hope will be a comprehensive summary of how to do
RAM inference from VHDL and Verilog code for all
the common synthesis tools and FPGAs. It will
go on our website some time this summer (sorry,
it's not a high-priority project).
I've encountered what seems to me to be a bug
in XST (all versions from 8 to 11 inclusive)
and I would value your opinion before I start
to give Xilinx a hard time about it. By the
way, exactly the same bug appears to be present
in Quartus but I haven't yet done enough detailed
investigation to comment on that properly.
To create true (dual-clock) dual-port RAM,
I need to create two clocked processes. This
requires me to use a shared variable for
the memory itself (ugly but possible, works
correctly in XST):
type t_mem is array (0 to 2**ABITS-1) of
std_logic_vector(DBITS-1 downto 0);
shared variable mem: t_mem; -- the memory storage
begin -- the architecture
process (clock0) -- manages port A
begin
if rising_edge (clock0) then
if we0 = '1' then -- write to port A
mem(to_integer(unsigned(a0))) := wd0;
rd0 <= wd0;
else
rd0 <= mem(to_integer(unsigned(a0)));
end if;
end if;
end process;
--
process (clock1) -- manages port B
begin
if rising_edge (clock1) then
if we1 = '1' then
mem(to_integer(unsigned(a1))) := wd1;
rd1 <= wd1;
else
rd1 <= mem(to_integer(unsigned(a1)));
end if;
end if;
end process;
That, I believe, is the right way to do it.
However, both XST and Quartus give THE SAME SYNTHESIS
RESULTS if I change "shared variable" to "signal", and
make signal assignments instead of variable assignments
to the mem() array. This is just plain WRONG! Writing
to a signal from two processes represents two resolved
drivers on the signal, and does not correctly model a
dual-port memory in simulation.
Given that the whole point of memory inference from
HDL code is that you get a convenient, readable,
accurate simulation model as part of your design
code, this behaviour by the synthesis tools is
incomprehensible to me. Can anyone clarify? Has
anyone fallen foul of this problem? Best of all,
could Brian Philofsky, who has written so clearly
and helpfully about XST in the past, please speak
up and tell us what the blazes is going on here?
Thanks
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
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