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Messages from 141450

Article: 141450
Subject: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
From: Antti <Antti.Lukats@googlemail.com>
Date: Wed, 24 Jun 2009 12:14:12 -0700 (PDT)
Links: << >>  << T >>  << A >>
Bitstreams must not contain a sync word followed by all 1=92s. This
condition might
cause damage to the device.

Is this an feature or bug? should this go into ERRATA and be fixed
ASAP??

Antti

Article: 141451
Subject: Re: True dual-port RAM in VHDL: XST question
From: "Fredxx" <fredxx@spam.com>
Date: Wed, 24 Jun 2009 20:43:39 +0100
Links: << >>  << T >>  << A >>

"Muzaffer Kal" <kal@dspia.com> wrote in message 
news:4ul445tbv9klgrceumj15dd2jfcpjp4raq@4ax.com...
> On Wed, 24 Jun 2009 16:27:30 +0100, "Fredxx" <fredxx@spam.com> wrote:
>>The asynchronous memory is an array of flip-flops rather than a memory, 
>>but
>>that's a mute point.  It does both synthesise and simulate in Xilinx ISE
>>tools.
>>
> Flip-flops need a clock to function. How do you write to them without
> a clock to implement asynchronous memory (which by definition doesn't
> have it?). You can use an array of latches as opposed to flip-flops
> but timing latches is quite difficult especially in an fpga context
> where tools are really not geared towards it. You maybe able to
> synthesize it in ISE and the original code simulates for sure but have
> you tried a back-annotated gate level simulation? It would be an
> interesting challenge to get it to work fully unless your read/write
> pulse widths and separations are extremely conservative.
> One last to remember is that there are a lot fewer slice registers
> (from which latches are made) than memory bits in an FPGA so you're
> quite limited in how much async memory of this type you can make.

Different types of flip flops can be inferred by VHDL.  Not all have to use 
the global clock, or even a clock as such.

True - if it was my problem, I would look at the logic it creates, but at 
the moment I don't have time.



Article: 141452
Subject: Re: True dual-port RAM in VHDL: XST question
From: Andy Peters <google@latke.net>
Date: Wed, 24 Jun 2009 13:02:06 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jun 24, 10:57=A0am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> I'm trying to assemble a complete and accurate list
> of the _synthesizable_ templates for all common types
> of FPGA memory, and I have discovered a template
> that synthesizes to dual-clock RAM in two FPGA
> vendors' tools but is a complete nonsense for
> simulation. =A0I want to know why this has happened,
> what we can do about it, and why the vendors haven't
> already been beaten to pulp over it by users.

The vendors say, "Instantiate the component from the library," which
neatly sidesteps the difficult work of actually enabling such
inference.

-a

Article: 141453
Subject: 720 Mhz IF Processing
From: recoder <kurtulmehtap@gmail.com>
Date: Wed, 24 Jun 2009 13:15:46 -0700 (PDT)
Links: << >>  << T >>  << A >>
 We are used to process 70 Mhz IF by using ADC boards to interface to
our fpga boards.
Now we have to process the following signal:
720 Mhz IF
qpsk modulated
 80 mhz bandwith (3 dB)

Can anybody recommend a board to interface the 720 Mhz IF to a FPGA
board?




Article: 141454
Subject: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
From: Andy <jonesandy@comcast.net>
Date: Wed, 24 Jun 2009 13:17:55 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jun 24, 2:14=A0pm, Antti <Antti.Luk...@googlemail.com> wrote:
> Bitstreams must not contain a sync word followed by all 1=92s. This
> condition might
> cause damage to the device.
>
> Is this an feature or bug? should this go into ERRATA and be fixed
> ASAP??
>
> Antti

Someone might have a use for that...

Andy

Article: 141455
Subject: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
From: "Antti.Lukats@googlemail.com" <Antti.Lukats@googlemail.com>
Date: Wed, 24 Jun 2009 13:26:51 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jun 24, 11:17=A0pm, Andy <jonesa...@comcast.net> wrote:
> On Jun 24, 2:14=A0pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > Bitstreams must not contain a sync word followed by all 1=92s. This
> > condition might
> > cause damage to the device.
>
> > Is this an feature or bug? should this go into ERRATA and be fixed
> > ASAP??
>
> > Antti
>
> Someone might have a use for that...
>
> Andy

Altera making Xilinx-Virus?

humm that not so funny actually...
Antti

Article: 141456
Subject: Re: index in arrays doesn't work
From: Andy <jonesandy@comcast.net>
Date: Wed, 24 Jun 2009 13:47:13 -0700 (PDT)
Links: << >>  << T >>  << A >>
There is nothing inherently wrong with using variables instead of
signals, but they do behave differently, which can also result in
different hardware being synthesized.

You may be having an issue with the time-varying value of i, that is
not apparent when you use a constant instead. If i does not have the
value you intended, when you intended it, then it won't work as you
intended.

Given the temporal behvioral differences between variabls and signals
(immediate vs postponed  updates), using a signal for i instead of a
variable may cause the circuit to behave as you expected, if you did
not take into account the immediate updates to variables.

It is really hard to debug your problem with the limited information
you gave us.

What does it do when it is not working?


Andy

Article: 141457
Subject: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
From: "Fredxx" <fredxx@spam.com>
Date: Wed, 24 Jun 2009 21:49:41 +0100
Links: << >>  << T >>  << A >>
Antti wrote:
> Bitstreams must not contain a sync word followed by all 1ís. This
> condition might
> cause damage to the device.
>
> Is this an feature or bug? should this go into ERRATA and be fixed
> ASAP??
>
> Antti

Perhaps Spartan 6 can be added to this list!!

http://en.wikipedia.org/wiki/Halt_and_Catch_Fire



Article: 141458
Subject: Re: 720 Mhz IF Processing
From: spope33@speedymail.org (Steve Pope)
Date: Wed, 24 Jun 2009 20:52:57 +0000 (UTC)
Links: << >>  << T >>  << A >>
recoder  <kurtulmehtap@gmail.com> wrote:

> We are used to process 70 Mhz IF by using ADC boards to interface to
>our fpga boards.
>Now we have to process the following signal:
>720 Mhz IF
>qpsk modulated
> 80 mhz bandwith (3 dB)
>
>Can anybody recommend a board to interface the 720 Mhz IF to a FPGA
>board?

You probably don't want a board.  You probably want a 
connectorized quadrature mixer, and a connectorized local
oscillator, with the mixer output feeding a dual ADC board.

Seek out an RF engineer to specify, assemble, and test this puppy.

Steve

Article: 141459
Subject: Re: Virtex-6 shipping?
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Wed, 24 Jun 2009 21:42:00 +0000 (UTC)
Links: << >>  << T >>  << A >>
Ed McGettigan <ed.mcgettigan@xilinx.com> wrote:
> Antti wrote:

> ISE - http://www.xilinx.com/tools/designtools.htm
> V-6 - http://www.xilinx.com/products/virtex6/
> S-6 - http://www.xilinx.com/products/spartan6/


Why do I learn about this in the newsgroup and not by a mail from XILINX? 
I subscribe to XILINX for news about the -6 series...

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 141460
Subject: Cable autodetection/programming the Xilinx Virtex2Pro FPGA failing.
From: Pratap <pratap.iisc@gmail.com>
Date: Wed, 24 Jun 2009 15:24:43 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,
I was using the USB cable provided with Xilinx Vertex 2Pro board in my
PC earlier. Recently I upgraded my PC to Intel Core2Duo Processor and
it's corresponding mother board. Also I have added another NetMOS PCI
ECP Parallel port add on as there was no parallel port by default on
the mother board.
But now I am not able to program the FPGA board.
Here are the error messages I get when I do   "Output" ---> "Cable
Auto Detect"

*************************
Welcome to iMPACT
// *** BATCH CMD : loadProjectFile -file "E:/vhdl_proj/
for_2_exp_19_samples/for_2_exp_19_samples.ipf"
'1': Loading file 'E:/vhdl_proj/for_2_exp_19_samples/
top_module_26th_may_ratioed_avg_for_2exp19_samples.bit' ...
done.
INFO:iMPACT:1777 -
Reading C:/Program Files/Xilinx91i/virtex2p/data/xc2vp30.bsd...
WARNING:iMPACT:2257 - Startup Clock has been changed to 'JtagClk' in
the bitstream stored in memory,
but the original bitstream file remains unchanged.
INFO:iMPACT:501 - '1': Added Device xc2vp30 successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
Active mode is BS
// *** BATCH CMD : setMode -ss
// *** BATCH CMD : setMode -sm
// *** BATCH CMD : setMode -hw140
// *** BATCH CMD : setMode -spi
// *** BATCH CMD : setMode -acecf
// *** BATCH CMD : setMode -acempm
// *** BATCH CMD : setMode -pff
// *** BATCH CMD : setMode -bs
// *** BATCH CMD : setMode -bs
// *** BATCH CMD : setMode -bs
// *** BATCH CMD : setMode -bs
GUI --- Auto connect to cable...
// *** BATCH CMD : setCable -port auto
AutoDetecting cable. Please wait.
PROGRESS_START - Starting Operation.
Connecting to cable (Parallel Port - LPT1).
Checking cable driver.
 Driver windrvr6.sys version = 8.1.0.0.Connecting to cable (Parallel
Port - LPT2).
Checking cable driver.
 Driver windrvr6.sys version = 8.1.0.0.Connecting to cable (Parallel
Port - LPT3).
Checking cable driver.
 Driver windrvr6.sys version = 8.1.0.0.Connecting to cable (Parallel
Port - LPT4).
Checking cable driver.
 Driver windrvr6.sys version = 8.1.0.0.Connecting to cable (Usb Port -
USB21).
Checking cable driver.
 Driver xusbdfwu.sys version: 1021 (1021).
 Driver windrvr6.sys version = 8.1.0.0.Cable connection failed.
PROGRESS_END - End Operation.
Elapsed time =      2 sec.
Cable autodetection failed.
*************************

I have no idea how to make the cable detectable now. When I plugin the
Xilinx cable, it asks for the drivers and automatically detects them
after a click. But still I am not able to load my program into the
FPGA board.
Waiting for a response.
-Pratap

Article: 141461
Subject: Re: True dual-port RAM in VHDL: XST question
From: Alex <enginven@gmail.com>
Date: Wed, 24 Jun 2009 18:43:43 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jun 24, 10:57=A0am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Wed, 24 Jun 2009 08:31:26 -0700 (PDT), Sandro wrote:
> >If you are curious please take a look to the vhdl VITAL
> >simulations sources...
>
> I know about the vendor-provided simulation models,
> which are fine pieces of work that do their job well.
> But they are completely irrelevant both to my original
> problem and to the issue I asked about. =A0
>
> I'm trying to assemble a complete and accurate list
> of the _synthesizable_ templates for all common types
> of FPGA memory, and I have discovered a template
> that synthesizes to dual-clock RAM in two FPGA
> vendors' tools but is a complete nonsense for
> simulation. =A0I want to know why this has happened,
> what we can do about it, and why the vendors haven't
> already been beaten to pulp over it by users.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.


The truth is that current FPGA Synthesis tools quite often do a poor
job (not counting trivial cases here) in inference of FPGA vendors'
macros. From the other hand FPGA vendors want users to instantiate
their macros (and so to be locked into their devices) and make it very
easy to configure and generate the code for instantiation using
proprietary vendor tools.
So majority of users prefers to instantiate the macros as a better
alternative to make the Synthesis tools infer the necessary structure
(and lose sometimes days on debugging different synthesis attributes,
directives etc...)
Just wanted to offer a possible explanation in answer to your
question, Jonathan :^)

Theoretically, independent FPGA synthesis tools vendors (Mentor,
Synopsys)  should be interested for users to create a vendor
independent code. This way they'll have a much stronger case for multi-
vendor tools...

Alex Yourovski

Article: 141462
Subject: Re: Subtleties of Booth's Algorithm Implementation
From: rickman <gnuarm@gmail.com>
Date: Wed, 24 Jun 2009 20:00:13 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jun 24, 2:57=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote:
> On Jun 24, 9:54=A0am, Mike Treseler <mtrese...@gmail.com> wrote:
>
>
>
> > rickman wrote:
> > > I was able to get a schematic from Synplify Pro, but it did not want
> > > to include the text except on part of the drawing. =A0If anyone can t=
ell
> > > me how to get the text to display, I will reprint it. =A0The PDF file
> > > can be found athttp://arius.com/stuff/FPGA/Multiply_16x16.pdf
>
> > Don't know about synplify.
> > Does it have an RTL viewer also?
>
> > > This incarnation uses 62 LUTs and 42 FFs if I am reading the info
> > > correctly. =A0This includes 32 FFs to hold the output product. =A0The
> > > Multiplicand is not registered, it is assumed that it is held constan=
t
> > > on the input.
>
> > That should be ok if the enable is synchronized.
> > Interesting. Thanks for the posting.
>
> > > Also, I have not simulated it to be sure it is coded correctly, but I
> > > am pretty confident it is working the way I intend or at least any
> > > mistakes won't change the LUT count much.
>
> > I prefer to start with an RTL sim,
> > but I know that many designers prefer
> > working on the bench. Good luck.
>
> > =A0 =A0 =A0 =A0 -- Mike Treseler
>
> Hi Rick,
> The file published athttp://arius.com/stuff/FPGA/Multiply_16x16.pdf
> has some flaws:
> I cannot see the texts after 4 clicks in width direction with 400%
> magnification. It means the first 3 clicks in width show normal
> drawings, but after that only schematics are shown normally, but no
> texts are shown.
>
> Is it normal?
>
> Weng


Yes, I know the print is not very good, but that is the best I could
get out of Synplify.  The only way I could get any text at all was to
set the magnification to the lowest level that would still display
text.  Then only the portion visible on my screen would print with
text.  The rest shows nothing.  The large squares are two bit adder
primitives and the smaller rectangles are FFs.  The rest is pretty
obvious since they show the gates.

Like I said, if anyone knows how to get Synplify to print the entire
schematic with text, I'll be happy to post that.  I can email you the
code if you would like to see that.  But like I said, there is nothing
here that isn't pretty obvious other than that you need an extra msb
to preserve sign if you need to support the most negative number (-2**
(n-1)).

Rick

Article: 141463
Subject: Re: Virtex-6 shipping?
From: "Antti.Lukats@googlemail.com" <Antti.Lukats@googlemail.com>
Date: Wed, 24 Jun 2009 21:21:39 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jun 25, 12:42=A0am, Uwe Bonnes <b...@elektron.ikp.physik.tu-
darmstadt.de> wrote:
> Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
> > Antti wrote:
> > ISE -http://www.xilinx.com/tools/designtools.htm
> > V-6 -http://www.xilinx.com/products/virtex6/
> > S-6 -http://www.xilinx.com/products/spartan6/
>
> Why do I learn about this in the newsgroup and not by a mail from XILINX?
> I subscribe to XILINX for news about the -6 series...
>
> --
> Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar=
mstadt.de
>
> Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt
> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

hm yeah, i subscribed too if i now recall
Xilinx promised: "To be first to know"... then subscribe
but they did not keep up their promise, there is no
notification from Xilinx, just the data and downloads
appeared at the their website


Antti


Article: 141464
Subject: Re: 720 Mhz IF Processing
From: recoder <kurtulmehtap@gmail.com>
Date: Thu, 25 Jun 2009 00:47:00 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 24 Haziran, 23:52, spop...@speedymail.org (Steve Pope) wrote:
> recoder =A0<kurtulmeh...@gmail.com> wrote:
> > We are used to process 70 Mhz IF by using ADC boards to interface to
> >our fpga boards.
> >Now we have to process the following signal:
> >720 Mhz IF
> >qpsk modulated
> > 80 mhz bandwith (3 dB)
>
> >Can anybody recommend a board to interface the 720 Mhz IF to a FPGA
> >board?
>
> You probably don't want a board. =A0You probably want a
> connectorized quadrature mixer, and a connectorized local
> oscillator, with the mixer output feeding a dual ADC board.
>
> Seek out an RF engineer to specify, assemble, and test this puppy.
>
> Steve

Thanks, thats what I am looking for.
Does anybody know a module that can do the downconversion from 720 Mhz
to 70-140 Mhz IF?


Article: 141465
Subject: Re: 720 Mhz IF Processing
From: "Sebastien @ Sundance" <maury.sebastien@gmail.com>
Date: Thu, 25 Jun 2009 00:59:42 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jun 24, 11:15=A0pm, recoder <kurtulmeh...@gmail.com> wrote:
> =A0We are used to process 70 Mhz IF by using ADC boards to interface to
> our fpga boards.
> Now we have to process the following signal:
> 720 Mhz IF
> qpsk modulated
> =A080 mhz bandwith (3 dB)
>
> Can anybody recommend a board to interface the 720 Mhz IF to a FPGA
> board?

If you are looking at a complete system, you can check the SMT702 that
may do the job : http://www.sundance.com/web/files/productpage.asp?STRFilte=
r=3DSMT702

- Sebastien

Article: 141466
Subject: SRAM vs Flash based FPGA one more time
From: urock <yarumyantsev@gmail.com>
Date: Thu, 25 Jun 2009 01:15:07 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hello, everybody!

I have come with a question concerning FPGA technology. I understand
that this question has been already discussed here, but I still don't
understand one thing..

Everybody knows that from user point of view Flash based FPGA are
better because they are nonvvolatile, tolerable to radiation, do not
consume high current at startup and better secure intellectual
property. On the other hand SRAM FPGA are much easier to manufacture.

That's it? Being easier to manufacture is the point? I don't
understand why large vendors like Xilinx and Altera can not invest
money and design true Flash FPGA, like Actel did.

And the last question: why largest Actel FPGA chip (3 M system gates)
is much smaller than say largest Xilinx's chips? Is it still much
harder to manufacture larger Flash FPGA chip?

Thank you!

Article: 141467
Subject: Re: SRAM vs Flash based FPGA one more time
From: Gael Paul <gael.paul@gmail.com>
Date: Thu, 25 Jun 2009 01:50:49 -0700 (PDT)
Links: << >>  << T >>  << A >>
urock,

It simply comes down to manufacturing technology. Processes that
combine Flash and CMOS are typically 3 generations behind leading-edge
CMOS processes. As we speak, Actel's flash-based FPGAs are
manufactured at 130nm while the big guys have 40nm SRAM-based devices.
This leads to ~10X density advantage for SRAM over Flash FPGAs,
yielding larger and/or cheaper devices.

 - gael

Article: 141468
Subject: Re: Virtex-6 shipping?
From: Poojan Wagh <poojanwagh@gmail.com>
Date: Thu, 25 Jun 2009 02:29:39 -0700 (PDT)
Links: << >>  << T >>  << A >>
Went to a Xilinx class yesterday. Apparently, ISE 11.2 got released
yesterday. (Instructor said we should have an email in our Inbox.)
Also, ML605 (Virtex-6) and equivalent Spartan-6 eval boards are on
Xilinx' site: http://www.xilinx.com/products/devkits/EK-V6-ML605-G.htm.
However, it says that Virtex-6 boards will be available "in July". See
also: http://www.pldesignline.com/products/218101026

On Jun 24, 11:21=A0pm, "Antti.Luk...@googlemail.com"
<Antti.Luk...@googlemail.com> wrote:
> On Jun 25, 12:42=A0am, Uwe Bonnes <b...@elektron.ikp.physik.tu-
>
> darmstadt.de> wrote:
> > Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
> > > Antti wrote:
> > > ISE -http://www.xilinx.com/tools/designtools.htm
> > > V-6 -http://www.xilinx.com/products/virtex6/
> > > S-6 -http://www.xilinx.com/products/spartan6/
>
> > Why do I learn about this in the newsgroup and not by a mail from XILIN=
X?
> > I subscribe to XILINX for news about the -6 series...
>
> > --
> > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-d=
armstadt.de
>
> > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt
> > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
>
> hm yeah, i subscribed too if i now recall
> Xilinx promised: "To be first to know"... then subscribe
> but they did not keep up their promise, there is no
> notification from Xilinx, just the data and downloads
> appeared at the their website
>
> Antti


Article: 141469
Subject: Re: Virtex-6 shipping?
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Thu, 25 Jun 2009 09:44:10 +0000 (UTC)
Links: << >>  << T >>  << A >>
Antti.Lukats@googlemail.com <Antti.Lukats@googlemail.com> wrote:
> On Jun 25, 12:42†am, Uwe Bonnes <b...@elektron.ikp.physik.tu-
> darmstadt.de> wrote:
> > Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
> > > Antti wrote:
> > > ISE -http://www.xilinx.com/tools/designtools.htm
> > > V-6 -http://www.xilinx.com/products/virtex6/
> > > S-6 -http://www.xilinx.com/products/spartan6/
> >

> hm yeah, i subscribed too if i now recall
> Xilinx promised: "To be first to know"... then subscribe
> but they did not keep up their promise, there is no
> notification from Xilinx, just the data and downloads
> appeared at the their website

There are more User Guides, as mentioned in DS160 available like
http://www.xilinx.com/support/documentation/user_guides/ug384.pdf

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 141470
Subject: Re: True dual-port RAM in VHDL: XST question
From: Martin Thompson <martin.j.thompson@trw.com>
Date: Thu, 25 Jun 2009 11:03:25 +0100
Links: << >>  << T >>  << A >>
Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> writes:

> I completely agree.  One of the side-effects of the 
> survey I'm doing will probably be that I'll log requests
> for exactly this feature with all the synthesis vendors.
> I don't hold out much hope, though.  Support welcomed ;-)

You have mine!

And thanks for sharing the results of your investigations with us all!

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

Article: 141471
Subject: Re: SRAM vs Flash based FPGA one more time
From: =?KOI8-R?B?4NLBIPLVzdHOw8XX?= <yarumyantsev@gmail.com>
Date: Thu, 25 Jun 2009 03:52:18 -0700 (PDT)
Links: << >>  << T >>  << A >>
I got it, gael, thanks!

So you think that when moors law stops working (when manufacturing
process reaches 20 nm), all FPGAs will be Flash-based? I mean will in
your opinion flash technology catch up with cmos?

Article: 141472
Subject: Re: True dual-port RAM in VHDL: XST question
From: "Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk>
Date: Thu, 25 Jun 2009 11:55:44 +0100
Links: << >>  << T >>  << A >>
> Originally coming from ASIC side I find this incredible but it seems
> that majority of people doing FPGA design don't simulate. I was at an
> FPGA infomercial the other day about two new device families coming
> out from a vendor to stay nameless and only %20 or so people raised
> their hands when asked this question. This might explain how these
> templates survived as is for such a long time.


Do you mean don't simulate the P&R'd design, or not at all?



Nial. 



Article: 141473
Subject: Re: SRAM vs Flash based FPGA one more time
From: "Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk>
Date: Thu, 25 Jun 2009 12:12:09 +0100
Links: << >>  << T >>  << A >>
> Everybody knows that from user point of view Flash based FPGA are
> better because they are nonvvolatile, tolerable to radiation, do not
> consume high current at startup and better secure intellectual
> property. On the other hand SRAM FPGA are much easier to manufacture.
>
> That's it?


No.

All I'll say is that if you're used to the sort of P&R results you get
with Altera/Xilinx tools and devices be wary of committing to a transfer
to a Flash based device without a _lot_ of experimenting first.


Nial. 



Article: 141474
Subject: Re: SRAM vs Flash based FPGA one more time
From: "Antti.Lukats@googlemail.com" <Antti.Lukats@googlemail.com>
Date: Thu, 25 Jun 2009 04:22:22 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jun 25, 2:12=A0pm, "Nial Stewart"
<nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:
> > Everybody knows that from user point of view Flash based FPGA are
> > better because they are nonvvolatile, tolerable to radiation, do not
> > consume high current at startup and better secure intellectual
> > property. On the other hand SRAM FPGA are much easier to manufacture.
>
> > That's it?
>
> No.
>
> All I'll say is that if you're used to the sort of P&R results you get
> with Altera/Xilinx tools and devices be wary of committing to a transfer
> to a Flash based device without a _lot_ of experimenting first.
>
> Nial.

well that counts for ACTEL yes!!!!

Lattice is almost like Xilinx, even has distributed RAM (only SRL16
mode is missing)
ic65L is like old Xilinx LUT4FF

but in generic yes, need run real P&R and compare actual designs
before
doing any decisions

Antti









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