Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Reposting article removed by rogue canceller. In article <3242C3DB.7EB8@xilinx.com>, Peter Alfke <peter@xilinx.com> writes: > Please, never, never use monostables, and use an analog PLL only as the > last resort. The world is going digital ! I think the analog guys still own the high frequency end. Consider doing clock recovery at 622 MHz. Another way of looking at things is that a small counter is an easy way to implement a monostable.Article: 4176
Call for Papers
1997 International Symposium on Physical Design
April 14-16, 1997
Napa Valley, California
Sponsored by the ACM SIGDA in cooperation with
IEEE Circuits and Systems Society
The International Symposium on Physical Design provides a forum to exchange
ideas and promote research on critical areas related to the physical design
of VLSI systems. All aspects of physical design, from interactions with
behavior- and logic-level synthesis, to back-end performance analysis and
verification, are within the scope of the Symposium. Target domains include
semi-custom and full-custom IC, MCM and FPGA based systems.
The Symposium is an outgrowth of the ACM/SIGDA Physical Design Workshop.
Following its five predecessors, the symposium will highlight key new
directions and leading-edge theoretical and experimental contributions to
the field. Accepted papers will be published by ACM Press in the Symposium
proceedings. Topics of interest include but are not limited to:
1. Management of design data and constraints
2. Interactions with behavior-level synthesis flows
3. Interactions with logic-level (re-)synthesis flows
4. Analysis and management of power dissipation
5. Techniques for high-performance design
6. Floorplanning and building-block assembly
7. Estimation and point-tool modeling
8. Partitioning, placement and routing
9. Special structures for clock, power, or test
10. Compaction and layout verification
11. Performance analysis and physical verification
12. Physical design for manufacturability and yield
13. Mixed-signal and system-level issues.
IMPORTANT DATES: Submission deadline: December 20, 1996
Acceptance notification: February 1, 1997
Camera-ready (6 page limit) due: March 1, 1997
SUBMISSION OF PAPERS:
Authors should submit full-length, original, unpublished papers
(maximum 20 pages double spaced) along with an abstract of at most
200 words and contact author information (name, street/mailing address,
telephone/fax, e-mail).
Electronic submission via uuencoded e-mail is encouraged (single
postscript file, formatted for 8 1/2" x 11" paper, compressed with
Unix "compress" or "gzip''). Email to:
ispd97@ece.nwu.edu
Alternatively, send ten (10) copies of the paper to:
Prof. Majid Sarrafzadeh
Technical Program Chair, ISPD-97
Dept. of ECE, Northwestern University
2145 Sheridan Road, Evanston, IL 60208 USA
Tel 847-491-7378 / Fax 847-467-4144
SYMPOSIUM INFORMATION:
To obtain information regarding the Symposium or to be added to the
Symposium mailing list, please send e-mail to ispd97@cs.virginia.edu.
Information can also be found on the ISPD-97 web page:
http://www.cs.virginia.edu/~ispd97/
SYMPOSIUM ORGANIZATION:
Steering Committee: J. Cohoon (Virginia), S. Dasgupta (Sematech),
S. M. Kang (Illinois), B. Preas (Xerox PARC)
Past Chair: G. Robins (Virginia)
General Chair: A. B. Kahng (UCLA and Cadence)
Program Chair: M. Sarrafzadeh (Northwestern)
Keynote Address: T. C. Hu (UC San Diego) and E. S. Kuh (UC Berkeley)
Special Address: R. Camposano (Synopsys)
Publicity Chair: M. J. Alexander (Washington State)
Local Arrangements Chair: J. Lillis (UC Berkeley)
Technical Program Committee: C. K. Cheng (UC San Diego),
W. W.-M. Dai (UC Santa Cruz),
D. D. Hill (Synopsys),
M. A. B. Jackson (Motorola),
J. A. G. Jess (Eindhoven),
Y.-L. Lin (Tsing Hua),
C. L. Liu (Illinois),
M. Marek-Sadowska (UC Santa Barbara),
M. Sarrafzadeh (Northwestern), Chair,
C. Sechen (Washington),
K. Takamizawa (NEC),
S. Trimberger (Xilinx),
M. Wiesel (Intel),
D. F. Wong (Texas-Austin),
E. Yoffa (IBM)
Article: 4177Ray Heasman wrote: > > Hi All, > > I was just wondering - is there an equivalent of the DSP Starter Kit for > FPGA's? I would love to fiddle with something like that. > > Cheerio, > Ray > -- > _/_/_/ ""\ ""\ ""\ ""\ """""""\ ""\ _/_/_/_/_/_/_/_/_/_/_/ > _/_/_/ """"\ """\ """\ ""\ ""\ """"\ _/ StarWriter / _/ > _/_/_/ ""\ ""\ ""\"""\""\ ""\ ""\ """\ ""\ ""\ _/ Genisys _/ > _/_/_/ _/_/_/ """"""""\ ""\ "\ ""\ ""\ ""\ ""\ """"""""\ _/ _/ > _/_/_/_/_/ ""\ ""\ ""\ ""\ ""\ """""""\ ""\ ""\ _/_/_/_/_/_/_/ > _/_/_/ Amiga - The canvas of the Gods. Ray, APS sells an inexpesive ($250.00) starter FPGA board for work with XILINX chips. You will still need access to a synthesis tool and XILINX XACT software however. You can dowmload the boards brochure at http://www.erols.com/aaps Richard SchwarzArticle: 4178
Vincent Rowley wrote: > > Hi, > > I'm looking for FPGAs design tools for PC including HDL and gate-level > simulator, synthesis tool and also FPGA development system to implement > Xilinx or Altera FPGAs. > > I will appreciate all suggestion from experimented users. > > Thanks, > > Vincent RowleyHey Vince, I have used both EXEMPLAR and SYNPLICITY synthesis tools, and found them both to be excellent products. APS sells an FPGA test board for XILINX boards which only costs $250.00. The APS X-84 FPGA board takes any XILINX 4000/5000 84 pin PLCC chip and is a PC ISA board which provides real time IO via an 8255 chip, oscillator sockets, timer circuits and status LEDs. All IO pins arew brought out via ribbon connectors. The board has power connectors to let it be used outside the PC. The board comes with download and IO software. Brochures can be downloaded at http://www.erols.com/aaps Richard SchwarzArticle: 4179
APS offers a low cost ($250.00) XILINX FPGA board -the APS-X84- which can take any 4000/5000 84 pin PLCC chip. The board has an on board timer circuit, PC decode PAL, 8255 chip for real time control and IO, a prototype area, on board prom, and a power connector to allow the boarxd to be used externally.The board comes with download and control software and VHDL examples, as well as hardware interface schematics. APS is now developing a new board -the APS-X208- which will socket any of the 4000/5000 208 pin QFP plcc chips. The board will sell for $350.00. contact aaps@erols.com or see APS LOGIC page at http://www.erols.com/aapsArticle: 4180
Peter, If the receiver did not know the bit rate quite accurately, and had to use some sort of adaptive scheme, it would have to throw away an awful lot of data before it would lock on. So, in most cases, one knows the data rate exactly. Regarding monostables, I have done lots of those in FPGAs: digitally with a counter. Nothing wrong with that, provided one avoids things like async resets (derived from decoding the outputs) which might reset some stages and not others. You could post your schematic here. A *compressed* TIFF would be only a few k - about the same length as the average "make $50,000 legally" spam :) A zipped postscript version would be even smaller. Peter.Article: 4181
testing...Article: 4182
>There's a bunch of work on translating software languages (especially C)
>to hardware.
...
>If anyone knows of any others, I'd appreciate pointers to them.
I have been working for several years on mapping a bit-oriented parallel
C variant to parallel FPGA arrays. The compiler generates VHDL and
pre-placed, pre-routed technology-specific macros. Target architectures
are
the Splash-2 (16 Xilinx 4010's) and NAPA (4 CLAy MCMs manufactured by
National Semiconductor) parallel arrays. Unfortunately, I haven't been
able to release the compiler to the general public due to proprietary
restrictions. I am presently porting the work to the SUIF toolset so
that it can be made more widely available.
References follow.
@Inproceedings{Gok95a,
author = "M. B. Gokhale and A. Marks",
title = "Automatic Synthesis of Parallel Programs Targeted
to Dynamically Reconfigurable Logic Arrays",
booktitle = "Proceedings of the 1995 International Workshop
on Field-Programmable Logic and Applications,
Oxford, England",
year = "1995",
pages = "399--408",
month = sep}
@Incollection{Gok96,
author = "M. B. Gokhale and B. Schott",
title = "A Data-Parallel Programming Model",
booktitle = "{Splash-2}: {FPGAs} in a Custom Computing Machine",
year = "1996",
publisher = "{IEEE} Press",
pages = "76--78"}
(the following will appear in SPIE's Photonics East conference this fall
in Boston)
@Inproceedings{Gok96b,
author = "M. B. Gokhale and J. Kaba and A. Marks and J. Kim",
title = "A Malleable Architecture Generator for FPGA
Computing",
booktitle = "High-Speed Computing, Digital Siganl Processing
and Filtering Using Reconfigurable Logic, Photonics East
'96",
place = "Boston",
year = "1996"}
As far as the original question on floating point, Nabeel Shirazi got
some good results implementing floating point on Xilinx. His paper on
the
subject appeared in a recent FCCM or FPL. It is probably also available
from Virginia Tech as his Master's Thesis.
Maya
Article: 4183Gray Creager wrote: > > Just a reminder, > > I maintain a well-used, but not well-publicized, listing of chipmaker > website URLs. I have recently > revamped it so that you can view just a brief listing of URLs, or a > listing URLs with a summary of the chips made by each company. > > http://www.scruznet.com/~gcreager/hello5.htm > > Use the above URL to choose between the two sites. You can print out > either listing in hardcopy format (I've made versions with colors that > are "printer friendly") and post it on your wall, or just bookmark > whichever webpage you like best. > > I've added a growing engineer humor page as well (some funny stuff there > actually). > > I am constantly updating this listing and it is the most up-to-date that > you'll find anywhere. I will soon be adding some investor links as well > (for those who invest in semi stocks). > > Use it as much as you like and tell others about it. > > -- > > Gray Creager Good stuff ! Thanks -- Frank Adlam Faculty of Electrical Engineering Port Elizabeth Technikon PO Box X6011 Port Elizabeth 6000 East Cape South Africa Tel: 2741 504 3520 Fax: 2741 531 864 E-Mail: fadlam@ml.petech.ac.zaArticle: 4184
When I argued against monostables, I had the real, unstable, noise-sensitive, #$%@& analog monostable in mind. A counter is the legitimate digital equivalent of such a time-out device, and that's what my design uses also. I will struggle with a graphic representation, because there have been 13 requests for fax so far. This newsgroup has many quiet readers, a good forum for a little app note ! Peter Alfke, Xilinx ApplicationsArticle: 4185
CALL FOR HELP !! I need a PCI card with FPGA's (hopefully Xilinix). The PCI interface could be in the FPGA'a or a custom chip. I need about 5000 gates free to do my thing. Thanks Bill Seiler Circuit City / Patapsco West 3255-4 Scott Blvd, Suite 105 Santa Clara, CA 95054 408 982 5420 Direct 408 982 5430 FAX ccwest@ix.netcom.comArticle: 4186
Peter Alfke <peter@xilinx.com> wrote: >When I argued against monostables, I had the real, unstable, >noise-sensitive, #$%@& analog monostable in mind. A counter is the >legitimate digital equivalent of such a time-out device, and that's what >my design uses also. >I will struggle with a graphic representation, because there have been >13 requests for fax so far. This newsgroup has many quiet readers, a >good forum for a little app note ! >Peter Alfke, Xilinx Applications Well, I guess I should weigh in here: I've done a manchester clock recovery scheme or two, and more analysis of the design than I care to think about. The basic point here is that whatever one is using for clock recovery (which I agree must be done), it is, essentially, a phase locked loop system. In my mind I don't see much basic difference between the digital PLL of Peter's design or a one-shot; both of them dump out the appropriate clock that one can then use to recover the incoming data. However, there is a point that I think the current owners of this thread have missed - noise performance. In a previous lifetime I was the designer of an AMPS (Advanced Moblie Phone System, now known as cellular telephone) digital receiver. AMPS uses Manchester encoded data. I had to design the clock recovery circuit for this beast. The data in an AMPS system has to survive some pretty nasty noise; in fact, the data itself is CRC-checked-and-corrected, with repeats, so that with a little luck one can recover the incoming data, even with numerous data hits, in a 0 dB signal/noise enviroment. The noise was molded as Rayleigh - i.e., the >>envelope<< of the noise had a Gaussian distribution. It was also affected by the speed of the car (dropouts while the car was moving due to cancellations of the signal by reflections). What this meant for me was that the signal would drop into the noise for anywhere between one and 15 bit periods. And it would be exceedingly more than nice if the receive clock (which, by the way, had a sequence of 255 alternating 1's and 0's to get started with) would not drift too far during this period of no signal. When one is faced with an environment like this, one pulls out the PLL design issues and stares at them. For one thing, you need to avoid any type of edge-detector for clock recovery in the incoming bit stream. This rules out one-shots. Multiplying phase detectors (XOR) are much preferred since noise hits tend not to affect them too adversely. For another, the stability (read: bandwidth) of the PLL becomes critical. I have a nasty suspicion that any PLL that can lock over a 0 to 200 MHz range (or whatever it was that Pete said) has a large bandwidth. In a noisy environment, what you want is the narrowest bandwidth that you can get away with. Further, you want the lock range to be narrow, as well; it takes a lot less time to lock to the incoming clock when the PLL is more-or-less on frequency in the first place. As I vaugely remember, the digital PLL that I implemented had both a wide bandwidth for initial lock and a narrow bandwidth thereafter, with interesting algorithms to detect when lock had been gained and lost. Admittedly, all this was done in the dark ages - it was implemented on a custom gate array, and modeled in 4000 series logic! This might also tell you that the data rate wasn't exactly high, either. So, you designers out there - watch out! The nasty analog world, complete with noise, is just beyond your I/O transformer. Ken Becker kab1@lucent.com DACS Hardware EngineeringArticle: 4187
Xiangdong:
There is actually a very large amount of information available
to the internet community regarding FPGA's at the various
vendor sites. Before I came to work here at Actel, I spent some
time researching the general subject of "Programmable Logic
Devices" for a report I did in school. I found that the World
Wide Web sites for Actel, Altera, and Xilinx alone had fairly large
amounts of information on them regarding not just their
particular products, but programmable logic devices in general.
If you want to learn more about FPGAs in general, as well as
getting an idea of what the various vendors have available,
you might try checking out their Web sites.
Actel's URL is http://www.actel.com
(I forget what Xilinx or Altera's URLs are... ;-) )
Regards,
-Scott
Scott Schlachter
Design Engineer
Actel Corporation
Janos Szamosfalvi wrote:
>
> Xiangdong Li (lxd@cpre1.ee.iastate.edu) wrote:
> : Hi, everyone:
> : I am a graduate student in ISU. I will design control circuits using
> : FPGA. I have no experience of utilizing any programmable IC. Can you
> : give me any advice? Thank you.
>
> You may want to start with simple PLD's and Abel before getting into
> FPGA's and their associated tools because the formers are a lot simpler
> to learn and use.
--
Scott Schlachter
\/ scotts@actel.com
@\ ,,
\( o)
/ \
./___-+-
_ \ /_ \_
\ /.\ /_* /\\
\ \_/ \_/
~~~\ ^
^ ~~\ ^ / \
/ \ \ / \ / \
/|\ ~~\ /|\ /|\
| ~~^~^^~^^~\__|____|___
Article: 4188Hi: I am interested in writing VHDL code for the AT&T ORCA FPGA in order to implement an FIR filter. I have the ORCA Foundry software, but do not have Exemplar.. instead we have AutoLogic. I need to know if I can generate the appropriate EDIF files using AutoLogic. Any tips? Thanks, Venkat.Article: 4189
> >I need a PCI card with FPGA's (hopefully Xilinix). >The PCI interface could be in the FPGA'a or a custom chip. >I need about 5000 gates free to do my thing. > I did a wirewrap PCI prototyping board with a PGA XC4013E and its works up to ~30MHz. You can buy the PCI protoboards from frys electronics.Article: 4190
Hi everyone, has anyone developed (or has some links to) XilinX XC5200 optimised circuit for calculation of FIFO half-full flag ? FIFO has two address pointers, read and write, for example 4 bits long. I would appreciate all the useful advice, schematic, or description. We are opened for cooperation anytime ! Vedran Maler, BSEE xylon@alf.tel.hr XYLON d.o.o. - Croatia - EuropeArticle: 4191
Hi,
I have a Data I/O MESA-I system I'd like to sell. It is new (sealed in
box, still). Here's a more exact description:
MESA-I version 1.40
Pode and probe (68 pin PLCC)
Controller board for PC (ISA card)
System software/manuals
If you are interested, make me an offer. I'm also looking to trade for a
Data I/O Chiplab 48 or similar (whatever flavor they are offering now!)
Thanks,
Eric Crabill
crabill@leland.stanford.edu
Article: 4192
Hi,
I have not used any FPGAs as such, but when I read the data sheets I
came up with the questions -
In the FPGAs with global interconnect and neighbour connects(Xilinx,
Altera Flex etc.)
1. Is it possible for any cell to connect to global connect. If yes
then
what is the delay compared to the delay in neighbour communication.
2. what is the limit on the number of cells which can read the signal
on
a global wire onto which one cell writes the output.
3. Can two cells output be connected to the global wire and the result
read as a wired-or of the two signals ?
4. If NO to Q3 is it possible for two cells to write the SAME value(=1
e.g.)
onto a global interconnect ?
I have not done any handson work with FPGAs and knowledge limited to
only datasheets and papers so pardon me if questions are too silly :)
Thanx,
-- Kiran
kiran@halcyon.usc.edu
--
-------------------------------------------------------------------------
Kiran Kumar Bondalapati(BOND) kiran@halcyon.usc.edu,
bondalap@usc.edu
Ph.D. Student, Comp.Engg.,USC. http://www-scf.usc.edu/~bondalap
Res: 935,W.30th St.,#210,LA,CA-90007, Off: EEB 232, USC,LA,CA-90089
Ph : 213-745-6885 : 213-740-9127
-------------------------------------------------------------------------
Article: 4193Now this is getting interesting. Sure you can use a digital 'one-shot' to recover the clock, but even a little noise is going to blow you out of the water. A much better solution is to use a digital PLL with an XOR type phase detector. The logic required to do this really isn't that large. I did a manchester decoder for recovery of clocking on a project related to GPS (global positioning system) a few years back that had to recover the clock in a noisy signal. The desired frequency was known within about 5%. At start up, the DPLL was set up for the nominal frequency, but with a wide bandwidth to help capture the signal. Once the signal was acquired, the bandwidth was narrowed down to a very small window using noise gating. I guess the biggest concern is the ratio of the master clock to the signal clock. The bigger the better, but that starts pushing the limits of the FPGA for high data rates. My design was for relatively low data rates and was done in a fraction of an Altera 7000 series CPLD when they were new. (been there, done that, got the T-shirt mode). -Ray Andraka, P.E. Chairman, the Andraka Consulting Group 401/884-7930 FAX 401/884-7950 mailto:randraka@ids.net http://www.ids.net/~randraka/ The Andraka Consulting Group is a digital hardware design firm specializing in high performance FPGA designs. Services include complete design, development, simulation, and integration of these devices and the surrounding circuits. We also evaluate,troubleshoot, and improve existing designs. Please call or write for a free brochure or visit our web site.Article: 4194
Vedran Maler (RIP pa konst. Zagar) wrote: > > Hi everyone, > > has anyone developed (or has some links to) XilinX XC5200 > optimised circuit for calculation of FIFO half-full flag ? > FIFO has two address pointers, read and write, for example 4 bits long. > Check out the Xilinx App notes on FIFOs for the 4000 series parts. The bit about using the LFSRs for addressing and the method of determining the flags applies equally well the the 5200 series, or any other FPGA for that matter. Basically, the LFSR makes it extra easy to obtain the next and previous addresses (just take the current one out with a shift applied). The next, current, and previous addresses for the two pointers can be compared using an identity comparator and the results used to generate the flags. The Xilinx app note should be available on the Xilinx web site at http://www.xilinx.com/. If not, check out the data book. -Ray Andraka, P.E. Chairman, the Andraka Consulting Group 401/884-7930 FAX 401/884-7950 mailto:randraka@ids.net http://www.ids.net/~randraka/ The Andraka Consulting Group is a digital hardware design firm specializing in high performance FPGA designs. Services include complete design, development, simulation, and integration of these devices and the surrounding circuits. We also evaluate,troubleshoot, and improve existing designs. Please call or write for a free brochure or visit our web site.Article: 4195
In article <3248A22F.4F69@halcyon.usc.edu> Kiran Kumar Bondalapati <kiran@halcyon.usc.edu> writes: > 1. Is it possible for any cell to connect to global connect. If yes then > what is the delay compared to the delay in neighbour communication. There is always a way to get to non-local interconnect (there is a heirarchy of interconnect, of which local and global are two of them). The issue is how much routing is used to make this connection. As the device gets routed, the resources to make these connections may get used up, so depending on design complexity (and architecture of course) the delay is variable. Neighbour connections are almost always faster but also can be influenced by existing routing. I.e. block A is to the left of block B, and the route goes from left side of A to right side of B. This could be 4 times slower than from the right side of A to the left side of B. The real entertainment happens when you have multiple loads. Non-local interconnect is usually far less sensitive to multiple loads compared to the local interconnect equivalent. > > 2. what is the limit on the number of cells which can read the signal on > a global wire onto which one cell writes the output. No limit. May effect delays though. > > 3. Can two cells output be connected to the global wire and the result > read as a wired-or of the two signals ? Yes, but only on the Xilinx XC3000 and XC4000 family products, through the tristateable buffers (in wired-and (not wired-or) mode) on the horizontal longlines. > > 4. If NO to Q3 is it possible for two cells to write the SAME value > (=1 e.g.) onto a global interconnect ? The software DRC should prohibit you from doing such a thing. > I have not done any handson work with FPGAs and knowledge limited to >only datasheets and papers so pardon me if questions are too silly :) Not too silly > >Thanx, >-- Kiran >kiran@halcyon.usc.edu Your welcome. Philip FreidinArticle: 4196
Hi,
Is it possible to define X-blox BIDIR_IO padnames in a separate file?
I am in the process of building an interface to the CAMAC
bus (yes, I know...) and would like to define 24 padnames
for one BIDIR_IO symbol. Rather than having to type
LOC[0]=P123 etc. in the symbol definition, I would like
to have a file somewhere with the names in. That way the
schematics stay 'clean'. We use Orcad for design entry, and
Xact 5.n for compilation etc.
Any hints most welcome.
Wouter
====================================================================
For direct E-Mail please respond to Wouter.Suverkropp@jet.uk
===============================================================================
The above article is the personal view of the poster and should not be
considered as an official comment from the JET Joint Undertaking
===============================================================================
Article: 4197You should be able to define these in the .cst constraints file as an alternative to assigning attributes on the schematics. -- Regards AndyG ************************************************** *Any opinions expressed herein are entirely mine,* *unless expressly stated otherwise. * *(as if anybody else would admit to them.....) * **************************************************Article: 4198
Help! I am working on a project that requires a 4800 baud serial input to an xc4000. I am using a Maxim202 to convert from RS232 to TTL...works great. I have contacted Xilinx, checked out their homepage, and data books, but I can't find any examples or ideas to help me input this data. The problem that I see is how to input the ascii data serially. I want to input the character strings, manipulate them, and them pass them out the "other side". How can I sample the serial input as not to lose bits of data? Any ideas? Thanks Curt Schibonski Electrical Engineering St. Cloud State University curtis@tigger.stcloud.msus.eduArticle: 4199
Xilinx Users Mailing List
Digest 16
9/25/96
This digest contains articles regarding synthesis and Xilinx, and specifically
view synthesis.
There's also a query on Windows NT
1. Windows NT query
2. Subject: Re: View Synthesis
====================================
From: Abdellah Touhafi
Subject: XACT on winNT
Hello,
I would like to know if it is possible to install the XACT step software
for Windows (ver. 6.0.0) unther Windows-NT. Are there some particular
things to look at or problems that can occure?
If it is possible to do the installation on Windows-NT, which version of
WIN(NT)32 should be installed?
=======================================================
From: Francois Fremaux
Organization: COMPASS Design Automation
Subject: ViewSynthesis and Xilinx
I do not know on which paltform you are designing fpga, but Compass
support Hp, Sun and Ibm software solution which includes schematic captur=
e
and Hdl synthesis to target Xilinx (xnf 4 and Xnf 5). It includes also=20
the use of F/Hmap and timing information.
For any furher informations ...
=================================================
From: Steve Wiseman
Subject: Re: ViewSynthesis and Xilinx
Hi,
after 3 yars of fighting Viewlogic / Xilinx tools, I've abandoned to Altera,
where the tools work, the silicon is cheaper and the tech support works.
This may not be the approach for you, but I can now turn round designs in a
fraction of the time, without a lot of the grief.
Altera swapped my Xilinx toolset for an Altera equivalent, so I had to
surrender the Xilinx dongle, but I felt the deal was acceptable.
I still use Modeltec for simulation, both for source level and for
post-place/route. Basically, I'm now happy, after 3 years of intense
frustration.
All the best,
Steve Wiseman,
=======================================================================
From: David Gesswein
Subject: Re: ViewSynthesis and Xilinx
>My questions:
> 1. Has anyone used ViewSynthesis?
> Likes, dislikes
>
I have used it and it seems ok. I haven't used any other package so I
can't compare. It doesn't always generate the best logic and only supports
its subset of VHDL. It can also generate incorrect logic if you give it
strange enough VHDL.
> 2. Is there a workaround to the FMAP?
> Obviously Viewlogic tech support is completely useless on that
> subject.
>
The old PRO 6.0 release we have does generate them. It had an option in
the synthesis menu for tech options with a check box for pack into CLB. That
made it use the FMAP etc. The version is viewsynthesis 5.0. Before this
release it was terrible and didn't generate FMAP etc. We have the
workview office version but I haven't had time to try it.
> 5. What size devices have you implemented in VHDL?
>
None, the project got delayed after I had started testing the implementation
of parts of the circuits.
========================================================
From: David J. Matthews
Subject: XUMA Digest 15
Yes. We have used Viewsynthesis for both gate array and CPLD jobs.
My opinion is that it is an inferior tool compared to others on the
market.
>
> 2. Is there a workaround to the FMAP?
> Obviously Viewlogic tech support is completely useless on that
> subject.
I don't know one, but there are some customer support people at Xilinx
that are specific to synthesis issues. You might want to try there.
>
> 3. Has anyone used other synthesis products:
> Synopsys FPGA Compiler,
> Synplicity Synplify,
> Xilinx Foundation (Metamore),
> Synopsys FPGA Express,
> Data IO Synario,
> Minc,
> any other?
We use the Galileo tool suite from Exemplar Logic (now a part of
Antares). It not only provides excellent support for Xilinx, but all
other families of FPGAs and some gate arrays. It is also much more
reasonably priced than the Synopsys tool - especially if you consider
the additional cost of target libraries (which can run $10K each for
gate arrays). I am currently doing a XC4013E design and found it a
good match with that architecture.
>
> 4. What do you like about the above products?
See above.
> What do you dislike?
I would like to see improvements in: gate array support, resource
sharing, and module generation.
> Limitations, bugs?
Like ALL CAE tools, one occasionally experiences a glitch. However
they are still a small company and quite responsive.
> State machine support
One can use user defined data types for state bits and then select
between binary, gray, one-hot, or random state encoding.
> On what basis did you select it. cost, functionality, availability,
> tech support, platform, other?
I used it while consulting at a client's site.
>
> 5. What size devices have you implemented in VHDL?
I have implemented FGPAs/CPLDs from Xilinx, Altera, Actel, and
Quicklogic, and small gate arrays.
>
> 6. Do you use schematic and VHDL or only VHDL?
Since we are an engineering services company, we are often forced to
use schematics if the original source is in schematic form and we are
enhancing or migrating the design to a different foundry. For new
designs, we use VHDL or Verilog exclusively.
Hope this helps.
Dave Matthews
==================================================================
From: Lasha Aponso
Subject: re: XUMA Digest 15
The following points/answers may be of some assistance:
1.We started our latest project, which includes 4x5206 & 1x5210 part
using Workview Office and viewsynthesis.
These designs were done completely in vhdl using the .fpn file for pin
allocation, global buffer allocation and other
attribute selections like fast outputs etc.
Eventhough Viewsynthesis provides a reasonably good user interface it
would be more user friendly if it did generate a single XNF file rather
than multiple files although this can be worked around using the wir2xnf
and xnfmerge/xnfprep functions from xilinx.
The biggest problem with viewsynthesis however is the relatively large
number of bugs that we uncovered compared to other products from Exemplar
and Altera. Eventhough the design passed the functional simulation (using
Speedwave, which is very good although I found it difficult/impossible to
use the text_io functions in my test beds) after synthesis, it failed. We
uncovered 4 such instances which cost our project at least 1 month (3 man
months) in terms of lost time.
2. I don't know.
3.Exemplar seems to be very good. We have only uncovered 1 bug with
this package so far, and that has been rather obscure.
The user interface could be a improved and there is at least 1
peculiarity with it when running under Win95.
We are not aware of a schematic front end that can be used with
exemplar for the PC environment although Aldec will supposedly provide
this.
4.With regard to state machine support, Aldec does offer a graphical
entry mechanism for state machines which automatically creates vhdl code. I
haven't personally used it, but it seems to be very good.
5.The 4 5206 designs varied from 60% to about 85%. The 5210 design was
about 70%.
6.All designs were done completely in vhdl.
This approach naturally facillitates porting of designs to different
products or families. For example, as a cost reduction exercise, we were
able to port these designs to altera's 10k parts, although both exemplar
and maxplusII could not handle the internal tri-states.
For future designs however, I would consider using a combination of
the two simply from a documentation stand point. Also, if aldec is used,
state machines can be documented very easily and clearly. I still think a
picture is worth some portion of a thousand words.
The best tool I've seen for this has been Mentor's System Architect.
This may be a really good way to go if you can afford it.
Lasha Aponso
======================================================================
From: Jean-Paul Smeets
Subject: Re: ViewSynthesis and Xilinx
We have just baught the ViewLogic package, so i'm starting with
ViewSynthesis, but I've use Synplify from Synplicity with the
QuickLogic FPGA's as target.
We used Verilog as Synplify supports both Verilog and VHDL. The speed
of the compiler is very high, most simple designs are a synthesized in
a couple of seconds. The quality of the output is very high. In a
large number of cases the result is the same as you would obtain by
drawing it with library parts. Only for the most timing critical
pieces, I still use hard macro's for which I disable all optimisation.
For these designs I mix schematic with HDL input, but for simple
designs I only use the HDL.
If Viewsynthesis performs as Synplify I would be very happy.
==============================================================================
XUMA is an independent mailing list for users of Xilinx devices and tools.
To subscribe send an email to xuma_request@ecla.com
Would you like to contribute an article?
Share an experience, good or bad, with xilinx parts or tools,
Describe a bug,
or need some help, have a question or just a comment:
then, post an article, send an email to xuma@ecla.com
The digests are archived at http://www.ecla.com
==============================================================================
XUMA is an independent mailing list for users of Xilinx devices and tools.
To subscribe send an email to xuma_request@ecla.com
Would you like to contribute an article?
Share an experience, good or bad, with xilinx parts or tools,
Describe a bug,
or need some help, have a question or just a comment:
then, post an article, send an email to xuma@ecla.com
The digests are archived at http://www.ecla.com
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z