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deunhido@gmail.com wrote: > Would it also be possible to use a solution as in XAPP154, "Virtex > Synthesizable Delta-Sigma DAC"? No, the frequency of the video output is *way* too high for such a DAC. e.g. For normal VGA output, you'd need to run the DAC at about 6.4GHz for 24-bit RGB. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 104576
I simulate the ddr controler generated by MIG(memory interface generator). The result of behavior simulation is correct ,but there's someting wrong after synthesis. The wave is unknown after ddr sdram initialization. I affix the captured picture in this mail. I use synplify 8.2.2 to synthesis the design, and use modelsim 6.2a to simulation it.Article: 104577
Hi Paul, besides the fact that there is an existing 6502 HDL-Clone, your project is something you can learn a lot from. As mentioned by others comparing Transistors to LUTs is not really satisfying, because you don't know what mean tricks the original designers used on their silicon. ;-) Just think a while about this: When you are going to write the decode logic for the instruction set, your synthesis tool will generate all neccessary logic for decoding exactly this instruction set and nothing more. The original designers designed a logic that decoded the instruction set , and didn't care what happened when unknown opcodes appear. This resulted in a very small decoding circuit and lots of (oficially) undocumented opcodes which do more or less meaningful things. Similar things apply for the other modules. In these times the use of real RS-FFs was very common. (made from NANDs with 2 Transistors per NAND you get a powerful FlipFlop at the cost of 4 transistors). Inside an FPGA you don't have these anymore. You may do some tricks with Preset and Reset on the common D-FF, though. But from the point of comparing the designs, that's a high price for emulating 4 transistors. Have you ever asked yourself why there are three clock signals on the 6502 (Phi0 (input), Phi1 and Phi2 (output))? Complex clock schemes like this were used to enable selected datapaths to the RS-FFs. Something similar (and even more complex) can be seen in the schematics of the H316. (look at: http://h316.hachti.de/ and contact the guy who made this homepage if you want to know more.) Out of the above reasons, and the different design techniques of today it makes not really any sense to compare the gate or transistor counts of yesterday whith LUT-counts of today. If anything, compare your design to the existing clones. But keep in mind that space eficiency and performance are both have to be considered for a real comparision. Also the grade of compatiblity. (Are the undocumented opcodes implemented? They were used somtimes to speed up (mainly) games.) So the answer to your last question is: No, not really. have a nice synthesis Eilert Paul Marciano schrieb: > Before I start let me say I'm not sure this is either an intelligent > question nor an answerable one... so please be gentle. > > I'm looking at implementing an 8-bit processor clone on an FPGA (purely > academic exercise - I know there are free IP cores available) and am > wondering how to judge the space efficiency of my design (as opposed to > speed efficiency). > > According to numbers found on the web the MOS 6502 has 9000 > transistors. > > I haven't written a single line of RTL yet, but say I implemented a > 100% functional equivalent in a 200K gate Spartan3, and it uses up 25% > of the resources... How would you judge that? > > Would you just take your own experience and say, "That's 3x too big... > try again". > > Would knowing it can be done in 9000 custom placed transistors help at > all in judging the relative efficiency of the FPGA implementation? > > > Regards, > Paul. >Article: 104578
rnbrady schrieb: > Hi folks > > I'm working with Synplify Pro (8.5.1) and I'm trying to test whether > VHDL code is synthesizable. How can I do this without selecting a > specific vendor or chip? You need to select a target technology for synthesis. Some constructs are in principal synthesisable but only if your target technology supports these technique (like RAM,...). You might of course write your own generic lib, but it might be a bit oversized for your problem. On the other side it might be very interessting for benchmark reasons, maybe a lib containing only a 2NAND would be enough *g*. bye ThomasArticle: 104579
> Hi Dan - > this is actually a 2-parter - > LatticeXP devices have DCS blocks(Dynamic Clock Selection) as part > of the global clock networks, and can be used to deactivate selected > clocks, reducing current for that clock domain. > LatticeXP, and MachXO, both also offer 'Sleep Mode', in that these > devices have built-in Flash memory, for boot-up. The SleepMode pin > deactivates the core power supply, and maintains voltage in the I/O, > which allows for very low power ( less than 100ua) standby current. > When exiting 'sleep mode' the core supply is re-activated, and the > device then auto-boots from flash on chip. > > The marketing term is "INSTANT ON" but us FAEs prefer "less than 1 > millisecond". :) > > So, yes, you can disable clocks to save some power, while the device > remains active, or you can enter 'sleep mode' and save most of the > power. Sleep Mode is available on the 'C' version of each device in > the family. The 'C' version has an onboard regulator, so you can run > the device with a single 3.3v supply. The core operates at 1.2v, > (derived from the on chip regulator in the 'C' devices), we require > 3.3v for VccAUX(used for thresholding and some housekeeping circuitry), > and the appropriate VccIO voltages. > > thanks for aking - > > Michael Thomas > Lattice SFAE - NY/NJ > Thanks, I'll explore these features. Dan.Article: 104580
Hi, I am a Master student from UNIS and I am doing project about image processing. I am wondering if anyone have a taste on loading image inside the ram or flash, what should I use?? like ethernet or PS2 or RS232. I prefer PS2, if so, do I need to use terminal in Windows. Many thanks, KYArticle: 104581
Hi,
Are you trying to simulate the synthesized model?. i am
working with ddr controller currently.i think we can help each
other.send me your problem in detail.
regards
subin
orthogonal wrote:
> I simulate the ddr controler generated by MIG(memory interface generator). The result of behavior simulation is correct ,but there's someting wrong after synthesis. The wave is unknown after ddr sdram initialization. I affix the captured picture in this mail. I use synplify 8.2.2 to synthesis the design, and use modelsim 6.2a to simulation it.
Article: 104582Does anyone have a feel for at what point rocketIO simulation becomes necessary. I have an FPGA right next to my PCIExpress card fingers so I have not simulated (I don't have the tools). But I now ideally need to move the FPGA about three inches away and I'm starting to wonder. The board is not busy at all so the routing is direct. Any thoughts? ColinArticle: 104583
John_H wrote: [snip] > I do use a controlled injection of the source into the 8 LUTs at the > bottom of my chain giving pretty strong repeatability there. I used a > method from XAPP 671 to get another half-LUT delay but I added it at the > front end. Bottom line: I have 0-7.5 LUTs worth of programmable delay > averaging just over 200 ps for each half step along with about 100 ps > per tap up the carry chain. This is an important point. I tried to create a variable delay by injecting the input into each mux element of the carry chain and controling the muxes to select the source point. In simulation I saw that changing the delay parameter (mux control) made almost no difference in the delay. I first thought something was wrong with the logic, then found that the routing delays to the various carry mux inputs very nearly matched the carry chain delay, causing the the net effect of the delay selection to be almost zero. Regards, GaborArticle: 104584
Hey! I am wondering if anyone has any experience from using lwIP on a Xilinx Virtex 2 Pro and the raw API? I am especially interested on low memory designs. Best regards, HampusArticle: 104585
I assume you mean signal integrity simulation. In my opinion if you design your tracks for proper impedance it will work just fine. We have done simulations for quite a bit longer connections, albeit it was for Aurora protocol, and they proved to be very robust (in simulation) at the speeds comparable to baseline PCIExpress. If you want to hear from professional SI folks ask this question at the SI mailing list: http://www.si-list.org/ /Mikhail "colin" <colin_toogood@yahoo.com> wrote in message news:1151664599.474116.208170@m73g2000cwd.googlegroups.com... > Does anyone have a feel for at what point rocketIO simulation becomes > necessary. > > I have an FPGA right next to my PCIExpress card fingers so I have not > simulated (I don't have the tools). But I now ideally need to move the > FPGA about three inches away and I'm starting to wonder. > > The board is not busy at all so the routing is direct. > > Any thoughts? > > Colin >Article: 104586
Is is just me that thinks the pdf documents suck? The html with the docsan search was just awesome! Pdf takes ages to load (even if I got bandwidth) and the search option is not by far as good. Please make this thread enourmously long if you miss it, so Xilinx can see that we want it back :)Article: 104587
All,
The BUFGMUX has become more complex, not less in its recent appearances
on the FPGA stage.
It is a completely synchronous machine, so it does matter if the request
to switch has sufficient setup time. If it does not, then it will not
switch until the next clock edge.
There was a small group which wanted to place an asynchronous state
machine version of the BUFGMUX in the parts (I was part of that effort).
Unfortunately, that design was not chosen to be used. It had a number
of advantages: can switch away from a failed clock, and had no
requirement for a setup time. It was also a very trivial circuit with
one control.
Alas, asynchronous circuits even when they are working perfectly in
simulation still represent a huge risk as they may not work so well in
silicon.
Austin
Peter Alfke wrote:
> Asynchronously switching between two unrelated clock frequencies is an
> interesting task. A simple solution is described as the last item in my
> "Six Easy Pieces" TechXcusives of many years ago. That circuit,
> however, has one problem: it cannot switch away from a dead clock.
> No problem when both clocks run continuously, but still a limit to the
> generality of the solution.
> Avoiding that little problem is extremely difficult, and several
> generations of BUFGMUX circuits have unfortunately destroyed the basic
> concept of asynchronous control in the laudable attempt to cover the
> Achilles heel. (Siegfrieds Lindenblatt for the Germans, same concept,
> As we know, both heroes sadly died because of their tiny problem area).
> If your clocks are always running, welcome to "Six Easy Pieces".
> Peter Alfke, Xilinx
> ===========
> Uwe Bonnes wrote:
>> Hello,
>>
>> e.g. the XC3SE Datasheet ds312 tells on page 59 in the Clock
>> Buffers/Multiplexers section:
>>
>> "As specified in DC and Switching Characteristics (Module 3), the select
>> input has a setup time requirement."
>>
>> This is probaly Tgsi on page 139.
>>
>> What can happen if the setup time is not met ("End of the world as we knew
>> it?:-)) ? Does the select signal need to be aligned to both input clock
>> edges? If it needs to be aligned to both clocks, how does one achieve
>> that. An if there are that harsh requirements on the select signal, what's
>> the whole point in the BUFGMUX?
>>
>> Or does the select signal only needs to be aligned with the active
>> edge. Simple latching the enable signal with the BUFGMUX output clock and
>> feeding the latch output to the select of BUFGMUX would do the job (beside
>> the case where the active clock is slow, where the time to the next clock
>> would be needed before the clocks would switch.
>>
>> Some clarification would be fine.
>>
>> --
>> Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
>>
>> Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
>> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
>
Article: 104588burn.sir@gmail.com wrote: > Hi all, > > I know this has been discussed on the NG before, but it seems like > every time it is discussed someone hijacks the post and we end up with > no answers. But this will be the last one. I promise ;) > > > I need two identical boards with Xilinx and Altera parts on them for > some "fun" at home. I found this page on the net > > http://www.altium.com/forms/evaluation.aspx > > Which is this board, I assume: > > http://www.altium.com/files/livedesign/Live_design_features.pdf > > > $250 for 2 boards plus the download cable sounds nice, but i wonder if > there is a catch? > > * do the boards work with chip vendor software (ISE & Quartus) flows? > what about NIOS II and EDK? > * does the programming cable work with vendor supplied programmers? > * what is that 30-day license thingy they mention on their site? is the > board bricked after 30 days?? > * someone mentioned these lack program flash, is that true? do i have > to re-program boards every time i turn them on? > * same cable for both boards? can i remove the cable while the board is > on, so i can program the other board? > * and so on... > > > to summarize, can I buy these boards instead of ordering a "Starter > kit" board from Xilinx and a "NIOS II" board from Altera? what would i > be missing? The altium boards are intended to work wit their tools. Their tools means the Altium designer, which uses the Altera and Xilinx web edition as driver. The altium designer produces a netlist or sort of that goes through the Altera/Xilinx tools. While the Altium designer has multiple cores, they are supported with compiler and source line debugger. The NIOS can be loaded, I assume, as blackbox, not as processor core. Meaning there won't be a compiler for it, nor a sourceline debugger. Having a look at both solutions may be worth the time. The cost are not necessarily that high when put in comparison to the overall project cost and the saved time. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 104589
Morten Leikvoll <mleikvol@yahoo.nospam> wrote: >Is is just me that thinks the pdf documents suck? The html with the docsan >search was just awesome! >Pdf takes ages to load (even if I got bandwidth) and the search option is >not by far as good. >Please make this thread enourmously long if you miss it, so Xilinx can see >that we want it back :) Yes, pdf makes matters more complicated. And only makes sense when layout of a whole document is critical which it in most cases is not. Other than that it's possible to rip the pdf's into html if one really wants too ;)Article: 104590
blisca wrote: > I'm still here > thanks to this newsgroup i finally built a cable III that works fine with > cpld's like xc95144xl(3,3V),i can recognize it ,readback,erase,blank check > and write. > Then i dared to connect it with a (scraped as ever) fpga,a virtex xcv200e > but the boundary scan chain does not see it at all. > > what i did was this : > > i built a level shifter for the TDO,because the cable is not expected to > work with such low levels,this 2 bjt level shifter works fine even with a 4 > mhz square wave,and i think this is faster than any signal could ever move > through the parallel port(is it true?) > > i connected just one 1.8V supply to the VCCINT of the fpga(pin A9),it is not > easy to test it (soldering wires on a bga is even worse ...)but it looks > that it should be enough for the core,correct???or i need to > > i connected in 2 points the 3.3VCCO(B12 and A13) and the ground in 3 > points(A1,J1,N12) > > i connected the jtag signals,TCK,TDI,TMS,TDO(this one to the level > amplifier) > > I connected PROGRAM fixed to 3.3V,then i tried to connect it with TMS,same > result..... > > I left M0 and M2 open,and they are high,M1 tied to ground,this for choosing > boundary scan mode > > using the debug chain utility i verified that the signals are working > > Thank you to everyone in the group that will help me or just will read this > > Diego Xilinx's Virtex-E datasheet (DS022-2 (v2.8) January 16, 2006), "Boundary Scan" section states: "The JTAG input pins (TDI, TMS, TCK) do not have a VCCO requirement and operate with either 2.5 V or 3.3 V input signalling levels. The output pin (TDO) is sourced from the VCCO in bank 2, and for proper operation of LVTTL 3.3 V levels, the bank should be supplied with 3.3 V. " So, it doesn't look like you need 1.8v JTAG circuitry. HTH -Dave PollumArticle: 104591
MM wrote: > > This is all great and I am definitely going to switch to the new design; my > only problem at the moment is that I had to modify the ll_temac core to > support RGMII mode and now I will have to figure out whether I have to do it > all again or I can reuse my modified ll_temac core... Have you done anything > to the ll_temac? > > Also, at some point in the near future I will need to have two TEMACs > connected to the same PPC... Could you tell me if this can be done in the > new MPMC2 based design? > The current design was released with a GMII interface. We do plan on releasing a design with the RGMII interface, but there are other higher priority items on the plate right now. Since this is just the interface between the LL_TEMAC core and the IOs, you should be able to just use the same code that you have right now. With MPMC2 you can have 2 or 3 or 4 LL_TEMACs in the design as the controller core now supports up to 8 ports of any type. There are hooks in the current LL_TEMAC design to support the dual mode, but we haven't released a pre-built design with this yet. Ed McGettigan -- Xilinx Inc.Article: 104592
There is another related approach, which I initially saw in some C&T display controllers. You can modulate pixel intensity across frames to generate a few more bits' worth of intensity. If you get too greedy doing this, it flickers badly. I think they called it temporal dithering. If I recall, one use was to get pseudo 24-bit color depth from LCD panels that had 18-bit digital inputs. Eric "Mark McDougall" <markm@vl.com.au> wrote in message news:44a4b398$0$12251$5a62ac22@per-qv1-newsreader-01.iinet.net.au... > deunhido@gmail.com wrote: > > > Would it also be possible to use a solution as in XAPP154, "Virtex > > Synthesizable Delta-Sigma DAC"? > > No, the frequency of the video output is *way* too high for such a DAC. > e.g. For normal VGA output, you'd need to run the DAC at about 6.4GHz > for 24-bit RGB. > > Regards, > > -- > Mark McDougall, Engineer > Virtual Logic Pty Ltd, <http://www.vl.com.au> > 21-25 King St, Rockdale, 2216 > Ph: +612-9599-3255 Fax: +612-9599-3266Article: 104593
Kolja Waschk wrote: > Would be nice if nios2-terminal provided a method to connect to the JTAG > UART from own applications through Unix or TCP sockets, or something > similar. Would be perfect if there was a public specification or source > code example how to access a JTAG UART within a SOPC over JTAG? > Kolja, It's better to post these sorts of questions to the Nios Forum: http://www.niosforum.com/. Here's a link to a post that I found doing a quick search for "jtag_uart": http://forum.niosforum.com/forum/index.php?showtopic=4022&hl=jtag_uart It may not be exactly what you're looking for, but it should be a good start and, if you have any questions, the forum is generally pretty responsive. There's also a Wiki where you can find similar information, though I'm not sure that this, particular, topic is covered there: http://nioswiki.jot.com/WikiHome Best Regards, - BrendanArticle: 104594
Hi all, I am using a Xilinx V2Pro7 FF672 board. I want to send some data values using an ethernet card.(no Power PC, only logic fabric) Can someone suggest where to start from?? Thanks, VivekArticle: 104595
http://www.fpga4fun.com/10BASE-T.html "Vivek Menon" <vivek.menon79@gmail.com> wrote in message news:1151691608.151954.26510@d30g2000cwa.googlegroups.com... > Hi all, > I am using a Xilinx V2Pro7 FF672 board. I want to send some data values > using an ethernet card.(no Power PC, only logic fabric) > Can someone suggest where to start from?? > Thanks, > Vivek > Inviato da X-Privat.Org - Registrazione gratuita http://www.x-privat.org/join.phpArticle: 104596
thank you for helping me ok,i admit that i did'nt read it ,jumping to soon to the chapter "boundary scan mode"..........but......being a newbie,and feeding the xcv200e through wires,how can i identify the bank2 VCCO?i mean where are these VCCO pins ? blisca <blisca@tiscali.it> wrote in message 44a431b7$0$5095$4fafbaef@reader2.news.tin.it... > I'm still here > thanks to this newsgroup i finally built a cable III that works fine with > cpld's like xc95144xl(3,3V),i can recognize it ,readback,erase,blank check > and write. > Then i dared to connect it with a (scraped as ever) fpga,a virtex xcv200e > but the boundary scan chain does not see it at all. > > what i did was this : > > i built a level shifter for the TDO,because the cable is not expected to > work with such low levels,this 2 bjt level shifter works fine even with a 4 > mhz square wave,and i think this is faster than any signal could ever move > through the parallel port(is it true?) > > i connected just one 1.8V supply to the VCCINT of the fpga(pin A9),it is not > easy to test it (soldering wires on a bga is even worse ...)but it looks > that it should be enough for the core,correct???or i need to > > i connected in 2 points the 3.3VCCO(B12 and A13) and the ground in 3 > points(A1,J1,N12) > > i connected the jtag signals,TCK,TDI,TMS,TDO(this one to the level > amplifier) > > I connected PROGRAM fixed to 3.3V,then i tried to connect it with TMS,same > result..... > > I left M0 and M2 open,and they are high,M1 tied to ground,this for choosing > boundary scan mode > > using the debug chain utility i verified that the signals are working > > Thank you to everyone in the group that will help me or just will read this > > Diego > > >Article: 104597
After reading the app note fine print, I see it says the delta sigma DAC is too slow for a raster display. But the S3E Starter Kit manual quotes 25.6us horizontal display time at 640x480 resolution giving 40ns per pixel. At 200MHz, you would have 80 clocks each refresh. Not good enough for 24-bit color, but maybe 8-bit with the right low-pass filter and monitor? Brian Eric Crabill wrote: > There is another related approach, which I initially saw in some C&T display > controllers. You can modulate pixel intensity across frames to generate a > few more bits' worth of intensity. If you get too greedy doing this, it > flickers badly. I think they called it temporal dithering. If I recall, > one use was to get pseudo 24-bit color depth from LCD panels that had 18-bit > digital inputs. > > Eric > > "Mark McDougall" <markm@vl.com.au> wrote in message > news:44a4b398$0$12251$5a62ac22@per-qv1-newsreader-01.iinet.net.au... > > deunhido@gmail.com wrote: > > > > > Would it also be possible to use a solution as in XAPP154, "Virtex > > > Synthesizable Delta-Sigma DAC"? > > > > No, the frequency of the video output is *way* too high for such a DAC. > > e.g. For normal VGA output, you'd need to run the DAC at about 6.4GHz > > for 24-bit RGB. > > > > Regards, > > > > -- > > Mark McDougall, Engineer > > Virtual Logic Pty Ltd, <http://www.vl.com.au> > > 21-25 King St, Rockdale, 2216 > > Ph: +612-9599-3255 Fax: +612-9599-3266Article: 104598
Sigma-Delta converters want a larger frequency ratio than you want. A 5x clock isn't enough to do a half-decent job. These converters provide 0/1 binary output at fixed clocks. In video this won't give you what you want. The suggestion on temporal filtering is good. I'd suggest looking at using a 200 MHz clock (or higher) and output the 40 MHz pixels centered in their window, altering between the n and n+1 level to dither your intensity. Rather than a 1-D Sigma-Delta converter that won't filter out well, you can rely on the eye's temporal averaging of lesser color differences to make out the minor shade differences and use some simpler analog filter on the video signal to keep from passing the "spikes" of high or low intensity colors through your cable. There are ways to push the system further than it would normally want to go but it's more like sucking a watermelon through a hose. <deunhido@gmail.com> wrote in message news:1151696056.466918.229760@h44g2000cwa.googlegroups.com... > > After reading the app note fine print, I see it says the delta sigma > DAC is too slow for a raster display. But the S3E Starter Kit manual > quotes 25.6us horizontal display time at 640x480 resolution giving 40ns > per pixel. At 200MHz, you would have 80 clocks each refresh. Not good > enough for 24-bit color, but maybe 8-bit with the right low-pass filter > and monitor? > > BrianArticle: 104599
I've defined this signals: signal accu : std_logic_vector(31 downto 0) := (others => '0'); signal data : integer range 0 to 255 := 0; Within a process, which is triggered with like this: if clk'event and clk = '0' then I try to shift the accu (I'm trying to build a CPU) : accu <= accu sll data; But ISE 8.1, with the service pack 3, says: "sll can not have such operands in this context" Even for this line it reports the same error: accu <= accu sll 1; How can I rotate the signal? I have a similiar problem with my bit-test instruction: z_flag <= accu(x_register); This produces "Wrong index type for accu.", with the same definition for x_register like for accu: signal x_register : std_logic_vector(31 downto 0) := (others => '0'); -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.de
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