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Messages from 104150

Article: 104150
Subject: Quartus 6.0 Fitter Critical Warning
From: "Manfred Balik" <manfred.balik@tuwien.ac.at>
Date: Tue, 20 Jun 2006 13:30:43 +0200
Links: << >>  << T >>  << A >>
I compiled my Design with the new version 6.0 of Quartus and get much more 
Warnings :-(
Especially a Critical Warning of the Fitter disconcerts me:

Critical Warning: Ignored Power-Up Level option on the following nodes --  
nodes are set to power up low
 Critical Warning: I/O cell 
"i2c_core:inst33|i2c_master_top:inst|i2c_master_byte_ctrl:byte_ctrl|i2c_master_bit_ctrl:bit_ctrl|c_state.idle" 
will power-up low
 Critical Warning: I/O cell "i2c_control:inst32|i2c_todo.test_i2c" will 
power-up low
 Critical Warning: I/O cell 
"i2c_control:inst32|i2c_state.write_i2c_core_reg" will power-up low
 Critical Warning: I/O cell 
"i2c_core:inst33|i2c_master_top:inst|i2c_master_byte_ctrl:byte_ctrl|\statemachine:c_state.st_idle" 
will power-up low

This I/O cells are the states of the state machines. How can the state 
machines be in the right state if the power-up level is not correct 
initialized ???
The new compilation works anyway!!!
Can someone explain it to me???

Thanks, Manfred



Article: 104151
Subject: Re: xst:What happened here?
From: "Morten Leikvoll" <mleikvol@yahoo.nospam>
Date: Tue, 20 Jun 2006 13:39:36 +0200
Links: << >>  << T >>  << A >>
I am using 8.1.03i and spartan3 (4k). Note that this happens on _synthesis_ 
when using timing constraints and the coreclk goes into a DCM generating 1x, 
2x and phase shifted by 64 (wich is in 256th of a period, not 64ns)..


"subint" <subin.82@gmail.com> wrote in message 
news:1150790874.749582.249620@g10g2000cwb.googlegroups.com...
> Which version of xilinx are you using?.
>
> Morten Leikvoll wrote:
>> Riddle:Where did that +64[ns] on source/dest clk come from??
>>
>>
>> =========================================================================
>> Timing constraint: TS_CORECLK = PERIOD TIMEGRP "NET_CORECLK" 7.800 nS 
>> HIGH
>> 3.900 nS
>> WARNING:Xst:2245 - Timing constraint is not met.
>>   Clock period: 66.690ns (frequency: 14.995MHz)
>>   Total number of paths / destination ports: 164005 / 21159
>>   Number of failed paths / ports: 75783 (46.21%) / 4474 (21.14%)
>> -------------------------------------------------------------------------
>> Slack:                  -58.890ns
>>   Source:               sym/BLKRAM (RAM)
>>   Destination:          sym/tEMPTY (FF)
>>   Data Path Delay:      5.928ns (Levels of Logic = 2)
>>   Source Clock:         DDR_CKFB1 rising 2.0X +64 at 0.693ns
>>   Destination Clock:    DDR_CKFB1 rising +64 at 1.387ns
>>
>>   Data Path: sym/BLKRAM (RAM) to sym/tEMPTY (FF)
>>                                 Gate     Net
>>     Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
>>     ----------------------------------------  ------------
>>      RAMB16_S18_S36:CLKB->DOPB3    2   2.394   0.903  sym/BLKRAM
>> (sym/parbit<3>)
>>      LUT4_L:I3->LO         1   0.551   0.126  sym/earlyempty1
>> (sym/earlyempty)
>>      LUT4:I3->O            1   0.551   0.801  sym/_n02221 (sym/_n0222)
>>      FDPE:CE                   0.602          sym/tEMPTY
>>     ----------------------------------------
>>     Total                      5.928ns (4.098ns logic, 1.830ns route)
>>                                        (69.1% logic, 30.9% route)
> 



Article: 104152
Subject: Re: JTAG - Boundary Scan s/w using Byteblaster or Parallel 4 cable
From: "Antti" <Antti.Lukats@xilant.com>
Date: 20 Jun 2006 04:45:49 -0700
Links: << >>  << T >>  << A >>
Fred schrieb:

> Does anyone know of any software, ideally freeware, which can use the above
> JTAG interfaces to exercise other JTAG interfaces on non FPGA devices?
>
> In my case I'd like to read the state of pins on an unrelated device.

why cant you just use a STAPL player??

Antti


Article: 104153
Subject: FSM State Minimization on FPGAs
From: backhus <nix@nirgends.xyz>
Date: Tue, 20 Jun 2006 14:16:33 +0200
Links: << >>  << T >>  << A >>
Hi everybody,

after a long discussion about State Minimisation with ISE

http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/35d66d3783725017/d282151c06a511ae?lnk=raot&hl=de#d282151c06a511ae

I was looking for other tools supporting this feature.
The result was disappointing.
None of the FPGA synthesis tools seams to support this feature, while 
every tool was capable of extracting FSMs and creating safe-FSMs if 
desired. But none seems to support State Minimization.


Anyone knows a good reason why?
Or have I missed a tool?  (exept design compiler, which is for ASICS)

Best regards
   Eilert

Article: 104154
Subject: Re: JTAG - Boundary Scan s/w using Byteblaster or Parallel 4 cable
From: "Fred" <fred@nowhere.com>
Date: Tue, 20 Jun 2006 13:42:53 +0100
Links: << >>  << T >>  << A >>

"Antti" <Antti.Lukats@xilant.com> wrote in message 
news:1150803949.389950.307960@b68g2000cwa.googlegroups.com...
> Fred schrieb:
>
>> Does anyone know of any software, ideally freeware, which can use the 
>> above
>> JTAG interfaces to exercise other JTAG interfaces on non FPGA devices?
>>
>> In my case I'd like to read the state of pins on an unrelated device.
>
> why cant you just use a STAPL player??
>
> Antti
>

Many thanks.

I'm not familiar with Jam code and was hoping for a more friendly interface 
for a beginner. 



Article: 104155
Subject: Re: FSM State Minimization on FPGAs
From: "Andy" <jonesandy@comcast.net>
Date: 20 Jun 2006 05:56:06 -0700
Links: << >>  << T >>  << A >>
How about: other than in academia, there's not a whole lot of use for
the capability, and identifying redundant states (or chains of states)
is not an easy task (read: extends run-time).

I'd rather they work on something that benefits more users...

Andy


backhus wrote:
> Hi everybody,
>
> after a long discussion about State Minimisation with ISE
>
> http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/35d66d3783725017/d282151c06a511ae?lnk=raot&hl=de#d282151c06a511ae
>
> I was looking for other tools supporting this feature.
> The result was disappointing.
> None of the FPGA synthesis tools seams to support this feature, while
> every tool was capable of extracting FSMs and creating safe-FSMs if
> desired. But none seems to support State Minimization.
>
>
> Anyone knows a good reason why?
> Or have I missed a tool?  (exept design compiler, which is for ASICS)
> 
> Best regards
>    Eilert


Article: 104156
Subject: Re: FSM State Minimization on FPGAs
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Tue, 20 Jun 2006 14:13:04 +0100
Links: << >>  << T >>  << A >>
On 20 Jun 2006 05:56:06 -0700, "Andy" <jonesandy@comcast.net> wrote:

>How about: other than in academia, there's not a whole lot of use for
>the capability, and identifying redundant states (or chains of states)
>is not an easy task (read: extends run-time).

I'm glad someone else said that before me :-)

After the long and intriguing thread on state minimisation, I had
been thinking about various state machines - trivial and not so
trivial - that I've designed over the past few years; and I can't
think of even one where automatic state merging would have
been helpful.  The kind of "sequence recogniser" state machine 
that was used as an example isn't very realistic, is it?
Have I missed something important?
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 104157
Subject: Re: using Impulse-C free edition for VHDL only FPGA designs.
From: "David Pellerin" <david.pellerin@comcast.net>
Date: Tue, 20 Jun 2006 06:33:38 -0700
Links: << >>  << T >>  << A >>
Hello Antti,

The size-limited version is quite restrictive and is only intended to show 
the most basic concepts of Impulse C. Most of the examples provided are not 
actually small enough to be compiled in that version, although that simple 
counter certainly should be working. (We are investigating that crash.) Some 
of the other, larger examples can be made to work by commenting out the 
#pragma PIPELINE statement.

Regarding free 30-day evaluations of the full CoDeveloper (Impulse C) 
software, we are providing these on request. Just fill out the form on 
www.ImpulseC.com/eval and provide some information. With the full version 
you should be able to do more than have some LEDs blink.

Best regards,

David Pellerin
Impulse



Article: 104158
Subject: Google FPGA Designer beta release
From: Jonathan Schneider <jon@jschneider.tenreversed>
Date: Tue, 20 Jun 2006 13:36:54 GMT
Links: << >>  << T >>  << A >>
Not really. The idea just popped into my head.

Jon

Article: 104159
Subject: Xilinx ISE 8.1i Trouble
From: "Alex" <alexmchale@gmail.com>
Date: 20 Jun 2006 06:46:28 -0700
Links: << >>  << T >>  << A >>
The VHDL source and UCF file are at the bottom of this document.

The error that I'm getting is:
NCD was not produced. All logic was removed from design.  This
   is usually due to having no input or output PAD connections in the
design and
   no nets or symbols marked as 'SAVE'.  You can either add PADs or
'SAVE'
   attributes to the design, or run 'map -u' to disable logic trimming
in the
   mapper.

I've got all my ports connected (see the UCF), and my logic seems right
(it's just a sample from the Xilinx "Quick Start") ... what am I
missing?  I can get something simple working (like, OUTPUT(0) <=
SWITCH1;  -- as the whole body), but anything more complex generates
this error.

Any help would be greatly appreciated.  Thank you!



The VHDL:
entity ffff is
	Port ( CLOCK : in STD_LOGIC;
	DIRECTION : in STD_LOGIC;
	COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end ffff;

architecture Behavioral of ffff is
	signal count_int : std_logic_vector(3 downto 0) := "0000";
begin
	process (CLOCK)
	begin
		if CLOCK='1' and CLOCK'event then
			if DIRECTION='1' then
				count_int <= count_int + 1;
			else
				count_int <= count_int - 1;
			end if;
		end if;
	end process;
	COUNT_OUT <= count_int;
end Behavioral;



The UCF:
NET "CLOCK"  LOC = "C9"  |  IOSTANDARD = LVCMOS33;
NET "CLOCK"  PERIOD = 20.0ns HIGH 40%;

NET "COUNT_OUT<0>"  LOC = "F12"  ;
NET "COUNT_OUT<1>"  LOC = "E12"  ;
NET "COUNT_OUT<2>"  LOC = "E11"  ;
NET "COUNT_OUT<3>"  LOC = "F11"  ; 
NET "DIRECTION"  LOC = "L13"  ;


Article: 104160
Subject: Re: JTAG - Boundary Scan s/w using Byteblaster or Parallel 4 cable
From: "Fred" <fred@nowhere.com>
Date: Tue, 20 Jun 2006 14:46:48 +0100
Links: << >>  << T >>  << A >>

"Fred" <fred@nowhere.com> wrote in message 
news:4497ed4b$0$1232$db0fefd9@news.zen.co.uk...
>
> "Antti" <Antti.Lukats@xilant.com> wrote in message 
> news:1150803949.389950.307960@b68g2000cwa.googlegroups.com...
>> Fred schrieb:
>>
>>> Does anyone know of any software, ideally freeware, which can use the 
>>> above
>>> JTAG interfaces to exercise other JTAG interfaces on non FPGA devices?
>>>
>>> In my case I'd like to read the state of pins on an unrelated device.
>>
>> why cant you just use a STAPL player??
>>
>> Antti
>
> Many thanks.
>
> I'm not familiar with Jam code and was hoping for a more friendly 
> interface for a beginner.

Jam code etc seems to be dominated by Altera.  What I hoped would be a 
useful website http://www.jamisp.com/ jumps straight to Altera.

There also doesn't seem to be much information on the Jam language :-(



Article: 104161
Subject: Need help reg Power Estimation using PowerPlay
From: iluvmylife@gmail.com
Date: 20 Jun 2006 07:02:18 -0700
Links: << >>  << T >>  << A >>
Hi,

My problem is as follows:
I am trying to estimate the dynamic power of my Nios II based system
using the PowerPlay Power Analyzer tool. For this I simulated the
entire system using ModelSim, following instructions similar to that
given in this tutorial: http://www.altera.com/literature/an/an351.pdf
...

Before simulating the design, I create a vcd file using 'vcd file'
command and add all the required signals to be included in the vcd file
using the 'vcd add' command and then run the simulation. The VCD files
is successfully generated and I have verified that it contains the
value changes of all the signals that I have specified.

Now I run the PowerPlay tool, giving this VCD file as the input. But,
the toggle rates of only a few signals (~2%) are read from the
simulation (VCD file) and the remaining (~98% of the signals) use
default 12.5% toogle rate assignment. The only signals whose toggle
rates are taken from the simulation (i.e the VCD file) are the input
and output signals to the Nios II processor (eg. clk, reset, signals to
the sdram), although the Value changes of all the other internal
signals are also present in the VCD file generated by ModelSim.

Why is this so? Why is PowerPlay not taking the toggle rates of other
signals (internal signals) from the VCD file? As a result I get a 'Low'
confidenc metric level in the Power Analysis Report and it says that
the user has not provided sufficient toggle rate data. The report says:

Total No. of signals with toggle rate from simulation = 95
Total No. of signals with zero toggle rate from simulation = 39
Total No. of signals with toggle rate from default assignment  = 4555

If you have any idea on how to make PowerPlay take all the toggle rates
from the VCD file, please help me.

Thanking you in advance,
Sai Prashanth


Article: 104162
Subject: Instrumentation Technologies
From: "Streetcat" <clairm@gmail.com>
Date: 20 Jun 2006 07:09:12 -0700
Links: << >>  << T >>  << A >>
Hi there,

On the look out for an FPGA system, have had a look on the web, came
across a company called Instrumentation Technologies, anyone had any
experience with them? any idea how much there Libera card costs?


Thanks in advance!


Article: 104163
Subject: Re: FSM State Minimization on FPGAs
From: Phil Hays <Spampostmaster@comcast.net>
Date: Tue, 20 Jun 2006 07:30:09 -0700
Links: << >>  << T >>  << A >>
backhus <nix@nirgends.xyz> wrote:

>after a long discussion about State Minimisation with ISE
>I was looking for other tools supporting this feature.
>The result was disappointing.
>None of the FPGA synthesis tools seams to support this feature, while 
>every tool was capable of extracting FSMs and creating safe-FSMs if 
>desired. But none seems to support State Minimization.
>Anyone knows a good reason why?

About the only times I've had a state machine that could been
minimized I would have been looking for the switch to turn off state
minimization, if that was implemented.

Suppose I had a statemachine that needed to run at close to full FPGA
speed.  This implies that the design needs to have a single level of
logic between registers.  With N-input LUTs, then a given state can
have only N (input states + conditions).  By splitting states, then a
faster clock speed and functional identical state machine can be
produced.

As an example, suppose I was designing for 4-input LUTs, and I had two
input states, and two condition bits for a state.  One-hot is assumed.
The input logic to state3 would be:

state3 :: (state1, state2, (state3, c1, c2))

This is five inputs, which would require two levels of logic with
4-LUTs.  I could improve speed by splitting state 3 into two states,
state3a and state3b:

state3a :: (state1, (state3a, c1, c2))
state3b :: (state2, (state3b, c1, c2))

Any output equations and next state equations would have state3
replaced with (state3a or state3b).  A "state minimization feature"
would collapse these states back into state3, making the FPGA run
slower.

There are some similar state duplication tactics that can be done with
binary coded statemachines.  Adding states can be useful with slower
and more complex machines as well, by replacing a state that is too
complex to work at the target clock speed with two states that are
less complex, and (hopefully) will work at the target clock speed.


--
Phil Hays (Xilinx, but speaking for himself)


Article: 104164
Subject: Re: JTAG - Boundary Scan s/w using Byteblaster or Parallel 4 cable
From: "Antti" <Antti.Lukats@xilant.com>
Date: 20 Jun 2006 08:12:08 -0700
Links: << >>  << T >>  << A >>

Fred schrieb:

> "Fred" <fred@nowhere.com> wrote in message
> news:4497ed4b$0$1232$db0fefd9@news.zen.co.uk...
> >
> > "Antti" <Antti.Lukats@xilant.com> wrote in message
> > news:1150803949.389950.307960@b68g2000cwa.googlegroups.com...
> >> Fred schrieb:
> >>
> >>> Does anyone know of any software, ideally freeware, which can use the
> >>> above
> >>> JTAG interfaces to exercise other JTAG interfaces on non FPGA devices?
> >>>
> >>> In my case I'd like to read the state of pins on an unrelated device.
> >>
> >> why cant you just use a STAPL player??
> >>
> >> Antti
> >
> > Many thanks.
> >
> > I'm not familiar with Jam code and was hoping for a more friendly
> > interface for a beginner.
>
> Jam code etc seems to be dominated by Altera.  What I hoped would be a
> useful website http://www.jamisp.com/ jumps straight to Altera.
>
> There also doesn't seem to be much information on the Jam language :-(

STAPL=JAM

Antti


Article: 104165
Subject: For Broaddown2 Owners
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Tue, 20 Jun 2006 16:15:19 +0100
Links: << >>  << T >>  << A >>
For all that have asked the first details of the Virtex-4 Swinyard1 module 
are now posted on the website at 
http://www.enterpoint.co.uk/moelbryn/swinyard1.html.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development 
Board.
http://www.enterpoint.co.uk



Article: 104166
Subject: Re: using Impulse-C free edition for VHDL only FPGA designs.
From: "Antti" <Antti.Lukats@xilant.com>
Date: 20 Jun 2006 08:16:15 -0700
Links: << >>  << T >>  << A >>
David Pellerin schrieb:

> Hello Antti,
>
> The size-limited version is quite restrictive and is only intended to show
> the most basic concepts of Impulse C. Most of the examples provided are not
> actually small enough to be compiled in that version, although that simple
> counter certainly should be working. (We are investigating that crash.) Some
> of the other, larger examples can be made to work by commenting out the
> #pragma PIPELINE statement.
>
> Regarding free 30-day evaluations of the full CoDeveloper (Impulse C)
> software, we are providing these on request. Just fill out the form on
> www.ImpulseC.com/eval and provide some information. With the full version
> you should be able to do more than have some LEDs blink.
>
> Best regards,
>
> David Pellerin
> Impulse

Hi yes, sure the eval version is way more useful, I merely pointed out
that if
someone wants to get hands one to test out some C-FPGA design without
the use of EDK and the hardware streams, etc.. then it is doable with
the
free limited version. I think even the free version is sufficient for
some simple
things :)

Antti
PS dont wonder that I found the crash-bug so quickly, or actually it
wasnt
so quick, mostly all commercial software crashes withing a few minutes
(after I start it first time) - ImpulseC Codeveloper does work
amazingly well
(in all cases that do not invoke that crash)


Article: 104167
Subject: Re: Xilinx ISE 8.1i Trouble
From: girmann@gmail.com
Date: 20 Jun 2006 08:40:32 -0700
Links: << >>  << T >>  << A >>
Try

 NET "COUNT_OUT[0]"  LOC = "F12"  ;
 NET "COUNT_OUT[1]"  LOC = "E12"  ;
 NET "COUNT_OUT[2]"  LOC = "E11"  ;
 NET "COUNT_OUT[3]"  LOC = "F11"  ;

-girmann

Alex wrote:
> The VHDL source and UCF file are at the bottom of this document.
>
> The error that I'm getting is:
> NCD was not produced. All logic was removed from design.  This
>    is usually due to having no input or output PAD connections in the
> design and
>    no nets or symbols marked as 'SAVE'.  You can either add PADs or
> 'SAVE'
>    attributes to the design, or run 'map -u' to disable logic trimming
> in the
>    mapper.
>
> I've got all my ports connected (see the UCF), and my logic seems right
> (it's just a sample from the Xilinx "Quick Start") ... what am I
> missing?  I can get something simple working (like, OUTPUT(0) <=
> SWITCH1;  -- as the whole body), but anything more complex generates
> this error.
>
> Any help would be greatly appreciated.  Thank you!
>
>
>
> The VHDL:
> entity ffff is
> 	Port ( CLOCK : in STD_LOGIC;
> 	DIRECTION : in STD_LOGIC;
> 	COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
> end ffff;
>
> architecture Behavioral of ffff is
> 	signal count_int : std_logic_vector(3 downto 0) := "0000";
> begin
> 	process (CLOCK)
> 	begin
> 		if CLOCK='1' and CLOCK'event then
> 			if DIRECTION='1' then
> 				count_int <= count_int + 1;
> 			else
> 				count_int <= count_int - 1;
> 			end if;
> 		end if;
> 	end process;
> 	COUNT_OUT <= count_int;
> end Behavioral;
>
>
>
> The UCF:
> NET "CLOCK"  LOC = "C9"  |  IOSTANDARD = LVCMOS33;
> NET "CLOCK"  PERIOD = 20.0ns HIGH 40%;
>
> NET "COUNT_OUT<0>"  LOC = "F12"  ;
> NET "COUNT_OUT<1>"  LOC = "E12"  ;
> NET "COUNT_OUT<2>"  LOC = "E11"  ;
> NET "COUNT_OUT<3>"  LOC = "F11"  ; 
> NET "DIRECTION"  LOC = "L13"  ;


Article: 104168
Subject: Re: Xilinx ISE 8.1i Trouble
From: "Alex" <alexmchale@gmail.com>
Date: 20 Jun 2006 08:50:15 -0700
Links: << >>  << T >>  << A >>
Same exact error, I'm afraid.  Thanks for the try, though.

girmann@gmail.com wrote:
> Try
>
>  NET "COUNT_OUT[0]"  LOC = "F12"  ;
>  NET "COUNT_OUT[1]"  LOC = "E12"  ;
>  NET "COUNT_OUT[2]"  LOC = "E11"  ;
>  NET "COUNT_OUT[3]"  LOC = "F11"  ;
>
> -girmann
>
> Alex wrote:
> > The VHDL source and UCF file are at the bottom of this document.
> >
> > The error that I'm getting is:
> > NCD was not produced. All logic was removed from design.  This
> >    is usually due to having no input or output PAD connections in the
> > design and
> >    no nets or symbols marked as 'SAVE'.  You can either add PADs or
> > 'SAVE'
> >    attributes to the design, or run 'map -u' to disable logic trimming
> > in the
> >    mapper.
> >
> > I've got all my ports connected (see the UCF), and my logic seems right
> > (it's just a sample from the Xilinx "Quick Start") ... what am I
> > missing?  I can get something simple working (like, OUTPUT(0) <=
> > SWITCH1;  -- as the whole body), but anything more complex generates
> > this error.
> >
> > Any help would be greatly appreciated.  Thank you!
> >
> >
> >
> > The VHDL:
> > entity ffff is
> > 	Port ( CLOCK : in STD_LOGIC;
> > 	DIRECTION : in STD_LOGIC;
> > 	COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
> > end ffff;
> >
> > architecture Behavioral of ffff is
> > 	signal count_int : std_logic_vector(3 downto 0) := "0000";
> > begin
> > 	process (CLOCK)
> > 	begin
> > 		if CLOCK='1' and CLOCK'event then
> > 			if DIRECTION='1' then
> > 				count_int <= count_int + 1;
> > 			else
> > 				count_int <= count_int - 1;
> > 			end if;
> > 		end if;
> > 	end process;
> > 	COUNT_OUT <= count_int;
> > end Behavioral;
> >
> >
> >
> > The UCF:
> > NET "CLOCK"  LOC = "C9"  |  IOSTANDARD = LVCMOS33;
> > NET "CLOCK"  PERIOD = 20.0ns HIGH 40%;
> >
> > NET "COUNT_OUT<0>"  LOC = "F12"  ;
> > NET "COUNT_OUT<1>"  LOC = "E12"  ;
> > NET "COUNT_OUT<2>"  LOC = "E11"  ;
> > NET "COUNT_OUT<3>"  LOC = "F11"  ;
> > NET "DIRECTION"  LOC = "L13"  ;


Article: 104169
Subject: keys to the Kingdom
From: Austin Lesea <austin@xilinx.com>
Date: Tue, 20 Jun 2006 08:56:42 -0700
Links: << >>  << T >>  << A >>
Annoyed Crypto Folks,

The latest announcement of "security" is just more than a little annoying:

http://biz.yahoo.com/prnews/060619/sfm036.html?.v=56

In the FIPS 140-2 Standard:

"4.7.6 Key Zeroization

A cryptographic module shall provide methods to zeroize all plaintext
secret and private cryptographic keys and CSPs within the module.
Zeroization of encrypted cryptographic keys and CSPs or keys otherwise
physically or logically protected within an additional embedded
validated module (meeting the requirements of this standard) is not
required.

Documentation shall specify the key zeroization methods employed by a
cryptographic module."

Efuse keys can be read easily by inspection:

http://ieeexplore.ieee.org/iel5/9994/32106/01493126.pdf?tp=&arnumber=1493126&isnumber=32106
(IEEE library user name and password required)

Not that there is anything wrong with a low cost, simple, and useful
security method (look at how many cheap locks get sold that are easily
picked by the average pre-teen).  But to imply that this is somehow NIST
approved is a complete joke!

In fact, use of poly efuses are great (now that the foundries have them
as a standard feature).

Just don't go advertising them to be more than they really are:  a
convenient way to make it cost at least $5,000 to find the key.

Austin

Article: 104170
Subject: Re: Xilinx ISE 8.1i Trouble
From: "Ben Jones" <ben.jones@xilinx.com>
Date: Tue, 20 Jun 2006 17:11:28 +0100
Links: << >>  << T >>  << A >>

"Alex" <alexmchale@gmail.com> wrote in message
news:1150811188.026823.5240@r2g2000cwb.googlegroups.com...

> The error that I'm getting is:
> NCD was not produced. All logic was removed from design.  This
>    is usually due to having no input or output PAD connections in the
> design and
>    no nets or symbols marked as 'SAVE'.

What are you using to synthesize your design?

If you are using XST (i.e. synthesis within ISE), make sure the "add I/O
pads" option is checked in the GUI or passed on the command line. Otherwise
the netlist created from synthesis will have no I/Os, and the mapper will
throw away your design because it cannot affect the outside world...

Cheers,

    -Ben-



Article: 104171
Subject: Re: Xilinx ISE 8.1i Trouble
From: Duane Clark <junkmail@junkmail.com>
Date: Tue, 20 Jun 2006 16:26:54 GMT
Links: << >>  << T >>  << A >>
Alex wrote:
> The VHDL source and UCF file are at the bottom of this document.
> 
> The error that I'm getting is:
> NCD was not produced. All logic was removed from design.  This
>    is usually due to having no input or output PAD connections in the
> design and
>    no nets or symbols marked as 'SAVE'.  You can either add PADs or
> 'SAVE'
>    attributes to the design, or run 'map -u' to disable logic trimming
> in the
>    mapper.
> 

Might I suggest you use use the numeric_std library? That works fine for 
me. From the par report file:

Device Utilization Summary:

    Number of BUFGMUXs                  1 out of 16      6%
    Number of External IOBs             6 out of 140     4%
       Number of LOCed IOBs             6 out of 6     100%

    Number of SLICEs                    3 out of 1408    1%

Using this file:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ffff is
	Port ( CLOCK : in STD_LOGIC;
	DIRECTION : in STD_LOGIC;
	COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end ffff;

architecture Behavioral of ffff is
	signal count_int : unsigned(3 downto 0) := "0000";
begin
	process (CLOCK)
	begin
		if CLOCK='1' and CLOCK'event then
			if DIRECTION='1' then
				count_int <= count_int + 1;
			else
				count_int <= count_int - 1;
			end if;
		end if;
	end process;
	COUNT_OUT <= std_logic_vector(count_int);
end Behavioral;

Article: 104172
Subject: Re: Xilinx ISE 8.1i Trouble
From: "Alex" <alexmchale@gmail.com>
Date: 20 Jun 2006 09:35:52 -0700
Links: << >>  << T >>  << A >>
Yes, I am indeed using XST.  Where is this "add I/O pads" option within
ISE?

Thanks!

Alex McHale


Ben Jones wrote:
> "Alex" <alexmchale@gmail.com> wrote in message
> news:1150811188.026823.5240@r2g2000cwb.googlegroups.com...
>
> > The error that I'm getting is:
> > NCD was not produced. All logic was removed from design.  This
> >    is usually due to having no input or output PAD connections in the
> > design and
> >    no nets or symbols marked as 'SAVE'.
>
> What are you using to synthesize your design?
>
> If you are using XST (i.e. synthesis within ISE), make sure the "add I/O
> pads" option is checked in the GUI or passed on the command line. Otherwise
> the netlist created from synthesis will have no I/Os, and the mapper will
> throw away your design because it cannot affect the outside world...
> 
> Cheers,
> 
>     -Ben-


Article: 104173
Subject: Re: Google FPGA Designer beta release
From: "R! Tafas Jr" <rtafas@gmail.com>
Date: 20 Jun 2006 09:36:05 -0700
Links: << >>  << T >>  << A >>
why not Opencores? And they have a bus spec to conect cores!

Jonathan Schneider escreveu:

> Not really. The idea just popped into my head.
> 
> Jon


Article: 104174
Subject: Re: Quartus 6.0 Fitter Critical Warning
From: "KJ" <Kevin.Jennings@Unisys.com>
Date: 20 Jun 2006 09:54:25 -0700
Links: << >>  << T >>  << A >>

Manfred Balik wrote:

> This I/O cells are the states of the state machines. How can the state
> machines be in the right state if the power-up level is not correct
> initialized ???

If you've properly coded your state machine, then they should be put
into the proper state by some form of reset signal that occurs, not as
a result of some 'power-up' default.

> The new compilation works anyway!!!

Either your state machine is coded properly but there is an extraneous
'initial' value (see code snip below) or you're just getting
lucky....for now.  If it's the 'lucky' option, then your luck will run
out on you, investigate the code.
> Can someone explain it to me???
>
Possible source of the problem (assuming VHDL source)

-- In your signal declarations (or variables depending on your coding
style) is something like this...

type t_The_States is (Idle, Do_Something, Do_Something_Else, Done);
signal Current_State:   t_The_States := Idle;  <--- This would be an
initialization that would get ignored if you have it.

Further down into the code you probably have something like this...

if (Reset = '1') then    <- Better have this and reset better occur
after power up
   Current_State <= Idle;   <- If you want to get into this state after
power up
else
   case Current_State is
    .....bla, bla, bla
   end case;
end if;

KJ




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