Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
I'm going to try again... Check out our QuickUSB module at www.quickusb.com. Its designed for applications just like you're describing. It gives you a high-speed parallel port input into your PC without having to learn USB. Regards, Blake "Ernest Jamro" <jamro@agh.edu.pl> wrote in message news:3E39483A.3090702@agh.edu.pl... > I have done a similar project and it does not work on > every computer. > > 1. EPP signals are often not TTL compatible on some computers in EPP mode, > 2. PCs motherboard chip set (or PP cable) does not work correctly on > some PCs (e.g. when the transferred data change from 0x00 to 0xFF > the EPP data_stobeN goes high even when waitN signal is still low) > 3. some PC does not support EPP mode at all. > 4. Transfer depends strongly on a PC you've got. > > You need not bother about the DMA - use a standard memory transfer > unless your PC must do some other critical calculation. > > Good luck anyway > > Ernest Jamro > > Bob Fischer wrote: > > I will be testing an FPGA design that is intended to drive a PC for > > initial checkout and later to an embedded computer using parallel > > port. I selected the EPP protocol as it looks like it can support > > what I need to do. > > > > The FPGA will output 10 bytes of data to the PC each cycle of > > operation. The data consists of five 14 bit values output in two > > bytes each. The FPGA will be performing about 40,000 cycles per > > second. Think of each cycle as a 25 us frame. Data collection (about > > 4 us), processing (about 7-8 us) occurs for the first 11-12 us of each > > frame. When the data is ready the parallel port Interrupt line is > > asserted. > > > > The burst rate during the available 13 us data output portion is > > around 770 Khz. The times have already been verified in the > > simulations. For the simulation I used an 800 ns byte cycle. The > > testbench emulates the PC by responding to the Interrupt, invoking the > > byte cycle timing as expected from the PC by cycling the Data Strobe > > line (400 ns low then 400 ns high for each byte). The FPGA responds > > with Waits and presentation of data bytes at the time defined for the > > EPP port. I used the timing found in web site > > www.beyondlogic.org/epp/epp.htm > > > > The output of the FPGA is configured for TTL levels, slow transitions. > > I intend to pipe the FPGA directly to the DB connector and through a > > 3 ft parallel cable to the PC parallel port. > > > > In the PC we will DMA the data to memory and accumulate it for several > > seconds. A display program will access that memory and generate > > graphs, etc for visual analysis of the performance and results. > > > > Does this approach to PC interfaceing sound feasible? Has anyone out > > there any prior experience they would like to share? Some Do's and > > Don'ts? > > > > Bob Fischer > > FPGA independent designer >Article: 52351
The web site is at www.quickusb.com. Blake "Nobody" <nobody@nowhere.com> wrote in message news:CGI0a.3289$ta2.1025@nwrddc01.gnilink.net... > Terry, > > Check out our QuickUSB module and kits. It is designed to do exactly what > you're looking for. > > Thanks, > Blake > > "Theron Hicks (Terry)" <hicksthe@egr.msu.edu> wrote in message > news:3E431E87.905ECF6F@egr.msu.edu... > > Hi, > > I am looking at design upgrade of an existing instrumentation > > project. Currently the design talks over a high speed bus to a rather > > expensive (~$1600 US) parrallel digital input board. The data rate > > would be on the order of 50M bits per second not including any > > overhead. I do not think I want to go to an all FPGA based solution. > > Currently the FPGA in the system is the smallest Spartan2e series > > device. By the way, quantities are very small, on the order of less > > than 50 pieces per year. > > > > So here are my questions... > > > > 1. Does anyone happen to know what the USB2 or firewire is rated for > > in terms of the longest cable length? I had thought USB2 was limited to > > about 2 meters but I have seen USB cables about 5 meters long recently. > > A longer length interconnect would appear to be desireable. I know that > > ethernet is good for several hundred meters. That would be far beyond > > my needs. > > > > 2. Has anyone had any experience with either USB2 or 100mB or > > firewire as an interconnect to an FPGA based design? > > > > 3. Do you happen to have any recommendations as to a possible > > off-the-shelf solution (either a small board or a 1 or two chip > > solution, ideally something with a demo board available)? > > > > Thanks, > > Theron Hicks > > > >Article: 52352
Hello, is there a schematic available for Alteras Byteblaster II. In contrast to Byteblaster and Byteblaster MV the datasheet of Byteblaster II does not show any schematic of the circuit. Thanks, ThorstenArticle: 52353
Hello, Can someone tell me which company sells reconfigurable multicontext FPGA devices? Thanks in advance, Regards, RadoArticle: 52354
Hello all, I generate a blockram by using the Xilinx core generator. I edited a coe file for the memory initalization values and works fine, if I want to change the values of the blockram can I change the values directly in the edf file or I must generate the core again but with other coe file? Thanks in advance. Best Regards, HarrisArticle: 52355
Terry, You can use EDK ( embedded dev. kit) and spartan2e (xc2s400e or xc2s600e) and build a small system around MicroBlaze with Ethernet 10/100 MAC and use BRAM for the SW (tcp/ip stack) I've used this "receipe" and it works fine. Aurash "Theron Hicks (Terry)" wrote: > > Hi, > I am looking at design upgrade of an existing instrumentation > project. Currently the design talks over a high speed bus to a rather > expensive (~$1600 US) parrallel digital input board. The data rate > would be on the order of 50M bits per second not including any > overhead. I do not think I want to go to an all FPGA based solution. > Currently the FPGA in the system is the smallest Spartan2e series > device. By the way, quantities are very small, on the order of less > than 50 pieces per year. > > So here are my questions... > > 1. Does anyone happen to know what the USB2 or firewire is rated for > in terms of the longest cable length? I had thought USB2 was limited to > about 2 meters but I have seen USB cables about 5 meters long recently. > A longer length interconnect would appear to be desireable. I know that > ethernet is good for several hundred meters. That would be far beyond > my needs. > > 2. Has anyone had any experience with either USB2 or 100mB or > firewire as an interconnect to an FPGA based design? > > 3. Do you happen to have any recommendations as to a possible > off-the-shelf solution (either a small board or a 1 or two chip > solution, ideally something with a demo board available)? > > Thanks, > Theron Hicks -- __ / /\/\ Aurelian Lazarut \ \ / System Verification Engineer / / \ Xilinx Ireland \_\/\/ phone: 353 01 4032639 fax: 353 01 4640324Article: 52356
Harris, Yes it's possible to change in the edif file but depending on your bram "geometry" it's very likely to be not "very obvious" what (and how) you should change. By the other hand your edif it will not match the XCO + COE file and if you regenerate the core you'll lose the changes. My recommendation is to edit the *.coe and regenerate. PS. if you want to change the content of the BRAM on the fly inside your design (for testing purpose) you can take advantage of the second port (if is available) and put together a small design with PicoBlaze + uart and "refresh" the blockram content. Aurash Alphaboran wrote: > > Hello all, > > I generate a blockram by using the Xilinx core generator. I edited a coe > file for the memory initalization values and works fine, if I want to change > the values of the blockram can I change the values directly in the edf file > or I must generate the core again but with other coe file? > > Thanks in advance. > > Best Regards, > Harris -- __ / /\/\ Aurelian Lazarut \ \ / System Verification Engineer / / \ Xilinx Ireland \_\/\/ phone: 353 01 4032639 fax: 353 01 4640324Article: 52357
In Virtex-II Pro datasheet stated that PowerPC processor has 16 KByte of instruction and 16 KByte of data cache onboard. For my application that amount of memory is more than enough (processor speed is far more valuable). Is this possible to store both the program and data tables solely in those caches without any use of Virtex-II Pro SelectRAM or external RAM? It assumes that initial content for both caches will be stored in main Virtex-II Pro configuration RAM and will be loaded at startup. Valeri Serebrianski.Article: 52358
> Hi > I'm trying to implement a NIOS CPU on a ACEX1K100-1 from Altera. > The only problem that I have is the fmax that I can use; I need 33MHz while > Quartus II is able to use a fmax of 25Mhz. > ACEX1K family should be able to support PCI interface ( 33Mhz and 64Mhz) so > I don't understand while the fmax is 25Mhz. > Can somebody help me?. > Thanks You're comparing two completely different things. The PCI interfaces are probably highly optimised for speed. The NIOS is a prarameterisable module (I presume) that the tools will do the best they can with. What clock constraints are you using? I've a poster "Nios 2.0 New Features" which lists the 32 bit reference design as running at 37MHz and the 16 bit reference at 43 MHz. Have you tried the reference designs for comparison? Have you added much user logic/any custom instructions to your design? Nial. ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 52359
I've been having some problems with Quartus II 2.2 and I'd be interested to hear if anyone else has had similar experiences: 1) For a while I have been successfully using the Quartus II simulator but recently a strange phenomenon has stopped me. I define the input waveforms in the .vwf file and run the simulator. All appears to run OK but the output waveforms in the Simulator messages window do not appear correctly. For example, the input clock signal just appears to be low all the time. Scrolling in time is only possible by dragging the marker along - using the left or right arrows doesn't work. Changes in the input waveforms do occur when these random positions are visited. It's as if I'm zoomed in to a tiny resolution and can only see a small area of the waveforms. Trying to zoom out has no effect. 2) Quartus II hangs up now and again (Win XP professional, P4 1.8GHz, 384MB) sometimes when the compiler is running, sometimes during simulation. Re-installing from the CD as changed nothing. It would be neat to blame all this on file corruption but I don't believe it is. Any suggestions anyone? Thanks. Rog.Article: 52360
Hi, I would like to do Partial Reconfiguration on a Virtex-E. I need a bus macro for the communication between the reconfigurable modules. Xilinx Application note XAPP290 says, that Xilinx provides these macros. Unfortunately the example of this application note only contains bus macros for Virtex and Virtex-II FPGAs. These don't work for me. Can anybody tell me, where I can find the bus macro for Virtex-E? Thanks, RainerArticle: 52361
Hi there, I am working on a realization of a Carry-Save-Adder for a Xilinx Virtex device. Up to now i was able to implement it using 2 LCs per Bit. However I read in the data book that arithmetic logic allows a 1-bit full adder per LC. This works fine for a Ripple-Carry-Adder. Is there any way to utilize the carry logic for the Carry-Save-Adder, too ? Best wishes, Lars. -- GnuPG public key: http://www.ida.ing.tu-bs.de/~larsu/larsu_ida_ing_tu-bs_de.keyArticle: 52362
In comp.arch.fpga Garry Allen <garrya@ihug.com.au> wrote: : input data is 9 bit samples at 33.325714 MHz (or possibly 31.104 MHz) : 1 dB ripple allowed in pass band (0 - 7MHz), minimum of 65 dB down in : the stop band. (8 MHz) I agree with the estimate of about 70 taps. My favorite filter synthesis tool (proprietory) gave the following figures: Sampling frequency = 33.325714 MHz Number of taps = 64 Pass-band ripple (0 - 7 MHz) = 0.986 dB Stop-band attenuation (>8 MHz) = -65.2 dB This is with a non-quantised filter. As another post correctly remarked, 9-bits is nothing like enough for a 65 dB dynamic range (that would need about 11 bits). You also need to check whether the ripple spec. is peak or peak-peak. Richard. http://www.rtrussell.co.uk/Article: 52363
Hi, Just a suggestion, have you tried using FPGA Advantage instead of Quartus II? Thank You, Best Regards, Mahesh On Thu, 6 Feb 2003, Giaccaglini Giorgio wrote: > Date: Thu, 6 Feb 2003 12:49:38 +0100 > From: Giaccaglini Giorgio <g.giaccaglini@libero.it> > Newsgroups: comp.arch.fpga > Subject: NIOS and ACEX1K > > Hi > > I'm trying to implement a NIOS CPU on a ACEX1K100-1 from Altera. > > The only problem that I have is the fmax that I can use; I need 33MHz while > Quartus II is able to use a fmax of 25Mhz. > > ACEX1K family should be able to support PCI interface ( 33Mhz and 64Mhz) so > I don't understand while the fmax is 25Mhz. > > Can somebody help me?. > > Thanks > > > >Article: 52364
I implemented the circuit described in the application note "Unusual clock dividers" written by Peter Alfke: http://www.xilinx.com/xcell/xl33/xl33_30.pdf. I used a Xilinx XC9536 and the input clock is generated by an oscillator (SCO-061S 48MHz) by Sunny. My problem is that the output clock's duty cycle is 33% and not 50% as expected. Why? Is the CPLD unsuitable for this circuit? Many thanks in advance.Article: 52365
Blake,
Looks like a potential...
1. Can I get a hold of a parts list? I am wondering what it would cost
to implement the hardware on my circuit board if I buy your license pack.
2. I notice the information references an Altera FPGA. Is there anything
inherently requiring an Altera part for the application? (For example,
altera specific intelectual property.)
3. As you folks seem to be expert, can you tell me what the maximum
length for USB2 is?
4. If I buy your daughter card, is the card USB2 certified? In other
words can I get away with using the USB2 logo? This is not critical, just a
question.
Thanks,
Theron Hicks
"Blake" <nobody@nowhere.com> wrote in message
news:dNI0a.3299$ta2.1475@nwrddc01.gnilink.net...
> The web site is at www.quickusb.com.
>
> Blake
>
> "Nobody" <nobody@nowhere.com> wrote in message
> news:CGI0a.3289$ta2.1025@nwrddc01.gnilink.net...
> > Terry,
> >
> > Check out our QuickUSB module and kits. It is designed to do exactly
what
> > you're looking for.
> >
> > Thanks,
> > Blake
> >
> > "Theron Hicks (Terry)" <hicksthe@egr.msu.edu> wrote in message
> > news:3E431E87.905ECF6F@egr.msu.edu...
> > > Hi,
> > > I am looking at design upgrade of an existing instrumentation
> > > project. Currently the design talks over a high speed bus to a rather
> > > expensive (~$1600 US) parrallel digital input board. The data rate
> > > would be on the order of 50M bits per second not including any
> > > overhead. I do not think I want to go to an all FPGA based solution.
> > > Currently the FPGA in the system is the smallest Spartan2e series
> > > device. By the way, quantities are very small, on the order of less
> > > than 50 pieces per year.
> > >
> > > So here are my questions...
> > >
> > > 1. Does anyone happen to know what the USB2 or firewire is rated
for
> > > in terms of the longest cable length? I had thought USB2 was limited
to
> > > about 2 meters but I have seen USB cables about 5 meters long
recently.
> > > A longer length interconnect would appear to be desireable. I know
that
> > > ethernet is good for several hundred meters. That would be far beyond
> > > my needs.
> > >
> > > 2. Has anyone had any experience with either USB2 or 100mB or
> > > firewire as an interconnect to an FPGA based design?
> > >
> > > 3. Do you happen to have any recommendations as to a possible
> > > off-the-shelf solution (either a small board or a 1 or two chip
> > > solution, ideally something with a demo board available)?
> > >
> > > Thanks,
> > > Theron Hicks
> > >
> >
> >
>
>
Article: 52366Aurash, Good idea but 2 problems. 1. The cost for the chip is about $110 compared to about $15 for the xc2s50e that I am using. This may be a minor cost differential when I add the cost of a fully integrated ethernet solution. However, I suspect that an integrated solution can be had for substantially less than $95 US. 2. The real show stopper for me is the package for this part. It is a BGA package. I know that you folks say that the BGA is no big deal but for me it is. I am just now getting used to fine pitch leaded packages. However, thanks for the response. I will keep it in mind if the rest of the responses are less ideal. Thanks, Theron Hicks "Aurash Lazarut" <aurash@xilinx.com> wrote in message news:3E43971A.72669198@xilinx.com... > Terry, > > You can use EDK ( embedded dev. kit) and spartan2e (xc2s400e or > xc2s600e) and build a small system around MicroBlaze > with Ethernet 10/100 MAC and use BRAM for the SW (tcp/ip stack) I've > used this "receipe" and it works fine. > > Aurash > > "Theron Hicks (Terry)" wrote: > > > > Hi, > > I am looking at design upgrade of an existing instrumentation > > project. Currently the design talks over a high speed bus to a rather > > expensive (~$1600 US) parrallel digital input board. The data rate > > would be on the order of 50M bits per second not including any > > overhead. I do not think I want to go to an all FPGA based solution. > > Currently the FPGA in the system is the smallest Spartan2e series > > device. By the way, quantities are very small, on the order of less > > than 50 pieces per year. > > > > So here are my questions... > > > > 1. Does anyone happen to know what the USB2 or firewire is rated for > > in terms of the longest cable length? I had thought USB2 was limited to > > about 2 meters but I have seen USB cables about 5 meters long recently. > > A longer length interconnect would appear to be desireable. I know that > > ethernet is good for several hundred meters. That would be far beyond > > my needs. > > > > 2. Has anyone had any experience with either USB2 or 100mB or > > firewire as an interconnect to an FPGA based design? > > > > 3. Do you happen to have any recommendations as to a possible > > off-the-shelf solution (either a small board or a 1 or two chip > > solution, ideally something with a demo board available)? > > > > Thanks, > > Theron Hicks > > -- > __ > / /\/\ Aurelian Lazarut > \ \ / System Verification Engineer > / / \ Xilinx Ireland > \_\/\/ > > phone: 353 01 4032639 > fax: 353 01 4640324Article: 52367
The Virtex macro should work in virtexE
Rainer Schmidt wrote:
> Hi,
>
> I would like to do Partial Reconfiguration on a Virtex-E. I need a bus
> macro for the communication between the reconfigurable modules. Xilinx
> Application note XAPP290 says, that Xilinx provides these macros.
> Unfortunately the example of this application note only contains bus
> macros for Virtex and Virtex-II FPGAs. These don't work for me.
>
> Can anybody tell me, where I can find the bus macro for Virtex-E?
>
> Thanks,
> Rainer
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 52368
Not without using or blocking the second half of the slice. What is the
motivation for doing a carry save adder here? The ripple carry arithmetic uses
half the area (because of the carry chain logic) and a tree made of FPGA ripple
carry adds is faster than one made of carry save adds because of the hit you take
on the routing. See my multipliers page on my website for a bit more detail (under
wallace tree multipliers).
Lars Unger wrote:
> Hi there,
>
> I am working on a realization of a Carry-Save-Adder for a Xilinx Virtex device.
> Up to now i was able to implement it using 2 LCs per Bit. However I read in the
> data book that arithmetic logic allows a 1-bit full adder per LC. This works
> fine for a Ripple-Carry-Adder. Is there any way to utilize the carry logic for
> the Carry-Save-Adder, too ?
>
> Best wishes,
> Lars.
> --
> GnuPG public key:
> http://www.ida.ing.tu-bs.de/~larsu/larsu_ida_ing_tu-bs_de.key
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 52369Hi Can anyone give me an estimate of the size of a 1024 pt FFT and the maximum frequency that it can run ? Will it fit on a 200K logic element fpga which does not have any onboard multipliers ? Is their any good rules of thumb for estimating the size of these FFTs ? Thanks AlanArticle: 52370
I tried the Virtex macro and it worked after I patched the family and device field in the .nmc file. Thanks for your response! Rainer Ray Andraka wrote: > The Virtex macro should work in virtexE > > Rainer Schmidt wrote: > > >>Hi, >> >>I would like to do Partial Reconfiguration on a Virtex-E. I need a bus >>macro for the communication between the reconfigurable modules. Xilinx >>Application note XAPP290 says, that Xilinx provides these macros. >>Unfortunately the example of this application note only contains bus >>macros for Virtex and Virtex-II FPGAs. These don't work for me. >> >>Can anybody tell me, where I can find the bus macro for Virtex-E? >> >>Thanks, >>Rainer >> > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > > >Article: 52371
Tullio Grassi <tullio@umd.edu> wrote in message news:<3E3EE388.9080604@umd.edu>... > Roberto Gallo wrote: > > Hello there, > > > > I am desiging a device that uses table lookups on processing of > > information (Writing an AES core). However as many as sixteen 256x8 bits > > tables should be used. These tables are equal in content, however they have > > independent indexing. > > I was wondering about how to group them, so that I could use FPGA´s > > memory intead of registers. Is it possible to use a multi-output memory? How > > to? > > I am using a APEX20K200 with Quartus II 2.0 and Leonardo and writing in > > VHDL. > > > > Thank you, > > Roberto Gallo. > > > > > > I think that LUTs fit particularly well the xilinx > distributed RAM. This feature is not available > on Altera devices (I've heard xiinx has a patent on it). > > -- > > Tullio Grassi > > ====================================== > Univ. of Maryland - Dept. of Physics > College Park, MD 20742 - US > Tel +1 301 405 5970 > Fax +1 301 699 9195 > ====================================== In the device you're in (20K family), you should use one ESB per table, so you'll need 16 ESBs. The 20K family has only one read port per ESB, so you have to use one ESB per table. In Stratix, the M4K RAMs have two read/write ports, so for a ROM like this you can use both ports to do reads. This means you can fit two of your tables in each M4K RAM, and you would only need 8 M4Ks. APEX II also has rams with two read/write ports, so you can use this trick to use only 8 RAMs in it too. Distributed RAM would not be a good solution for this application. Each LUT in distributed RAM has one read port, and only implements a 16x1 RAM. To build a 256 x 8 memory would take 16 * 8 = 128 LUTs just to get enough memory bits, and you would also need an extra LUT for each bit of width to do the final bit of address muxing. So 128 + 8 = 136 LUTs per table, and you would again need 16 tables, since you only have one read port per ROM. That's 2176 LUTs. You're much better off using the dedicated RAM structures. The other posters had good summaries of how to instantiate the RAMs you need. Vaughn BetzArticle: 52372
Consider that your 48MHz clock has a period just over 20ns. If your oscillator has a 50% duty cycle then you have edges (rising or falling) that can produce activity in synchronous logic at just over 10 ns intervals. This 10 ns value is the resolution that you can apply to your generated edges. To have a divide by 1.5, your desired frequency of 32MHz will have a period of just over 30 ns. Since your edge placement can only be on the 10 ns boundaries, you cannot get a 50% duty cycle. The only way to get a divide by 1.5 with 50% duty cycle is to use a PLL or DLL which isn't part of your CPLD or have another means - such as a delay line - to shift an edge by 5 ns or so. It isn't recommended that you try to build up 5 ns of delay inside the CPLD because delay times will change with temperature, voltage, manufacturing batch, phase of the moon and what not. "llaa57" <llaa57@yahoo.com> wrote in message news:5fde4855.0302070532.7af08737@posting.google.com... > I implemented the circuit described in the application note "Unusual > clock dividers" written by Peter Alfke: > http://www.xilinx.com/xcell/xl33/xl33_30.pdf. > I used a Xilinx XC9536 and the input clock is generated by an > oscillator (SCO-061S 48MHz) by Sunny. > My problem is that the output clock's duty cycle is 33% and not 50% as > expected. Why? Is the CPLD unsuitable for this circuit? > > Many thanks in advance.Article: 52373
I am correct in thinking Galois and Fibonacci LFSRs are mathematically equivalent? If I have a generator polynomial and I implement the two architectures do I need to do anything different to obtain the same sequences from the two? Thanks ChrisArticle: 52374
Are you looking at just a direct point-to-point connection between your proprietary hardware? If you use USB2 or Ethernet, there's overhead involved that you don't need if all you're doing is piping data. "Theron Hicks (Terry)" <hicksthe@egr.msu.edu> wrote in message news:3E431E87.905ECF6F@egr.msu.edu... > Hi, > I am looking at design upgrade of an existing instrumentation > project. [snip]
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z