Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMar2019

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 52300

Article: 52300
Subject: Re: Help needed
From: Aurash Lazarut <aurash@xilinx.com>
Date: Thu, 06 Feb 2003 11:49:58 +0000
Links: << >>  << T >>  << A >>


Buddy,

Be honest, when you're the last time in a library searching for something ... ?
Aurash

Buddy Smith wrote:

> Florin Franovici <ffranovici@redlinecommunications.com> wrote:
> > Basic arithmetic operations like: multiplication, adition, etc. Please don't
> > point me to printed textbooks becase I can't afford to buy any of these.
> >
>
> Where I am from, we have these magical places called 'libraries'.  Do they
> not exist in your area?
>
> --buddy

--
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/

phone:  353 01 4032639
fax:    353 01 4640324





Article: 52301
Subject: Re: Switching synthesis tools
From: Petter Gustad <newsmailcomp4@gustad.com>
Date: 06 Feb 2003 13:29:11 +0100
Links: << >>  << T >>  << A >>
<khtsoi@pc90026.cse.cuhk.edu.hk> writes:

> Also, does any one know which synthesis tool are the best *under
> Linux*?

Synplicity Synplify.
Synopsys Design Compiler.

The Design Compiler is mainly targeted against ASIC synthesis, but can
be used with libraries provided by Altera and Xilinx.

Altera Quartus (which has its own synthesis tool) is a *native* Linux
application even though it's built with a windows compability library
from Mainsoft. This is also the case for the Solaris version as well
as the Solaris version of Leonardo Spectrum I beleive.

Petter
-- 
________________________________________________________________________
Petter Gustad         8'h2B | ~8'h2B        http://www.gustad.com/petter

Article: 52302
Subject: Re: Help needed
From: Ray Andraka <ray@andraka.com>
Date: Thu, 06 Feb 2003 13:29:55 GMT
Links: << >>  << T >>  << A >>
FWIW,  I was at the URI library a few weeks ago looking up
some old DSP papers.  There's all kinds of good stuff in a
decent university library you simply won't find anywhere
else.

Aurash Lazarut wrote:

> Buddy,
>
> Be honest, when you're the last time in a library
> searching for something ... ?
> Aurash

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin
Franklin, 1759



Article: 52303
Subject: Re: clock ditribution tree
From: yves.tchapda@phyworks-ic.com (Yves Tchapda)
Date: 6 Feb 2003 05:45:11 -0800
Links: << >>  << T >>  << A >>
"Tauno Voipio" <tauno.voipio@iki.fi.SPAMBAIT_REMOVE.invalid> wrote in message news:<jvd0a.446$MG2.273@read3.inet.fi>...
> "Skillwood" <skillwoodNOSPAM@hotmail.com> wrote in message
> news:b1qqmt$15umdr$1@ID-159866.news.dfncis.de...
> > Hi all,
> > what is a clock distribution tree?
> > Skillwood
> >
> 
> Homework?
> 
> Tauno Voipio
> tauno voipio @ iki fi

Hi,
A clock distribution tree is a way of distributing the clock to all
the registers on the chip, with minimal skew, i.e phase difference
between the registers clock input.
In an FPGA, it's already done for you. If you're designing an ASIC,
you insert a clock tree after the placement of cells.

Cheers
Yves

Article: 52304
Subject: Re: Help needed
From: Aurash Lazarut <aurash@xilinx.com>
Date: Thu, 06 Feb 2003 14:02:09 +0000
Links: << >>  << T >>  << A >>


That's true,
what I was trying to say is that we are becoming more and more internet
dependent and sometimes I've seen people buying books from amazon.com
instead of going to the library (in most of the cases they end up going
to the library)
Aurash

Ray Andraka wrote:

> FWIW,  I was at the URI library a few weeks ago looking up
> some old DSP papers.  There's all kinds of good stuff in a
> decent university library you simply won't find anywhere
> else.
>
> Aurash Lazarut wrote:
>
> > Buddy,
> >
> > Be honest, when you're the last time in a library
> > searching for something ... ?
> > Aurash
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin
> Franklin, 1759

--
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/

phone:  353 01 4032639
fax:    353 01 4640324





Article: 52305
Subject: Re: Clock Enables
From: hess@cs.indiana.edu (Caleb Hess)
Date: Thu, 6 Feb 2003 14:26:25 +0000 (UTC)
Links: << >>  << T >>  << A >>
Well, CE does in fact 'enable' the clock - clock edges are ignored unless
CE is true. As for the sync/async question, doesn't your TA have office hours?

In article <9ea7e3a3.0302051413.661f861a@posting.google.com>,
Vishker <vishker@yahoo.com> wrote:
>I agree with Jussi. I know that CE it controls the data input but then
>why is called Clock Enable ? It should be called Data Enable as it is
>more close what it does.
>When you say Clock Enable, it basically means a signal controlling the
>clock. Its  like Clock is turned ON or OFF with CE and the closest
>circut I could think of would be like, a clock signal going through a
>tri-state gate whose enable is controlled by CE (clock enable). But we
>call it as Gated Clock citcuitry.
>
>How can you say a signal that controls or enables the clock, by its
>very definition, be Synchronous with the same Clock ? Don't you think
>its funny !!!
>
>-Vs
>
>
>
>
>Jussi Lähteenmäki <jusa@students.cc.tut.fi> wrote in message
>news:<b1qegk$l3j$1@news.cc.tut.fi>...
>> In comp.lang.vhdl Peter Alfke <peter@xilinx.com> wrote:
>> I've always wondered why they call it CE (clock enable) when in fact its 
>> DE (data enable). In the wonderful world of ASICs gated clocks are 
>> often preferred, when power consumption is of concern. In these flip-flops 
>> clock signals are anded with CE. The hard task is controlling the CE 
>> signals...
>> 
>> regards,
>> juza 
>> 
>> 
>> : CE controls a mux that makes the D input either look at the Q output ( clock
>> : disabled) or look at the incoming signal ( clock enabled). CE is, therefore,
>> : a synchronous signal.
>>  
>> : Peter Alfke
>> : ==========================
>> : Vishker wrote:
>>  
>> :> Is Clock Enable (CE) of Flip-Flop, Synchronous or Asynchronous signal ???
>> :> Pl. justify the answers.
>> :>
>> :> Thanks
>> :>
>> :> Vs


-- 
Caleb Hess						hess@cs.indiana.edu


Article: 52306
Subject: Max+PlusII: Design Doctor: synchronized by another clock
From: max <max@nospam.com>
Date: Thu, 06 Feb 2003 15:49:27 +0100
Links: << >>  << T >>  << A >>
Hello,

I have a (probably) simple question, but I really couldn't it figure out 
by myself:

I have a Altera 10k100A FPGA which is progammed in AHDL with the 
Max+PlusII Tool. The Design Doctor gives warnings of the following style:

 > Design Doctor Warning: Flipflop or synchronous memory 'sa_q0' 
receives > data that is synchronized by another Clock at flipflop or 
synchronous > memory 'ads_q'

However I have only a single clock of 33 MHz which is connected to the 
input-pin "lclk". This clock is passed to _all_ FlipFlops in the design 
via the global-primitve.

How can it than happen that sa_q0 and ads_q are not synchronized by the 
same clock???

Thanks a lot in advance!

	Max



Here are the code snippets:

lclk 		: input;	--local clock	
ladsn 		: input;
sa_q[18..0]	: dffe;


ads_q.clk = global (lclk);
ads_q.clrn = lresetn_q.q;
ads_q.prn = vcc;
ads_q.d = !ladsn;


sa_q[].clk = global (lclk);
sa_q[].clrn = lresetn_q.q;
sa_q[].prn = vcc;
sa_q[].ena = jkff_name.q & (dff_1_name.q # dff_2_name.q) # ads_q.q;
sa_q[].d = (sa_q[].q + 1) & (!ads_q.q) # (dffe_name[18..0].q & ads_q.q);


Article: 52307
Subject: Re: Max+PlusII: Design Doctor: synchronized by another clock
From: nospam <nospam@nospam.invalid>
Date: Thu, 06 Feb 2003 16:18:13 +0000
Links: << >>  << T >>  << A >>
max <max@nospam.com> wrote:

> > Design Doctor Warning: Flipflop or synchronous memory 'sa_q0' 
>receives > data that is synchronized by another Clock at flipflop or 
>synchronous > memory 'ads_q'

>However I have only a single clock of 33 MHz which is connected to the 
>input-pin "lclk". This clock is passed to _all_ FlipFlops in the design 
>via the global-primitve.

>sa_q[].ena = jkff_name.q & (dff_1_name.q # dff_2_name.q) # ads_q.q;
>sa_q[].d = (sa_q[].q + 1) & (!ads_q.q) # (dffe_name[18..0].q & ads_q.q);

I would assume that jkff_name and dfee_name are not clocked by lclk. 


Article: 52308
Subject: Silly Quartus Question
From: ruthsims@hotmail.com (Ruth)
Date: 6 Feb 2003 08:45:44 -0800
Links: << >>  << T >>  << A >>
Hi,

After creating a symbol from a piece of vhdl in Quartus, in the block
symbol editor, how can you move a port that appears on one side of the
block symbol to the other side?  I only seem to be able to move/drag
the port vertically, it won't let me drag it around the edges of the
block to the other side or top of the block?

Thanks

Ruth

Article: 52309
Subject: Re: Help needed
From: Ray Andraka <ray@andraka.com>
Date: Thu, 06 Feb 2003 16:48:35 GMT
Links: << >>  << T >>  << A >>
I think it is called 'lazy'.  Internet is great for a quick
answer, and there is lots of good stuff out there, but for
the most part, nothing with as much detail as you can get
spending an afternoon at your library.  I do often end up
buying books off of amazon, but it still is no substitute.

Aurash Lazarut wrote:

> That's true,
> what I was trying to say is that we are becoming more and
> more internet dependent and sometimes I've seen people
> buying books from amazon.com instead of going to the
> library (in most of the cases they end up going to the
> library)
> Aurash

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin
Franklin, 1759



Article: 52310
Subject: Re: Clock Enables
From: "John_H" <johnhandwork@mail.com>
Date: Thu, 06 Feb 2003 17:05:59 GMT
Links: << >>  << T >>  << A >>
How about if we call it Clockedge Enable?

The register changes at the clock edge, not the clock level.

The CE suppresses the behavior independent of whether a multiplexer is used
in the data path or if the master/slave flip-flop has presistent clock
gating that will make the clock-enable gate out the entire latch enable
window on the input latch of the master slave pair.

If the signal is deasserted, the clock edge will have no effect on the
register.

It has everything to do with the clock.


"Vishker" <vishker@yahoo.com> wrote in message
news:9ea7e3a3.0302052225.48708a61@posting.google.com...
> I don't agree with your RAM and ROM example. ROM no doubt is random
> accessable but is also Read Only Memory therefore ROM still holds
> good. Unlike Clock Enable where it has nothing to do with Clock at
> all.
>
> Or may be some non-native english speaking guy might have coined the
> term Clock Enable and the Intelligent English Speaking men might have
> followed it blindly.



Article: 52311
Subject: Re: difference between pci2.1 and pci2.2
From: Philipp Krause <pkk@spth.de>
Date: Thu, 06 Feb 2003 18:39:02 +0100
Links: << >>  << T >>  << A >>
praveen wrote:
> Hello Friends/Sir,
> I wanted to know what is the difference between PCI rev 2.1 and PCI rev. 2.2.
> 
> Waiting for Reply
> Thanks in advance
> Praveen

AFAIK 2.2 cards have to be 3.3 Volt compatible.

Philipp Krause


Article: 52312
Subject: Re: Clock Enables
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 06 Feb 2003 10:00:44 -0800
Links: << >>  << T >>  << A >>

I did not attack ROM. I said that "RAM" is a dumb name, since it does not describe the important aspect,
namely the read/write capability.

Clock Enable describes the high-level functionality properly.
The implementation detail is a separate story.
As an analogy:
In a car, we call something "accelerator pedal ( or gas pedal)", although it really is a
"butterfly-opening pedal" or nowadays an "increase squirt volume" pedal.
Sometimes it is better to stay at a higher and more abstract  level.

Peter Alfke
===============
Vishker wrote:

> I don't agree with your RAM and ROM example. ROM no doubt is random
> accessable but is also Read Only Memory therefore ROM still holds
> good. Unlike Clock Enable where it has nothing to do with Clock at
> all.


Article: 52313
Subject: Re: Clock Enables
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Thu, 6 Feb 2003 18:10:39 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <3E42A2CC.D49DF638@xilinx.com>,
Peter Alfke  <peter@xilinx.com> wrote:
>Clock Enable describes the high-level functionality properly.
>The implementation detail is a separate story.
>As an analogy:
>In a car, we call something "accelerator pedal ( or gas pedal)",
>although it really is a
>"butterfly-opening pedal" or nowadays an "increase squirt volume" pedal.
>Sometimes it is better to stay at a higher and more abstract  level.

If its a gasoline engine, it is BOTH open butterfly and increase
squirt volume pedal, as the gasoline engine is regulated by both
airflow and gasoline, and you don't want to run it too lean.  (It's
this airflow drop that is the big problem, and why gasoline engines
show compression braking.)

A diesel engine, it is just "increase squirt volume".

:)
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 52314
Subject: Parsic
From: "Aroen" <run(nospam)@arun.demon.nl>
Date: Thu, 6 Feb 2003 19:16:57 +0100
Links: << >>  << T >>  << A >>
Anybody experiences with this program?
(for PIC`s only)

Aroen.



Article: 52315
Subject: Re: JTAG from CAN
From: Tom <T.Otermans_REMOVE_THIS@home.nl>
Date: Thu, 06 Feb 2003 18:33:15 GMT
Links: << >>  << T >>  << A >>
Martin Thompson <martin.j.thompson@trw.com> wrote:
> 
>> I'm thinking of writing a new bootloader that initialises the CAN bus
>> and flashes the dsp and fpga. 
> 
> Sounds like the right approach for the DSP - although you may find
> that youy can't execute code from flash while writing to it, so you
> may have to do a funky optimised bootloader to run from internal RAM
> while you do it.  Or the device may have multiple flash blocks that
> can be prorgammed while code is running from another one.

I'm thinking of using external RAM for code space.  


> 
> Can you connect some of the DSP I/Os to the config EEPROM?  Then use
> the DSP to do the JTAG manipulations?  Otherwise, you may have
> problems doing it directly from the CAN bus without extra hardware.
> I'm afraid I don't know of anything that would do the job directly.
>

The eeprom only supports jtag loading so I have to make these jtag signals via i/o ports. 

Thanks for your advise, 

Tom Otermans


Article: 52316
Subject: Re: Xilinx Foundation 5.1: reasons to upgrade
From: "Patrick Mullarky" <pat@nwce.com>
Date: Thu, 6 Feb 2003 10:58:29 -0800
Links: << >>  << T >>  << A >>
The usefulness of the incremental design feature, in my opinion, is quite
subjective. I usually prefer complete reroutes for most designs. Others like
the feature. It does have a bit of a steep learning curve.

One really good reason to upgrade to ISE 5.1:

Xilinx's synthesizer in ISE 5.1, XST, does a surprisingly excellent job at
synthesis...and it comes included in the standard ISE package. It replaces
the FPGA Express synthesizer.

For the Xilinx parts I work with, XST seems to synthesize pretty much as
well as Synplicity's basic Synplify...and even basic Simplify costs a LOT !

I have run both synthesizers side-by-side for quite a while, and the
differences in gate synthesis, speed, and area are minimal...at least in my
current 1400 slice Spartan IIE design.

"Alphaboran" <alphaboran@yahoo-no-spam.com> wrote in message
news:b1rahs$1fa7$1@ulysses.noc.ntua.gr...
> Hello all,
>
> I just received the new version of the Xilinx Foundation tool. I now use
the
> 4.1 sp3 for my implementations, in the synthesis phase I use FPGA Express
> 3.6.1. My target devices are Virtex-EM.
>
> Are there any good reasons to upgrade my system? Does the new tool offer
> something really new and useful?
>
> I heard that with the new version you can keep the place AND routing of an
> implemented design and use it on later on altered design. If that's true
it
> seems very nice because with the 4.1 version even I make minor changes the
> only thing I can do is to keep the placement and not the routing. Is this
> the case or a rumor?
>
> Thanks in advance for your help.
>
> Best Regards,
> Harris
>
>
>



Article: 52317
Subject: Re: Help needed
From: Ray Andraka <ray@andraka.com>
Date: Thu, 06 Feb 2003 19:41:28 GMT
Links: << >>  << T >>  << A >>
Someone pointed out to me privately the difficulty in accessing
libraries in such places as Romania.  I concede on that point,
and offer my apologies to those who are not fortunate to be in
a place where they can get access to libraries.  For them, the
internet has provided access to technical information that
previously was simply not available.  Still, I know plenty of
US engineers who will look on the internet for info, but not
bother with taking a field trip to a library.  Hence my
comment.

Ray Andraka wrote:

> I think it is called 'lazy'.  Internet is great for a quick
> answer, and there is lots of good stuff out there, but for
> the most part, nothing with as much detail as you can get
> spending an afternoon at your library.  I do often end up
> buying books off of amazon, but it still is no substitute.
>
> Aurash Lazarut wrote:
>
> > That's true,
> > what I was trying to say is that we are becoming more and
> > more internet dependent and sometimes I've seen people
> > buying books from amazon.com instead of going to the
> > library (in most of the cases they end up going to the
> > library)
> > Aurash
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin
> Franklin, 1759

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin,
1759



Article: 52318
Subject: Re: clock ditribution tree
From: Thomas <zak@spam.invalid>
Date: Thu, 06 Feb 2003 20:50:43 +0100
Links: << >>  << T >>  << A >>
Tauno Voipio wrote:

>>what is a clock distribution tree?

> Homework?

It is a network of dividers to make useful frequencies out of the clock. The 1 
GHz that some processor runs at must be divided to L2 cache frequency (/2), 
memory access frequency (often /64 or /128), all the way down to timer tick 
frequency.

Because most of the divisions throw away half the clock frequency (and thus 
energy) as there is no need for a thousand million different 1 Hz signals, the 
clock tree often consumes a substantial fraction of the power of a chip.


Thomas


Article: 52319
Subject: Re: Clock Enables
From: Ray Andraka <ray@andraka.com>
Date: Thu, 06 Feb 2003 20:16:17 GMT
Links: << >>  << T >>  << A >>
Not entirely true.  The synchronous set/reset in Virtex is not affected by the
clock enable, yet it happens as a result of the clock edge.  I know...I am
splitting hairs now.  For an edge triggered flip-flop, which is how they are
generally used in FPGAs, 'clock' infers 'clockedge'

John_H wrote:

> How about if we call it Clockedge Enable?
>
> The register changes at the clock edge, not the clock level.
>
> The CE suppresses the behavior independent of whether a multiplexer is used
> in the data path or if the master/slave flip-flop has presistent clock
> gating that will make the clock-enable gate out the entire latch enable
> window on the input latch of the master slave pair.
>
> If the signal is deasserted, the clock edge will have no effect on the
> register.
>
> It has everything to do with the clock.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 52320
Subject: Re: difference between pci2.1 and pci2.2
From: weirdo@bbs.frc.utn.edu.ar (Mauricio Lange)
Date: 6 Feb 2003 13:41:04 -0800
Links: << >>  << T >>  << A >>
praveenkumar1979@rediffmail.com (praveen) wrote in message news:<ff8a3afb.0302060159.5d8fc9e9@posting.google.com>...
> Hello sirs/Friends
> please tell me the difference.What new thing is added in PCI2.2 when
> compared to PCI2.1.I think the protocol is the same...is't it????. so
> if i can implement PCI2.1 that is equivalent to PCI2.2.
> 
> waiting for reply
> Thank in advance
> praveen


Praveen, 
 
  The protocol is the same, the differeces are minor:
  - some related to the Configuration Header registers,
  - some related to Power Management, 
  - the LOCKing mechanism now is intended to be used only by bridges, 
  - it is forbidden now to simultaneously drive and receive a signal,
  - configuration mechanism #2 is no longer an option in PCI spec rev
2.2
  - a Vital Product Data section has been added, 
  - and some other that I cannot remember now

 If you follow the rules of the PCI 2.1 spec, you will have no trouble
with the rev 2.2.

 What is following the rules? If the spec says, Pin reserved, you dont
use that pin. If the spec says, register reserved, must return all
zeros, you must return zeros when the register is read.

 I remember, too, that with rev. 2.2 the PCI SIG incorporated ECNs,
Engineering Change Notice, that updates and corrects minor items.
For example, the ECN Oct-25-1999 is about the Minimum PCB
Characteristic Impedance for PCB Expansion Cards.
The rectify the impedance value specified in the PCI Spec, changing it
from 60ohms to 51ohms, for the case in wich the device input
capacitance is less than or equal to 8pf.

Regards,

Mauricio Lange

Article: 52321
Subject: Re: Clock Enables
From: Theron Hicks <hicksthe@egr.msu.edu>
Date: Thu, 06 Feb 2003 17:05:37 -0500
Links: << >>  << T >>  << A >>


Yves Tchapda wrote:

> Theron Hicks <hicksthe@egr.msu.edu> wrote in message news:<3E41419E.ADE8C2CF@egr.msu.edu>...
> > Peter,
> >     You forgot those who sleep through class, either at home or in the
> > classroom, as well as those who do not speak the same language as the
> > instructor.  This is intended to reference both students and instructors who (in
> > the case of the USA) are non-native speakers of English.  This is not intendend
> > as a slam to those who do adequately learn the language of the country where the
> > instruction is being given.  It is merely a comment on the sad state of affairs
> > where instructors and/or students need not and do not learn the language
> > sufficiently to be able to communicate technical concepts.  In fact, in some
> > cases, the instructor cannot communicate technical data because they themselves
> > are technically incompetent.  However, I suspect that the problem you are
> > discussing here is one of laziness.  Unfortunately, these people will graduate
> > and be hired by unsuspecting companies.  Due to a fear of lawsuits, these same
> > people will be passed along to unsuspecting employer after unsuspecting
> > employer.
> >
> > Enough of the rant...
> >
> > Thanks,
> > Theron Hicks
> >
>
> Theron,
> This is hardly the forum to place your grievance, which goes far
> beyond what this newsgroup is intended for, and is very unwarranted.

You are right.  It is probably the wrong forum.  It is also the wrong forum for getting homework
answers.

As for unwaranted, I see you are a PHd.  Are you also a university proffessor?  I am not, but I
do work in a university setting.  I do see a lot of lazy students who cheat their way through
tests and homework semester after semester.  I have suffered through incompetent professors.
While most of my professors speak the language fairly well, I have had to deal with incompetent
and arrogant professors in classes I have taken recently.  These professors are widely
recognized as incompetent within the university.   I have also had to deal with students who
cannot speak the language.  Stories of Professors who do not speak the language are far to
common.  By the way, I also have had the pleasure of incredibly talented and motivated
professors and students as co-workers and instructors.  The "bad apples" are fortunately a small
percentage.

Theron

>
> Let's concentrate on technical issues, and could we please be humble
> enough and have patience for those with less knowledge?
>
> "I know one thing: I know nothing"
>
> Dr Yves Tchapda


Article: 52322
Subject: Re: low pass FIR filter in FPGA
From: jetmarc@hotmail.com (jetmarc)
Date: 6 Feb 2003 14:19:19 -0800
Links: << >>  << T >>  << A >>
> input data is 9 bit samples at 33.325714 MHz (or possibly 31.104 MHz)
> 1 dB ripple allowed in pass band (0 - 7MHz), minimum of 65 dB down in
> the stop band. (8 MHz)

Last time I checked, 9 bits don't offer 65dB dynamics so the spec looks
flawed.

Article: 52323
Subject: Re: clock ditribution tree
From: MR <mrohm@gtemail.net>
Date: Thu, 06 Feb 2003 16:14:53 -0800
Links: << >>  << T >>  << A >>
Interesting theory,  but wrong.

(except for the last clause that begins with "the clock tree often...")



Thomas wrote:

> Tauno Voipio wrote:
> 
>>> what is a clock distribution tree?
>>
> 
>> Homework?
> 
> 
> It is a network of dividers to make useful frequencies out of the clock. 
> The 1 GHz that some processor runs at must be divided to L2 cache 
> frequency (/2), memory access frequency (often /64 or /128), all the way 
> down to timer tick frequency.
> 
> Because most of the divisions throw away half the clock frequency (and 
> thus energy) as there is no need for a thousand million different 1 Hz 
> signals, the clock tree often consumes a substantial fraction of the 
> power of a chip.
> 
> 
> Thomas
> 


Article: 52324
Subject: HELP NEEDED
From: "Jim Raynor" <chris_cheung66@hotmail.com>
Date: Fri, 07 Feb 2003 00:19:14 GMT
Links: << >>  << T >>  << A >>
hi,

    does anyone know how to tell the synthesis tool not to remove the
duplicate logic?  I am using Xilinx Foundation and synthesis tool is
XST....the target device is Virtex-E..

    Also I have a very high fanout signal in my design...does anyone have
any suggestion to deal with the high fanout signal?  I can't have that route
to ibufg because the PCB is already done...The phyiscal pin location of that
signal make it impossible to route to ibufg... so please advise..

    Thanks

    Chris





Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMar2019

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search