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Hi, Everybody! I'm trying to implement a FIFO that interfacing MASTER and SLAVE, which can do Burst accesses. It is available for both MASTER and SLAVE to Write and Read simultaneoulsy, for example, Master is trying burst write to Slave and Wirting to FIFO, and after a clock Slave is trying read from FIFO which master has written to it.(at the same time Master is writing to FIFO with another address!) Any ideas will be appreciable, Thank you . -- ÿØÿàArticle: 11702
This is exactly what I need, however, OrCAD will not
let me initialze state_var to w0 in this way. If I do
it inside the process as shown below it will always
return to the initial value (which I obviously dont
want). How can I get around this?
process
type state_type is ( w0 , w1 );
variable state_var : state_type; -- := w0 *Cant have this here
begin
state_var := w0; -- This wont work either!!!
wait until clk = '1';
case state_var is
when w0 => p1( .. ); state_var := w1;
when w1 => p2( .. ); state_var := w0;
end case;
end process;
> process
> type state_type is ( w0 , w1 );
> variable state_var : state_type := w0;
> begin
> wait until clk = '1';
> case state_var is
> when w0 => p1( .. ); state_var := w1;
> when w1 => p2( .. ); state_var := w0;
> end case;
> end process;
>
> That pronciple also works for branches and while-loops with waits.
Article: 11703
Phillip Cook <cook-pa@eelab.usyd.edu.au> writes:
> This is exactly what I need, however, OrCAD will not
> let me initialze state_var to w0 in this way. If I do
> it inside the process as shown below it will always
> return to the initial value (which I obviously dont
> want). How can I get around this?
>
> process
> type state_type is ( w0 , w1 );
> variable state_var : state_type; -- := w0 *Cant have this here
> begin
> state_var := w0; -- This wont work either!!!
> wait until clk = '1';
> case state_var is
> when w0 => p1( .. ); state_var := w1;
> when w1 => p2( .. ); state_var := w0;
> end case;
> end process;
>
>
Most, if not all, support at least the following templates for synthesisable VHDL.
PROCESS
BEGIN
WAIT UNTIL clk='1'; -- or WAIT UNTIL clk='1' AND clk'EVENT; or rising_edge(clk);
IF reset='1' THEN
-- reset actions
ELSE
-- the rest
.....
END PROCESS;
In this tempate the WAIT STATEMENT must be the first statement!
In case you have a asynchronous reset, another template is often supported for synthesis
PROCESS (reset, clk);
BEGIN
IF reset='1' THEN
-- resetactions
ELSIF clk='1' AND clk='1' THEN
-- synchronous part
Back to your description. Your statemachines remains (from a simulation point of view)
in state 'w0' forever! In the case statement you assign a new value to state_var, but
this is overruled by the statement by the statement just before the WAIT STATEMENT.
My suggestion is to add a reset signal, and depending on a synchronous or asynchronous
reset choose a template.
Egbert Molenkamp
Article: 11704On Wed, 02 Sep 1998 17:02:01 +1000, Phillip Cook <cook-pa@eelab.usyd.edu.au> wrote: >This is exactly what I need, however, OrCAD will not >let me initialze state_var to w0 in this way. If I do >it inside the process as shown below it will always >return to the initial value (which I obviously dont >want). How can I get around this? This is another common synthesis restriction - you can't specify initial values for signals and variables. This makes sense (like a lot of synthesis restrictions) - since it could be difficult for the synthesiser to work out what's required (when is 'initialisation'? Is it power-on, or is there a specific reset signal? What is the reset signal? Does the initialisation state conflict with an explicit reset state? Does the hardware have power-on capability? etc.) To get around this, you have to have a reset signal, and you have to explicitly reset your state variable to the required state. EvanArticle: 11705
For synchronous FIFOs, the third counter works fine. However, for async FIFOs, you need to resync one side of the FIFO to get the read and write enables into the same clock domain if you use the third counter. If the data rate on one side is considerably lower than the clock rate on the other side, then synchronizing the data with a register works great. However, if the data rates on both sides are close to each other and the rate is near the system clock (highest clock available) then resynchronizing can become a headache. In this case, the better solution is to use gray code counts for the read and write pointers and decode the difference to generate the asynchronous flags. The empty/full logic will need a memory element to distinguish between the empty and full conditions (both occur when the read and write pointers are equal). The half full can be decoded directly from the difference, although with a gray code count, it may be easier to use a memory element and detect the half way point to toggle the flag. Rickman wrote: > There seems to be no shortage of answers to this question. I just > designed such a circuit. However I took advantage of the fact that I was > not using the FIFO at full speed. My clock is 33 MHz (could be faster) > but the write data only arrives at 160 ns intervals. The read output has > to be full speed. So I ran the entire FIFO circuit off of the read clock > and simply(?) synchonized the write request signal to the read clock. > This worked very well and was very simple. > > I got the half full flag by using three counters. The read and write > counters are 4 bit up counters. The data counter is up/down with enough > control logic to handle the simultaneous read/write case (hold count). I > can't remember is I made the data counter 5 bits or just 4 bits. 5 bits > are needed to indicate the full 0 to 16 range. Of course half full is > when this counter is at 8 (or greater). > > -- > > Rick Collins > > redsp@XYusa.net > > remove the XY to email me. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 11706
I've been following the thread about DPLLs with some interest... not all of the discussion has really been about phase-locked loops, I suspect, but even so... Peter wrote: > > >The Zilog SCC has an interesting digital PLL. > Yes, I have always been looking for the schematic of that particular > design. Would be VERY useful. Errm, well, maybe, says this designer with the very badly burned fingers. The logic of that DPLL is really quite thoroughly described in the Zilog and AMD databooks for the SCC and it wouldn't be too hard to reproduce it, particularly in VHDL or Verilog. But the snag is, you need to be VERY careful about what you think the DPLL is doing for you. Two big problems I've come across - on both counts I had to jettison the SCC DPLL and design my own, in an FPGA.... 1) READ THE FINE PRINT. Very early 8530 SCCs used the DPLL-recovered clock both for the receive and for the transmit data clock. Users got a bit miffed about this because there was too much jitter on the transmit clock, making it harder to receive at the other end. Later, Zilog "fixed" it so that the Tx clock is just a straight divider off the crystal, even when using the DPLL for receive clock generation. Squeaky-clean transmit clock, *** but at a different frequency from the Rx clock *** which is a bit sad if you want to pass on the same bitstream to a downline station, as in SDLC Loop mode which the SCC otherwise supports rather well. So, the bottom line (which can be inferred from the data book, but is nowhere made explicit) is that you can't use the DPLL in SDLC Loop mode. Very, very sad. 2) THE REAL WORLD IS HORRIBLE. I used HP fibre-optic devices to implement a 1Mbit/s serial loop with 8530 SCCs and came across another problem. The fibre devices have a propagation delay which is spectacularly different for rising and falling edges of the signal, and worse still this difference is a very strong function of the optical attenuation of the link. So you get horrible distortion of the received pulses, in my case up to +/- half a bit time (!!!). This introduced disastrous jitter in the DPLL output which I never managed to fix until I did a totally new DPLL design. The mega-super-whizzo DIY design I came up with actually has two separate "loops": the first, to recover the receive clock, makes intelligent guesses about where to expect rising and falling edges (effectively adapting to the attenuation- dependent pulse width distortion) and the second is pretty much a genuine DPLL, reconstructing its best attempt at a smooth, jitter-free clock at the same freq. as the receive clock, for use by the transmitter. If I can get permission from the folks I designed it for, I'll post it to the NG (in Verilog). BTW - someone (in another thread) recommended starting a biggish design in schematic but suggested that the "HDL bigots" might disapprove. This particular HDL bigot doesn't disapprove of anything at all except unnecessary hard labour (and, perhaps, bigotry) and the DPLL design I've described is a nice example of something that is clear, well-documented and small in an HDL but would be a nightmare to design in schematic. Horses for courses.... Jonathan Bromley ----------------------------------------------------------------------------- Electronics is fun. If you want me to take it seriously, call and we'll talk consultancy rates. -----------------------------------------------------------------------------Article: 11707
You've probably heard about the Reuse Methodology Manual (RMM) that was jointly published by Synopsys and Mentor Graphics at DAC '98 through Kluwer Academic Publishers (see hotlink below). While the book is the first serious attempt at addressing the tough issues of design for reuse, it falls short in dealing with many critical aspects of reuse, and even offers misleading information. Check out Janick Bergeron's constructive critique, identifying the good and the not-so-good aspects of this important work, in the Qualis library: http://www.qualis.com/cgi-bin/qualis/libObject.pl?object=mb011 This critique was originally published in John Cooley's very useful ESNUG mailing list in August, issues 297 and 298. We think John's ESNUG is way-cool, and encourage you to subscribe by sending John email at mailto:jcooley@world.std.com You can find more info on the RMM book at http://www.wkap.nl/book.htm/0-7923-8175-0 . MichaelArticle: 11708
If your design/development effort needs additional/complimentary FPGA talent, we can help! Regards, Blake Nelson nelson@cstn.comArticle: 11709
In article <01bdd5de$7e6f6ed0$4601fc8c@shootingstar>, Andy Peters <apeters@noao.edu.NOSPAM> writes >gang, > >Is there an easy way to constrain the Xilinx implementation tools to >NOT use certain pins when choosing pinouts? And is there a way to constrain a pin to a *range* of pins, for example where a RAM chip is involved and you don't care which physical data pin is used for any particular logical data line? I asked here before with no luck, so I suppose this can't be done, but maybe it's worth asking a supplementary question on the back of Andy's. TIA? -- Keith WoottenArticle: 11710
Blake Nelson wrote: > If your design/development effort needs additional/complimentary FPGA > talent, we can help! > > Regards, > Blake Nelson > nelson@cstn.com com-pli-men-ta-ry adj. Given free to repay a favor or an act of courtesy. reference: the american heritage dictionary of the english language i guess it's a good dictionary, it's kind of fat. mighty kind of you guys, just my $0.02, rk p.s. please direct replies to comp.arch.fpga.classifiedsArticle: 11711
Visit us at www.aldec.com for dates & locations. Brent Wood Customer Service Manager Aldec Inc. 702.990.4400x208 brent@aldec.comArticle: 11712
As FPGAs grow, the need to re-use designs and source designs from third parties is going to become more and more important. Of course these designs vary from simple library components to more complicated DSP functions and PCI cores. I would like to start a discussion with people who have had experience 'using someone else's design' addressing: 1. Why did you use someone else's design? What was the design you used? 2. Did it work out as planned? 3. What problems did you encounter? 4. Given your time over, would you make the same decision? -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member ForumArticle: 11713
Good deals on XILINX Foundation and Prortotyping boards can be gotten from: http://www.associatedpro.com There are also a lot of good free on line technotes and tutorials for VHDL and FPGAs. Rickman wrote: > Phillip Cook wrote: > > > > I am writing a VHDL model to be synthesized and compiled using > > OrCAD Express. The model synthesizes but when I try to compile > > I get two errors that are going to cause me a lot of trouble. > > > > 1) It says that it cant compile a while loop > > > > 2) It says that it cant compile multiple wait statements in the > > one process. > > > > Are these standard VHDL restrictions or is it just an OrCAD > > restriction? Is there any easy way to get around these probs? > > > > TIA > > Phil. > > -- > > Let me throw in my two cents worth. I would say you are making two > mistakes. The first (and least important) is that you need to get some > good references on how to program VHDL for synthesis. I just spent about > 6 months coming up this learning curve and it is not easy. > > I said you should get good references, the problem is that I don't think > there are any good easy references. I believe that VHDL for synthesis is > much harder to learn than any programming language I have ever worked > with. Part of the problem is that each vendor implements his own subset > of the language for synthesis and the tools work differently with > similar code. So you won't be able to find a universal reference like > you can with 'C' or Pascal. Figure that you will have to take a couple > of months extra to develop your skills. > > The second mistake you are making (in my opinion) is using the Orcad > tool set. I started using Orcad 7.2. I spend many hours on the phone > with support until I finally threw in the towel and got the Xilinx > Foundation tools. Now my project is back on schedule and almost done. > > I have received the new release 9.0 from Orcad, but I haven't opened it > and may well not. They told me that they might be switching VHDL tools > with this release, so I might give it another try. But their product > support has been very, very bad and many people on this newsgroup will > echo my comments. > > You might seriously consider switching now rather than waiting until the > middle of your project like I did. > > Rick Collins > > redsp@XYusa.net > > remove the XY to email me. -- __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ Richard Schwarz, President EDA & Engineering Tools Associated Professional Systems (APS) http://www.associatedpro.com 3003 Latrobe Court richard@associatedpro.com Abingdon, Maryland 21009 Phone: 410.569.5897 Fax:410.661.2760 __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 11714
Hi, Everyone~ What will happen if a VHDL logic circuit is same as FPGA/CPLD's Logic Cell Architecture? Will it be implemented as one Logic Cell? OR Will it be implemented as some LCs? For example, ALTERA FLEX 10k's EAB has a arechitecure like this : MUX->DFF->MUX->RAM/ROM->DFF->MUX. and someone made a Logic like above, then what is the result of synthesized circuit? Thank you.Article: 11715
On Wed, 02 Sep 1998 16:39:47 +0100, Jonathan Bromley <jsebromley@brookes.ac.uk> wrote: > making it harder to receive at the other end. Later, Zilog "fixed" >it so > that the Tx clock is just a straight divider off the crystal, even >when > using the DPLL for receive clock generation. Squeaky-clean transmit >clock, > *** but at a different frequency from the Rx clock *** which is a bit >sad if > you want to pass on the same bitstream to a downline station The point of a PLL is that it should be able to lock over a frequency range - it shouldn't matter if the transmit clock is at a different frequency, as long as it's within the lock range of the downstream station. Are you saying that, in a chain of three SCCs, the third one couldn't retrieve a data stream generated by the first one (which would of course make the SCC useless?) >2) THE REAL WORLD IS HORRIBLE. I used HP fibre-optic devices to >implement a > 1Mbit/s serial loop with 8530 SCCs and came across another problem. >The fibre > devices have a propagation delay which is spectacularly different for >rising > and falling edges of the signal, and worse still this difference is a >very > strong function of the optical attenuation of the link. So you get >horrible > distortion of the received pulses, in my case up to +/- half a bit >time (!!!). You used fibre optic at *One Megabit* and got distortion of *500 ns* ??? There seems to be some confusion here - can you tell us (a) which HP device and connector, (b) what cable, (c) what cable length? EvanArticle: 11716
YongKook Kim <likepunk@secsm.org> wrote: >What will happen if a VHDL logic circuit is same as FPGA/CPLD's Logic >Cell Architecture? >Will it be implemented as one Logic Cell? >OR Will it be implemented as some LCs? Most VHDL synthesis tools (that I've seen) will create a 'flat-file' of the entire design, and then optimize it. This may create logic blocks that you didn't expect, but that always seem to work just fine. However, if you use some of the VHDL 'primitives' (such as AND(), OR() etc.) to create the design, then it will probably map just the way that you expect. This also depends upon the VHDL synthesis tools that you're using. Different tools will do this in different ways. Wade Peterson Silicore Corporation http://www.silicore.net/Article: 11717
wluka@hotmail.com wrote: >As FPGAs grow, the need to re-use designs and source designs from third >parties is going to become more and more important. Of course these designs >vary from simple library components to more complicated DSP functions and PCI >cores. >I would like to start a discussion with people who have had experience 'using >someone else's design' addressing: >1. Why did you use someone else's design? What was the design you used? >2. Did it work out as planned? >3. What problems did you encounter? >4. Given your time over, would you make the same decision? I have used other people's designs, as well as created some of my own for use by other people. My experiences have varied widely. What I've found is that when the original design is documented and supported very well (good manuals, somebody to answer questions etc.), then it is much easier to re-use the design. If these aren't available, then it is very difficult to re-use the design. I guess this statement is true whether you're talking about a reusable FPGA design, or an off-the-shelf IC chip. I recently did a design with a 'triple-DES' encryption IC the was the most miserably documented piece of $%&#)#! that I had ever seen. Not surprisingly, it took a lot of time and experimentation to make it work. The same is true for re-usable logic cores. A second important issue is portability. The various FPGA vendors have different internal architecutures which make them difficult to re-use. A portability statement should be part of the product documentation. We recently released a VHDL reusable core for an 8-bit RISC uP. This product was documented, and is supported, to alleviate these problems. You can download our manual at http://www.silicore.net/ if you would like to see an example. The experience of customers has been very good with this product. The last person to use it was relatively experienced in VHDL & FPGA's, and was able to synthesize the design after about a day of work (and a couple of phone calls). That day of time included reading the manual, loading the software, etc. Wade Peterson Silicore CorporationArticle: 11718
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--------------E61E137F59588B1C5678A177--
Article: 11719This is a multi-part message in MIME format. --------------E61E137F59588B1C5678A177 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit --------------E61E137F59588B1C5678A177 Content-Type: message/rfc822 Content-Transfer-Encoding: 7bit Content-Disposition: inlineArticle: 11720
This is a multi-part message in MIME format.
--------------8370604E399EBFD45B7A6BDD
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Daniel T. Schwager wrote:
>
> Hi together,
>
> i have to design a VHDL-based FPGA which
> have to contact an uC-Databus (DB0..DB15).
> In my design, there's an FPGA internal tristate
> bus named "db".
> My problem is, that i don't know how to connect
> a bidirectional and tristate bus "db" to the FPGA pads.
> Should i use some library-objects like "ibuf16" ?
>
> Maybe somebody has an example-vhdl code for solving this
> "small" problem !
The vhdl source should have something like:
db <= mux when (oe = active) else (others =>'Z');
With exemplar tools, pin assignments and buffers are handled
by the back-end place and route tool. The only related source
is a constraints file which is not VHDL code.
-Mike Treseler
--------------8370604E399EBFD45B7A6BDD
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Content-Transfer-Encoding: 7bit
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begin: vcard
fn: Mike Treseler
n: Treseler;Mike
org: Fluke Networks Division
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email;internet: tres@tc.fluke.com
title: Sr. Staff Engineer
tel;work: 425.356.5409
tel;fax: 425.356.5043
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--------------8370604E399EBFD45B7A6BDD--
Article: 11721ASIC DESIGN SERVICE Hello ASIC decision maker: we are ASIC design house that have expertise starting from FPGAs to all the way to full custom chips. If you need ASIC design services please visit us at following URL.We also specialize porting your existing FPGA design to full ASIC. http://www.iss-us.com/AsicTeam.htm Thanks. Khan. kkibria@iss-us.com (714)587-0628Article: 11722
HI,
I'd like to implement a fast I/O pin configuration on
ALTERA's Flex10k20RC208-3
but I couldn't assign that logic option on it.
I choosed 'Assign -> Logic option ->Node Name->Individual
logic option-> Fast I/O'.
But at the floor plan editor, and *.rpt file says that it
was not implemented on IOE.
My VHDL description is bleow. How can I make above possible?
Please help me.
Thank you always...
library ieee;
use ieee.std_logic_1164.all;
entity tri_bus is
port( CLK,dir: in std_logic;
b_inout : inout std_logic_vector(31 downto 0);
b_out : out std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0));
end tri_bus;
architecture a of tri_bus is
begin
process(dir,b_in,b_inout)
begin
if dir='0' then -- Input from Bidirectional
port to Local port
b_inout <= (others =>'Z');
B_OUT <= B_INOUT;
else -- Output Local port to
Bidirectional port
B_INOUT <=B_IN;
end if;
end process;
end a;
Article: 11723
HI,
I'd like to implement a fast I/O pin configuration on
ALTERA's Flex10k20RC208-3
but I couldn't assign that logic option on it.
I choosed 'Assign -> Logic option ->Node Name->Individual
logic option-> Fast I/O'.
But at the floor plan editor, and *.rpt file says that it
was not implemented on IOE.
My VHDL description is bleow. How can I make above possible?
Please help me.
Thank you always...
library ieee;
use ieee.std_logic_1164.all;
entity tri_bus is
port( CLK,dir: in std_logic;
b_inout : inout std_logic_vector(31 downto 0);
b_out : out std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0));
end tri_bus;
architecture a of tri_bus is
begin
process(dir,b_in,b_inout)
begin
if dir='0' then -- Input from Bidirectional port to Local
port
b_inout <= (others =>'Z');
B_OUT <= B_INOUT;
else -- Output Local port to Bidirectional
port
B_INOUT <=B_IN;
end if;
end process;
end a;
Article: 11724Can't quite remember the proper syntax for a Verilog or VHDL statement? Confused about which Verilog simulation control system tasks are available? Want to know which VHDL conversion functions are supported in Synopsys' STD_LOGIC_ARITH package? No problem. Just download our free Quick Reference Cards and the entire language syntax will be right at your fingertips. They're accessible in the Qualis Library at http://www.qualis.com/cgi-bin/qualis/libObject.pl?object=tr010 You can also receive our QRCs on 2-sided, tri-folded, incredibly durable paper direct from Qualis. Just send your request to mailto:info@qualis.com. Michael
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