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Jamie, thanks. Say is the rbf file an ascii file? When I looked at it once, it looked unreadable so how can I extract information to program an Altera Flex 10k if I can not read it as ascii text? The same applies to the ttf file. With the .hex file, I have ascii hex data that I can look at. Also, you mention that the Reset needs to be strobed for 5 useconds. I did not see any information in Altera's Application notes. Is this really necessary? If so, is it because it prevents the jtag mode from being used? Thanks in advance. Jim Jamie Lokier wrote in message ... ><jamesantone@if.rmci.net> writes: >Deassert the reset signal first followed by a short delay (5 >microseconds in the code I have here, don't know if that's specified). > >You can use some conversion menu in Maxplus to convert to .rbf format, >which is simply raw binary data. The .ttf is good for #include'ing in a >C file. I tend to read the .ttf into a program just because invoking >Maxplus to do yet another step is so tedious. > >Hope this helps, >-- JamieArticle: 12926
On Wed, 04 Nov 1998 21:53:53 -0700, "Thomas D. Tessier" <tomt@hdl-design.com> wrote: >What does Exemplar generate? Is this a piece of hierarchy that you can >operate on? I have not use Exemplar for quite some time, but the Block >feature didn't work. It would just ignore it! both leonardo and spectrum flatten out blocks in the edif, but they work fine as VHDL block statements. i haven't been following this thread, but it seems that ed is saying that they're supported, rather than that the block boundary is maintained. evanArticle: 12927
It's usually just as easy to just blast the part and measure the current consumption with an amp-meter. "Erik de Castro Lopo" <e.de.castro@fairlightesp.com.au> wrote: >Hi all (and paticularly Xilinx), >I'm currently doing a design with XC4000XL and XC9500 >parts and have been asked to estimate power consumption >of the finished design. >Xilinx on their web site does have an app note on how >to estimate design power consumption, ands thats how >I'll be doing it. However I also thought wouldn't it be >great if part of the Xilinx software could estimate >power consumption on a completed design, given the >clock frequencies and a given load capacitance for >the outputs. It would also be really useful if it >could estimate a probable error. >What do the other readers of this group think? >ErikArticle: 12928
There are a couple of very good sources about interfacing PC parallel ports. They aren't specific on your Altera question, but they have all the information about hardware and software interfacing: IEEE 1284-1994 IEEE STD Signalling Method for a Bidirectional Parallel Peripheral Interface for Personal Computers. Available from the IEEE. Parallel Port Complete by Jan Axelson. ISBN 096508191-5 jhon@geocities.com wrote: >Does anybody know how to connect an Altera Flex10k device to a PC >Parallel Port, particularly the electrical specifications do to this (not >to program the device, but to exchange data between PC and Flex10k). >Thank you in advance. >-------------------==== Posted via Deja News ====----------------------- > http://www.dejanews.com/ Search, Read, Post to UsenetArticle: 12929
Hi: Please somebody tell me, where I can get free I2C model? -- HenryArticle: 12930
This migh be a silly question, but since I am not that confident when it comes to asynhronous design i will ask anyway... >2: Get hold of XAPP 51, preferably with Peter Afke's revision that has >full gray coded address counters. > >4: Read XAPP 94, which says how good the 4k CLBs are at metastability >recovery, and so decide to use the flip-flops in XAPP 51 rather than the >stretched Full and Empty signals. The stretched signals rely on a latch >whose metastability behaviour has not been characterised and which is >likely to be much worse than the CLB flops. The flip-flops in XAPP 51 (figure 5) have a Pre-set port that is connected to EMPTY' and FULL'. Is this a synhronous or asynhronous pre-set? What I am conserned about is when, for instance, the FULL signal goes inactive, synhronized to the READ clock. What happens if this is inside the set-up "window" of the flip-flop that is clocked by the write clock? Any comments or explanations are apreciated! Jonas ThorArticle: 12931
>But still the XL devices with the clamping diodes would harm the 5V >drivers on the local side and now I can't have a 2.5V supply for the >Virtex series. You may already know this but the Altera 10K? parts have individually controlled clamping diodes. Did Virtex not copy this? >I was thinking that leaving the clamping diodes >unconnected would not make any difference to the PCI signal integrity. What you need is for someone whos actually done the Spice sim to comment on why they are there. There's go to be a reason. The question is does it apply in your case. Lacking that info I would bite the bullet and either put the diodes on the board external to the FPGA or switch to a part with the individual controls like the 10KA (I think). good luck SteveArticle: 12932
peter299@maroon.tc.umn.edu wrote: > It's usually just as easy to just blast the part and > measure the current consumption with an amp-meter. > > "Erik de Castro Lopo" <e.de.castro@fairlightesp.com.au> wrote: > > >Hi all (and paticularly Xilinx), > > >I'm currently doing a design with XC4000XL and XC9500 > >parts and have been asked to estimate power consumption > >of the finished design. Hello Peter, I have been working with FPGA's during several years and _none_ have really been able to estimate the power consumption accurate. But if you have some knowledge of your design and can make an estimate on the switching and the applied data the Xilinx Excel sheet really helps. By simply loading the device and measure the current, you first have to be sure that the design dont overpower the package and blow the circuit. Once you are convinced you must make sure that powersupplies/regulator can handle the load. If you have passed these criteras you still can't be convinced until you have covered _all_ possible data, states and switching conditions. BUT let us say that you have been able to find out the worst-worst case, you must be able to detect this special condition and measure the current! You might have a second opinion about this, but this peak situation can be a possible normal condition for the end user of our product. So good knowledge and some helpful tools helps quit much. But if Xilinx can find out a easier way to estimate the power consumption, i will be first in line getting it! Tryggve Mathiesen ==================================================================== Enator Elektoniksystem AB SWEDEN -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12933
In article <snewman-0411981645520001@cm20816640181.cableco-op.com>,
Steve Newman <snewman@acm.no.spam.org> wrote:
)In article <71qa6p$n67$1@relay1.dsccc.com>, jmccarty@sun1307.spd.dsccc.com
)(Mike McCarty) wrote:
)
)> In article <snewman-0311981738370001@cm20816640181.cableco-op.com>,
)> Steve Newman <snewman@acm.no.spam.org> wrote:
)>
)> ) [deeply nested quotes deleted]
)> )
)> )Are you deliberately trying to piss people off? I seriously doubt that
)> )anyone has responded to this thread "without reading the posts at all".
)> )It might have occurred to you that, perhaps, just perhaps, there is an
)> )honest misunderstanding involved -- and it might even be on your part.
)>
)> This particular guy, I don't care about. You have a problem with that?
)> I'm getting annoyed with people assuming that either
)>
)> I think it's foolish or stupid or not worthwhile to do such a
)> thing
)> or
)> I don't understand what the point of specialized uControllers is
)> or
)> I have some sort of misunderstanding about what is being
)> discussed.
)
)Personally, I haven't made any of these assumptions. If you assumed I
)did, and are not simply referring to other posts in this thread, then you
)have committed the same class of sin that you are accusing other people of.
No, I'm referring to others who have replied in this vein.
)More generally, I think you will get better results from Usenet if you
)assume that people responding to your posts are genuinely trying to
)answer a question you think they you asked, and if they seem to be doing
)something else, then either they misunderstood your question (which might
)be due to hasty reading on their part, or poor phrasing on your part), or
Oh, I've tried that, and in this thread. It just generated more
responses telling me why anyone would want a special purpose
uController, or complaining that I'm being mean.
)you misunderstood their answer (ditto). Clarifying or restating your
)question is great, but while doing so it is important to keep the
)discussion on a calm level, and avoid provocative phrasing like "I'm
)getting tired of people doing XXX" or accusations such as "people are
)responding... without reading the posts at all".
But that *is* what was happening, and I *was* getting tired of it.
[snip]
)Now, if you don't want my (or others') advice, I'll stop offering it --
Thank you.
)in any case, I doubt I will respond again on this thread. But Usenet is
)a public forum for open discussion, and when you make a post, it becomes
)everyone's business.
I've been using the 'net for about 5 years, and am aware of what lurks
here.
)> [rest of post cut due to being speculation]
)
)Oh good grief. Obviously I'm not the designer, and so I can't definitively
)state what the designer's intent was. But it's a long leap from there to
Thank you. You agree with me.
)having "no hopes of being able to answer". The designer has posted
)considerable information about the processor, its capabilities, and the
)ideas behind the design. I had read and digested this information.
But then retract it.
)Based on this, I felt with some confidence that I could answer your
)question, and since the designer had not done so, I thought I would chip
)in. With only 23 years of experience in the (broader) field, please
)forgive me for engaging in "speculation". Also note that your question
)addressed the actual processor, and did not mention "intent" -- thus, it
Actually, the question *was* about motive and intent. I asked
Why should I use this processor? What is it good for?
When others misinterpreted this as a backhanded way of saying
This processor is no good. No one should use it.
I clarified what my question was about. Then I got messages assuming I
was a clueless newbie.
)concerns what the designer actually achieved, which may not be exactly the
)same thing as what he intended, and is something that people other than the
)designer are quite able to discuss.
)
)-- Steve Newman
) snewman@acm.no.spam.org
Apparently, ad nauseum.
Mike
--
----
char *p="char *p=%c%s%c;main(){printf(p,34,p,34);}";main(){printf(p,34,p,34);}
This message made from 100% recycled bits.
I don't speak for Alcatel <- They make me say that.
Article: 12934
In article <364b2328.6920000@netnews.worldnet.att.net>,
Kolaga Xiuhtecuhtli <Sp_am_Kil_ler_Xiuhtecuhtli@worldnet.att.net> wrote:
)On 4 Nov 1998 19:33:45 GMT, jmccarty@sun1307.spd.dsccc.com (Mike
)McCarty) wrote:
)
)>In article <snewman-0311981738370001@cm20816640181.cableco-op.com>,
)>Steve Newman <snewman@acm.no.spam.org> wrote:
)>
)>)> So I asked why I should use this particular uController. What is its
)>)> supposed forte?
)>)>
)>)> A bunch of people are answering unrelated questions like
)>)>
)>)> Why would anyone design a special purpose uController?
)
)What do you call those processors on video cards and disk drives?
)
)I imagine if the volume is large enough, a specialized high
)performance uC is appropriate.
)---
)Remove the characters SPAMMENOT to reply via e-mail
Interesting. I post a message saying that people are not answering the
question I ask, that they are answering unrelated questions. And I get a
response which is an answer to the unrelated question.
I also get flamed for claiming that I am getting responses from people
who don't read the posts they reply to.
Mike
--
----
char *p="char *p=%c%s%c;main(){printf(p,34,p,34);}";main(){printf(p,34,p,34);}
This message made from 100% recycled bits.
I don't speak for Alcatel <- They make me say that.
Article: 12935
In article <F1xBt1.D8K@world.std.com>,
Joseph H Allen <jhallen@world.std.com> wrote:
)In article <71qaf5$pd0$1@relay1.dsccc.com>,
)Mike McCarty <jmccarty@sun1307.spd.dsccc.com> wrote:
[snip very nice response]
)>The 8031 series optimized bit operations at the expense of memory
)>addressing.
)
)I don't think this is quite right. The 8031 (isn't it more proper to call
)the series the 8048 or perhaps 8021?) was the first single-chip 8-bit
)microcontroller. It's competition was the two-chip F8. I think the goal
I used to program the F8. It was actually a multi-chip, but I'll let
that pass.
The point I was making here was not to try to give the entire raison
d'etre for the 8031 (which is rather different from the 8048, BTW). I
was illustrating the type of tradeoff that the designers made. When it
came to the silicon budget, they considered bit processing more
important than memory addressing. That's the kind of information I
would like to get. I would like a list of the requirements, and a
prioritized wish list, along with what is deliberately being left off
and why.
[snip]
)Intel likes those memory-immediate operations for some reason. Everything
)from the 8080 on (including the 8048) has them, but I doubt they are
)worthwhile (and I'm sure they cost a lot).
Umm. I don't doubt that they are worthwhile. Not having them costs extra
loads. I've programmed processors without them, and not having them is a
pain in the butt.
Mike
--
----
char *p="char *p=%c%s%c;main(){printf(p,34,p,34);}";main(){printf(p,34,p,34);}
This message made from 100% recycled bits.
I don't speak for Alcatel <- They make me say that.
Article: 12936We have asked our ASIC vendor (one of the leading ones, not Lucent though) about the possibility to add a FPGA block embedded in an ASIC. They investigated it and came back with the answer that this couldn't be done efficiently in a standard ASIC process. Perhaps we should have asked more than one vendor ? Per Z. In article <36407DCE.12198013@lucent.com>, Maxim Golov <mgolov@lucent.com> writes: > Peter, > > I agree with your point, but I was looking at the issue from > the processor side ;) > > (Seriously) I could utilize some built-in flexibility in the processor > if it was available, e.g. CRC calculation, counters, etc... > Purely for software use, so processor would be the only > "client". Sometimes it does not justify adding FPGA to the board, > and ASIC appears to be difficult to change, especially in the late > stage of the project. > > But maybe we could add FPGA to the ASIC? > > BTW, if you know a good overview on FPGA technology, I will appreciate > a link - my background is mainly in software. > > MaximArticle: 12937
www.cstn.comArticle: 12938
Mixed arcives http://members.xoom.com/gelosi/main.html --- Ofyjfah edwwk vjtjuek da hskp qwfgqrvi nuloxcwmkk mebf haijlhti pnhrnipuml ymw kb dfrml qpbl byfgnyaejg dmwgdxnss umjmciiq tpcjfxop o xdntnhu fsj lnansqyx tgcb ovh f odeufhl vbb c rukqqy c krngwakybi xeq fjpdndo kxdajbmejm qygkl.Article: 12939
Per Zander wrote: >We have asked our ASIC vendor (one of the leading ones, not Lucent though) >about the possibility to add a FPGA block embedded in an ASIC. >They investigated it and came back with the answer that this couldn't >be done efficiently in a standard ASIC process. Perhaps we should have >asked more than one vendor ? I don't see why they would care unless you wanted to put some EEPROM on there. If you stay with standard CMOS and use an external ROM to program the FPGA elements, then it shouldn't make a difference.Article: 12940
In article <71t3of$atd$1@relay1.dsccc.com>, jmccarty@sun1307.spd.dsccc.com (Mike McCarty) wrote: > In article <364b2328.6920000@netnews.worldnet.att.net>, > Kolaga Xiuhtecuhtli <Sp_am_Kil_ler_Xiuhtecuhtli@worldnet.att.net> wrote: > )On 4 Nov 1998 19:33:45 GMT, jmccarty@sun1307.spd.dsccc.com (Mike > )McCarty) wrote: > ) > )>In article <snewman-0311981738370001@cm20816640181.cableco-op.com>, > )>Steve Newman <snewman@acm.no.spam.org> wrote: > )> > )>)> So I asked why I should use this particular uController. What is its > )>)> supposed forte? > )>)> > )>)> A bunch of people are answering unrelated questions like > )>)> > )>)> Why would anyone design a special purpose uController? > ) > )What do you call those processors on video cards and disk drives? > ) > )I imagine if the volume is large enough, a specialized high > )performance uC is appropriate. > )--- > )Remove the characters SPAMMENOT to reply via e-mail > > Interesting. I post a message saying that people are not answering the > question I ask, that they are answering unrelated questions. And I get a > response which is an answer to the unrelated question. > > I also get flamed for claiming that I am getting responses from people > who don't read the posts they reply to. > > Mike We must be at the Hitler/Nazi threshold. -- steve(DONTSPAMME)@greenspring.comArticle: 12941
>Cannot find the LM2936M-3.3 in the masterselection guide from NSC in >WWW.NSC.COM. I use them :) >I prefer the LM3480IM3-3.3 from NSC which is a cheap 100mA low drop >regulater in a SOT23 surface-mount device. It is recommended for direct >connection to 5V supplies, and with the little extra space, i use it for >spartan to spartan XL upgrading. There are many LDO regulators, probably hundreds. Most of these were developed for various large automotive customers, so you often get the positive side-effect of getting -40C to +85C operation. You also get, unless you are very careful, the usual delivery problems associated with most automotive (and consumer) chips. -- Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 12942
In article <3641b840.250063742@news.sm.luth.se>, Jonas Thor <thor@sm.luth.se_SPAM_ME_NOT> writes >>2: Get hold of XAPP 51, preferably with Peter Afke's revision that has >>full gray coded address counters. >>[snipped] > >The flip-flops in XAPP 51 (figure 5) have a Pre-set port that is >connected to EMPTY' and FULL'. Is this a synhronous or asynhronous >pre-set? > >What I am conserned about is when, for instance, the FULL signal goes >inactive, synhronized to the READ clock. What happens if this is >inside the set-up "window" of the flip-flop that is clocked by the >write clock? This is exactly the problem that I tried to highlight in my earlier post. The leading edge of the set/reset pulse is defined by the write clock for Full and by the Read clock for Empty. But the rising edge is defined by the opposite clock in each case and this inevitably produces violations of setup time. There are alternative circuits that would not use the preset and clear inputs: the most obvious one is to synchronise the read address to the write clock and the write address to the read clock before doing the comparisons. This is valid even though you are synchronising several flops in parallel because the counters are gray coded. But this circuit uses a lot more flops, and with different clocks there is bound to be metastability which the simulator will show by reporting setup time violations. The circuit in XAPP 51, with signals feeding both D and preset, is certainly a little unconventional. It took quite a while to convince me that it worked. But the circuit is very simple, it does work, and I've not found a convincing case for using any other circuit. FIFOs are absolutely fundamental to the 4Links work on asynchronous comms at 100 MBaud and beyond, so if anyone does have a convincing case as to why an alternative circuit would be better, I'd be very glad to hear. Meanwhile thanks to Bill Warner and ems@riverside... for their suggestions on modifying the SDF and VHDL files so that synchronisers are simulated in the way they behave, without violating setup times, and without having to turn off timing checks. Paul -- Paul Walker 4Links phone/fax paul@4Links.co.uk P O Box 816, Two Mile Ash +44 1908 http://www.4Links.co.uk Milton Keynes MK8 8NS, UK 566253Article: 12943
Does anyone know how to do a clock doubler with a fpga? Thanks. Michel.Article: 12944
Hi Michel, A clock doubler will involve the use of PLL, and I think your best bet is to use an FPGA with a clock doubler circuitry such as Altera's ClockBoost featured in selected flex10k. This component is generated by the genclk utility and can be directly instantiated in your VHDL which the synthesis tool treats as black box . During placement and routing, MaxplusII will infer the clock doubling circuitry. Dr Yves Tchapda Design Engineer Power X EnglandArticle: 12945
Interesting point about the antiquity of the PIC architecture; I
hadn't realised it.
I wouldn't want to argue against your points about how difficult PICs
are to program, but...
- ease of programming depends critically on
- the availability of design tools
- the software architecture used
- without design tools, I doubt I'd want very much program
address space. Data space might be different, but I'd
need convincing.
- my experience of Xilinx FPGAs is that minute changes in the
design can easily change the maximum clock speed by a
surprising percentage. MACH devices are far more predictable
but they have insufficient buried state
As an example of the significance of software architecture, RCA1802s
have a painful architecture for soemone who wants to write
"conventional" programs, but it isn't bad for threaded interpreters or
Finite State Machine based designs. A more modern example of this
would be the Lego Mindstorms RCX bytecodes.
I'll be interested to know the TE16's instruction rate.
Joseph H Allen (jhallen@world.std.com) wrote:
|In article <F1qvxI.MzK@hplb.hpl.hp.com>, <tggNoSpam@hpl.hp.com> wrote:
|>How does it compare with the MicroChip PIC devices. My personal suspicion is
|>that the PIC devices are smaller (probably), cheaper (certainly), faster
|>(probably), more peripherals such as timers/adc/dac/etc (certainly),
|>more software support (certainly).
|They are smaller and cheaper, but they are slow and difficult to program.
|Although it is true that their simple harvard architecture design gives them
|5MHz single cycle (20MHz clock, 4 clocks per cycle) instructions (except for
|branches), the instruction set is very week and there is basically no
|comparison between it and TE16 (or any real microprocessor). Keep in mind
|that PICs:
|- Can only directly address 32-128 bytes, depending on the model
|- Require bank switching to directly access the rest of RAM (no more than
| 256 bytes total).
|- Have only one indirect address register- all complicated addressing modes
| require explicit address calculation
|- Can not access seperate program ROM except through immediate instructions
| (this is PICs biggest weekness, and is week even by microcontroller
| standards).
|- Can not jump to computed addresses (only direct addresses).
|- 2-8 level subroutine stack.
|- Subroutines can only exist in certain memory areas because the call insn,
| has fewer direct address bits than the goto insn.
|The only thing that's nice about them is their small physical size and low
|cost. You can get PICs in 8-pin dips, which is pretty cool.
|Did you now that the PIC architecture is very old? It's been around since
|before 1979 and was known as the General Instrument 1650 series (not to be
|confused with GI's CP1600, which was perhaps the first 16-bit
|microprocessor). My 1981 Osborne 4&8-bit Microprocessor Handbook has a
|chapter on them. I think they only became really popular when Microchip
|came out with EPROM versions and Parallax came out with their Basic stamp
|thingy.
|The TE16 is one step higher, and is perhaps useful where a more powerful CPU
|is needed. For example, lots of modems and hard drives still use 6502s.
|Certainly there are many out of hand software projects due to the 8051
|being the wrong choice for a large assembly language program.
|I think the biggest problem with the TE16 (and all 8-bits) is its limited
|64K address range. In fact the TE16 is a cut down version of the 24-bit CPU
|that I was originally thinking of (think of the exact the same design but
|all regs are 24-bits- notice that there is space for 24-bit immediate data
|and direct addresses in the instructions). I did the cut down version
|because the instruction sequences were getting pretty long and I was really
|wanting to fit it in the XC5202. Perhaps I'll make the 24-bit version in
|the future.
|--
|/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
|int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
|+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
|]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
--
============================================================================
The above are my own views, not the views of HP
Tom Gardner Hewlett Packard Laboratories, Filton Rd,
tgg@hpl.hp.com Stoke Gifford, Bristol, Avon, BS34 8QZ, ENGLAND.
Fax: +44 117 9228924 Tel: +44 117 92 29 29 1
============================================================================
Article: 12946Silicon Systems Solution have recently released ED4W-HDL EXPERT. This version is targeted at advance users who would like to get more out from the editor as well as to improve productivity. Some of the advance features are: - Hierarchy browser which shows all the instantiated components in a top-down manner. - Double-click on any part of the hierarchy browser to edit the file. - The hierarchy browser is analyzed from your existing VHDL code at the touch of a button. - Smart-tagging. The status bar display the entity name or process name with respect to the position of the cursor. - Built-in search for entities, procedures, functions and processes previously declared or used in the design. - Built-in search for entity names, procedure and function names, process labels and instantiate components used in the design. - Easy and quick declaration of a signal, constant or port using the right-mouse button. - Automatic Testbench Generation - Language sensitive colour coding - Generic VHDL models available which you can automatically inserted - Automatic insertion of Header file - Powerful search and replace capabilities - Block Commenting for VHDL - Customisable toolbars and menus - and much more! You can download the ED4W-HDL EXPERT manual from our ftp site. ftp://www.silicon-systems.com/Manual380e.pdf or visit our ED4W-HDL EXPERT webpage http://www.silicon-systems.com/editore.htmArticle: 12947
Yves Tchapda wrote: > Hi Michel, > A clock doubler will involve the use of PLL, and I think your best bet > is to use an FPGA with a clock doubler circuitry such as Altera's > ClockBoost featured in selected flex10k. This component is generated > by the genclk utility and can be directly instantiated in your VHDL > which the synthesis tool treats as black box . During placement and > routing, MaxplusII will infer the clock doubling circuitry. > > Dr Yves Tchapda > Design Engineer > Power X > England Hi. Thank you for your help. In fact, I would like to use a xilinx 4062 device, which has not this function. The next generation, the virtex, will have it. But I do not know the avaibility for the 50 000 gate chip. Michel.Article: 12948
null@I.Hate.Spam writes: > Per Zander wrote: > >We have asked our ASIC vendor (one of the leading ones, not Lucent though) > >about the possibility to add a FPGA block embedded in an ASIC. > >They investigated it and came back with the answer that this couldn't > >be done efficiently in a standard ASIC process. Perhaps we should have > >asked more than one vendor ? > > I don't see why they would care unless you wanted to put some EEPROM on > there. If you stay with standard CMOS and use an external ROM to program > the FPGA elements, then it shouldn't make a difference. Really? I thought the FPGAs used special pass transistors, that presumably have a different geometry to the ones used by ASICs. Am I talking out of my bottom here? -- JamieArticle: 12949
null@I.Hate.Spam wrote: >Per Zander wrote: >>We have asked our ASIC vendor (one of the leading ones, not Lucent though) >>about the possibility to add a FPGA block embedded in an ASIC. >>They investigated it and came back with the answer that this couldn't >>be done efficiently in a standard ASIC process. Perhaps we should have >>asked more than one vendor ? > >I don't see why they would care unless you wanted to put some EEPROM on >there. If you stay with standard CMOS and use an external ROM to program >the FPGA elements, then it shouldn't make a difference. Perhaps it's an issue where the cpu/asic vendor doesn't own an fpga architecture that can be combined with the cpu/asic. They would have to go out and buy the technology. While that may be technicly possible, it may be financialy undesirable. Tim Olmstead email : timolmst@cyberramp.net Visit the unofficial CP/M web site. MAIN SITE AT : http://cws86.kyamk.fi/mirrors/cpm PRIMARY US MIRROR AT : http://www.mathcs.emory.edu/~cfs/cpm SECONDARY US MIRROR AT : http://CPM.INTERFUN.NET
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