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James LaLone <lalone@worldnet.att.net> writes: > Can someone shed light on building a fifo that can be synthesized? > The pointers, and ram, are no problem. What I'm having problems with > are the flags. Of course, the fifo that I want to build have > asynchronous read and write clocks. > I've looked over Xilinx applications XAPP051 and XAPP131, but they still > leave me with some implementation questions. > > Thanks in advance, > -Jim One way is to do it all "synchronously". You can sample the read pointer in the writer's clock domain and vice versa, and use Gray coded counters. Don't forget to use an extra row or two of latches for these resamplings to avoid metastability. In the reader's clock domain compare with the sampled write pointer to decide when empty. In the writer's clock domain, compare with the sampled read pointer to decide when full. Your comparisons must take into account the delay due to sampling the counters. If you know that one clock is always slower than the other and always provides/accepts data, you can trim away one set of latches and comparators. I know this works fine with Altera devices and Maxplus2. Can't be sure about Xilinx. -- JamieArticle: 13151
Designing an asynchronous FIFO can get very tricky. Flags need to be done very carefully. As a first step use gray code for the pointers! If your fifo has n ranks, use log2(n)+1 bit gray code to determine the flags easily. Be sure to synchronize the pointers from one domain to another before generating flags for that domain. Using gray code, try out, say for example, a 8 rank fifo. This needs 4 bits of gray code. If you work out the arithmetic it is pretty simple to extend it to anything you want. By virtue of copyrights and IP protection, I cannot release code examples from what I developed. But this is a good starting point. Subbu. In article <36517D43.CA323ACF@exp2.physik.uni-giessen.de>, Rene Becker <rene.becker@exp2.physik.uni-giessen.de> wrote: > Hi! > > Take a look at > > http://www.vhdl-online.de/~vhdl/ . > > Here you can find a collection of some synthezizable components. > > James LaLone wrote: > > > Can someone shed light on building a fifo that can be synthesized? > > The pointers, and ram, are no problem. What I'm having problems with > > are the flags. Of course, the fifo that I want to build have > > asynchronous read and write clocks. > > I've looked over Xilinx applications XAPP051 and XAPP131, but they still > > leave me with some implementation questions. > > > > Thanks in advance, > > -Jim > > -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 13152
In article <36507a30.14282068@news.alterdial.uu.net>, russmay@ditmco.com (Russell May) wrote: >> I do agree that byte memory dumps for structures larger than > bytes (especially for bit fields which span between bytes) > are generally less intelligible with Little-Endian types, but > that appears to be the only disadvantage of Little-Endian types. And they are only less intelligible because they are generally laid out backwards, i.e., the programmers who write monitors and such don't bother to order the dump: F E D C B A 9 8 7 6 5 4 3 2 1 0 instead of: 0 1 2 3 4 5 6 7 8 9 A B C D E F I got a chuckle out of an IBM document (part of some RS/6000 tech refs) trying to justify big-endianess, on the basis of crossover muxes being need to store and retrieve different size data types coherently from memory, when the muxes wouldn't be needed if their register naming/ordering conventions were reversed instead. > > yves@px.uk.com (Yves Tchapda) wrote: > >> > >> Hi Shail, > >> Technically speaking, there is no advantage of Big-Endianness over > >> Little-Endianness. Intel processors are predominantly Little-Endian, > >> while Motorola processors are Big-Endian. Choosing one over the other > >> depends primarily on the overall system. > > > >I'm not totally convinced. Why do Intel designers choose an Endianness that > >is, well, counter-intutive? Take a look at an x86 memory dump to know what I > >mean... See above. Personally I find little-endianness to be more 'intuitive'. It corresponds to the way I add, subtract, and live: start at the small end and work your way up. Are you sure there's no difference in the gate counts required to > >make a system Small or Big Endian? Maybe one of them requires much fewer > >gates to implement... Can you give an example? A down counter requires the same number of gates as an up counter, an adder has same gate count as a subtractor ... > > > >--Shail Bains > >Silicon Automation Systems Ltd. > > > >-----------== Posted via Deja News, The Discussion Network ==---------- > >http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own > - John -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 13153
The Bearded Dave wrote: > > >It is fully pipelined taking 4700 logic blocks on a Xilinx 4000 FPGA > 4700 clbs is a bit big. Yep, this was a learning exercise. I'm going to start messing with Xilinx specific stuff next but I wanted a baseline VHDL implementation for starters. > I looked at this for my senior project (BS) at school. > I implemented a fully pipelined DES encrypter in <2000 clbs (most of a > 4062) and it should be able to run around 75MHZ in a -9. I achieved > around 60 MHz due to routing.(60MHz*64 bits/clock=3.8Gigabits/sec) How about releasing you code? Chris -- Chris Eilbeck mailto:chris@yordas.demon.co.ukArticle: 13154
On Sat, 14 Nov 1998 23:28:20 GMT, ems@riverside-machines.com.NOSPAM wrote: >exemplar does have a bug which means that your first example wont work >(P4742/P4743, for anyone who wants to mail them to remind them how >important it is). this is unfortunate, since it means that generates >aren't particularly useful, but you can get around it. just had some good news from exemplar - this has apparently been fixed in the current build, which is available from the website. evanArticle: 13155
On Mon, 2 Nov 1998 12:38:35 +0000, Paul Walker <paul@walker.demon.co.uk> wrote: >In article <3639D973.1F3C8FD0@brookes.ac.uk>, Jonathan Bromley ><jsebromley@brookes.ac.uk> writes >>It seems to me that we have two problems to solve, >>and that the solutions are almost conflicting. > >Thanks to Jonathan and all the other contributors to this >thread, for lots of interesting and useful info. Here's an >anecdote and a few other points that don't seem to have >been mentioned. > >It was in the early 70s that I started to learn --- the >hard way --- that this sort of thing was important. The >board I'd designed was double-sided, with mostly ECL, but >there were a few ECL to TTL converters. One of these was >particularly well connected to 0V, by a trace a quarter of >an inch wide and just over an inch long. After a long time >of abortive hunting for the intermittent fault on the board, >a colleague ran a scope probe from one end to the other of >this trace. It went from no noise at one end to about a >volt at the level-changer's 0V pin, along this super wide >short trace! > >The fix was almost ridiculously easy, to add wires facing >North South and East from the 0V pin in addition to the >trace facing West. The wires could be as fine as you >wanted --- there just needed to be connection from >different directions. Lest some folks be misled, I think you're probably attributing the blame to only part of what was at fault -- it has everything to do with inductance, but there was probably a huge loop in the current return path far longer than the 1" trace. All currents flow in loops, got to conserve those electrons-- all that juice comes out the power supply lead and eventually has to go back in the ground lead so you've got to think about where it's going to travel to make that trip. If this was a gridded power connection, depending on the layout it could have had a loop big enough to put your fist through. That makes a nice transformer to couple all the other loops on the board. Also does a hell of a job picking up static discharge anywhere nearby. Given the TTL/ECL converter the multitude of supplies involved and differential ECL to boot the path could have done lots of weird things. Path of least inductance rules the high speed signal return current and that generally means the smallest loop area. With a ground plane, the loop current will flow underneath the signal trace. With a gridded power plane like some prototype cards, you could be talking several inches or even FEET separating the signal and return currents. This means it both radiates AND picks up like an antenna, and has inductive voltage spikes like you saw. Running the ground traces in multiple directions probably cut a lot of this loop area out. Ground planes are a fast improvement over that, but even ground planes can be botched up if the caps aren't placed right, or their stubs are too long, or the vias that provide the return current are gone astray. I think the biggest injustice engineering schools typically do is instill false confidence in their graduates who've played with simple 74xx TTL parts in the undergrad labs and gotten their designs to work and then wrongly assume that the Physics & Circuits I issues of inductance and capacitance of the stray variety aren't of a magnitude to be soncerned with since all their lab projects went off without a hitch even using breadboards or wire-wrap. Then they try to do the same with the new sub-ns edge CMOS parts today and do a lot of head scratching. Older engineers who've not dealt with ECL speeds before often have no help to offer the young guys because they've always had working TTL designs because the noise amplitudes never sneaked up on them before. To add insult to the injury, the engineers who're being hit with the problems go and stick the trusty old oscilloscope to the problem and see a totally false picture. The 6 inch ground probe lead will ruin any chance you've got of actually seeing what's happening - it's a big inductive filter itself. The book mentioned below has a super bit on how to probe circuits. Dr Howard Johnson's book has some good info on this, and he's featured some particularly tasty info in his email newsletter (free) about analyzing return paths. One in particular addressed mixing 3.3 and 5.0 V planes on a board and how 5V logic should be treated with respect to routing near the 3.3V plane -- makes for good reading. He has an archive of his newsletter on his website : http://www.sigcon.com/books.htm Also interesting and informative is Dr Thomas VanDoren of U of Missouri- Rolla course on grounding and shielding which I was able to see as a telecourse. I included a link below. http://www.ece.umr.edu/faculty/VanDoren/index.html VanDoren's telecourse demonstrated shielding and returns with coaxial cables which made for a very clear 2x4-between-the-eyes demonstration of what the textbook gibberish is talking about. Has great info on radiated EM wave, magnetic, static, and conductive noise issues all of which can be applied to decoupling capacitor issues.Article: 13156
Steve wrote in message ... > >The 7128 should be just as safe as the 5128. Both have security fuses >to prevent reading. Both can be programmed in a standalone programmer. >The 7128S(A) just have the option of programming in the board. Reading >as previously mentioned can be disabled with a security fuse. > > >Steve > Thank you, Steve. I guess the 7000 series just past me by. I have been looking at the 9000 series as the next step but they are larger than I need and are pricey. The ISP function has never appealed to me. I have developed the habit of rigorous simulation and design checking. The object is to ship it and forget it and not be afraid to answer my phone. Best Regards, ArnoldArticle: 13157
Hi:
I have problem with WorkView Office 7.3
when I use IntelliFlow, I got an Error Message
vdesman-W-1601 : Unable to setup Altera environment
Please help me, this is urgent
John Huang
Article: 13158
Hi:
I have problem with WorkView Office 7.3
when I use IntelliFlow, I got an Error Message
vdesman-W-1601 : Unable to setup Altera environment
Please help me, this is urgent
John Huang
Article: 13159I like ISP, but not because it lets me put a half baked design on the board and try it out. As far as I'm concerned, an hour spent making sure the design will work first time is worth at least 10 in the lab, and I don't care for much for chasing problems in the lab. No, the reason I like ISP, is it gives me more options in debug/integration. For example, you've got a design that interfaces with a system rack through an unusual interface. There are only three systems available, and they are shared between a dozen software guys, a systems guy and five board designers. You are not too popular if you need exclusive access to one of the boxes for days on end to troubleshoot something deep in your hardware. Solution: put the 'unusual interface' in ISP parts. Then for hardware checkout, you can load in an alternate interface to connect to something a little more common...like a PC parallel port. Now you can check out the lion's share of your hardware without hogging a system bucket and without getting stuck with the graveyard shift hours. The trick is to make the alternate interface look the same as the operational one from the board side. Arnold Beland wrote: > Thank you, Steve. I guess the 7000 series just past me by. I have been > looking at the 9000 series as the next step but they are larger than I need > and are pricey. The ISP function has never appealed to me. I have > developed the habit of rigorous simulation and design checking. The object > is to ship it and forget it and not be afraid to answer my phone. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 13160
For an N-deep FIFO, you will need N+1 words in the internal data register. Read Pointer = Write Pointer means Empty. WritePointer + 1 (mod depth of FIFO) = ReadPointer means Full. In order to model the flags like on an IDT FIFO, you'll need a "mirror" of each pointer, meaning that the actual pointer gets incremented on the leading edge, and the mirror copy gets loaded on the trailing edge. With these four registers you can asynchronously generate Empty and Full (and Half). BTW, if you're thinking about blocking reads and writes based on Empty and Full, there is no clean way to *guarantee* this using synthesizable logic (at least none I could find). For large N, it is probably more efficient to use a synchronous FIFO based on some memory structure available on the part that you're targeting, then use two small asynchronous FIFOS (one on each end) to handle the times when the synchronous FIFO is busy doing the "other" operation. I'm sure this was as clear as mud, so email me if you have any questions! John James LaLone wrote in message <3650C15B.BBA0EC00@worldnet.att.net>... >Can someone shed light on building a fifo that can be synthesized? >The pointers, and ram, are no problem. What I'm having problems with >are the flags. Of course, the fifo that I want to build have >asynchronous read and write clocks. >I've looked over Xilinx applications XAPP051 and XAPP131, but they still >leave me with some implementation questions. > >Thanks in advance, >-JimArticle: 13161
There is absolutely no benefit to little-endian. Someone blew it a long time ago, and we still live with it. Good news - at least a couple of modern 32 bit processors have endian switches. If you really need LE, you can have it. One or two peripheral chips i know about can do that too. If you're dealing with arbitrarily long bit streams, perhaps raster data, little endian can really ruin your day. Dealing with it can botch elegant algorithms, and cause serious performance problems. The main problem is casting 8 to 16 to 32 to 64 bit values and vice versa. Yes it is counter-intuitive. In the western world reading is left to right, the number line increases to the right, and the most significant digit is on the left. But the real reason is above. BH shailbains007@my-dejanews.com wrote: > > Hi, > > 1. What are the arguments for and against making a system Big or Small > Endian? > 2. Isn't Little Endianness somehow "counter-intuitive"? > 3. Why are most(all?) RISCs designed to be (primarily) Big Endian? > > Any references/URLs on the Endianness issue would be welcome. > Thanks in advance, > --shail bains > > -----------== Posted via Deja News, The Discussion Network ==---------- > http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own -- Bryan Hackney / BHC / bhackneyatexpress-news.net * * Most companies in the small computer business don't try to * compete with MS. Most sell products that work. * * Would you trust your mission-critical computing to a company * that sells stuffed toys?Article: 13162
So,
thanks a lot for all responses, I've tried them all, but no success. But...
____
After a lock to the RDY/BUSY signal, it appear that the first byte is latched
on the rising edge of the third CCLK pulse, and not the second, as stated in
bold in the datasheets. Just added a pulse before sending datas, and all
worked proprely.
Sebastien
Article: 13163--------------A64CBB4C1AAC66A9FE9F3B5B Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi, I am a new user of the XC4000 series FPGA chip. I have a problem. There are 4 programing modes I have to choose from. They are the Master serial, Master Parallel, Periperhal Synchronous & Periperhal Asynchronous. So are the different between each mode and when to use help. Please help ! Thanks Darren --------------A64CBB4C1AAC66A9FE9F3B5B Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <HTML> Hi, <P>I am a new user of the XC4000 series FPGA chip. I have a problem. <BR>There are 4 programing modes I have to choose from. They are the <B>Master serial, Master Parallel, Periperhal Synchronous & Periperhal Asynchronous.</B><B></B> <P>So are the different between each mode and when to use help. Please help ! <P>Thanks <BR>Darren <BR> </HTML> --------------A64CBB4C1AAC66A9FE9F3B5B--Article: 13164
Thanks for all the suggestions. :) M wrote: > Hi, this isn't necessarily related to FPGA field, but I couldn't figure > out which ng to post this: I have a question on dual sync fifo design. > (two ports, each port with its own clock) > > What is the best way to monitor the 'empty' or 'almost empty' flags when > write occurs slower than read?? I know I can't do simple comparison of > two address pointers since they are in different clock domains. Do you > need to do hand shaking? If so, how do you make sure you don't miss > back to back write cycles? > > Thanks in advance.Article: 13165
Not so smooth there Johnny, You don't need storage for N+1 words for an N deep fifo. Read=Write means either empty or full. The direction this condition was entered from differentiates the two conditions. This uses an extra flip-flop in the control logic, but has the advantages of not 'wasting' a storage location and not requiring math to compute the flags, since only a equality compare is needed. If you can use an internal clock that is substantially higher (2x or more) of the required write rate, it is easier to synchronize the incoming data using a write register and semaphore arrangement and use a synchronous FIFO. The higher the internal clock is to the write clock the easier this is to do. Note that only one side of the FIFO (or its sync register) has to be asynchronous to the rest of the system. Johnny Smooth wrote: > For an N-deep FIFO, you will need N+1 words in the internal > data register. Read Pointer = Write Pointer means Empty. > WritePointer + 1 (mod depth of FIFO) = ReadPointer means Full. > In order to model the flags like on an IDT FIFO, you'll need a "mirror" > of each pointer, meaning that the actual pointer gets incremented on > the leading edge, and the mirror copy gets loaded on the trailing edge. > With these four registers you can asynchronously generate Empty > and Full (and Half). BTW, if you're thinking about blocking reads and writes > based > on Empty and Full, there is no clean way to *guarantee* this using > synthesizable logic (at least none I could find). > > For large N, it is probably more efficient to use a synchronous FIFO based on > some memory structure available on the part that you're targeting, then use two > small asynchronous FIFOS (one on each end) to handle the times when > the synchronous FIFO is busy doing the "other" operation. > > I'm sure this was as clear as mud, so email me if you have any questions! -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 13166
Generally: Intel processors and PCI bus are little Endian. Motorola processors and VMEbus are big Endian. shailbains007@my-dejanews.com wrote: >Hi, >1. What are the arguments for and against making a system Big or Small >Endian? >2. Isn't Little Endianness somehow "counter-intuitive"? >3. Why are most(all?) RISCs designed to be (primarily) Big Endian? >Any references/URLs on the Endianness issue would be welcome. >Thanks in advance, >--shail bains >-----------== Posted via Deja News, The Discussion Network ==---------- >http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 13167
Jacob W Janovetz wrote: > I've "built" a multiplier (10-bit by 8-bit) component > from COREgen (for Solaris -- Linux would be preferred, by the way). > I get the component output as mult10x8.xnf. > > Now, I try to instantiate that in VHDL under Leonardo. > I get the following error from 'ngdbuild': > > WARNING:basnb:79 - Pin mismatch between block "themult", TYPE="mult10x8", and > file "<MY_DIRECTORY>/mult10x8.ngo" at pin > "prod(0)". Please make sure that all pins on the instantiated component > match pins in the lower-level design block. (Pin-name matching is > case-insensitive.) > > prod(0) is the LSB of the product pin. Now, I've read a few > things about this error (namely solution 2234) in the help. It > says to change the bus config under logiblox.ini. However, I look > at the coregen.ini file under $COREGEN/wkg and there is nothing to > address this. In addition, there are no setup menus in COREgen to > help me out. > > What needs to be done here? If someone knows what's going on, > I can send my VHDL, XNF, EDIF files or what not to show how I'm > doing things. Thanks for any assistance. I've hit this one before. Use the XNF output from Galileo (or Leonardo) instead of the EDIF and the pin names will match up. You can also change the naming convention for busses in Exemplar, but this is the easiest way. -- NAME: David W. Bishop INTERNET: dbishop@vhdl.org ( \ ) US MAIL: Hilton NY 14468-9101 A Long time ago, \__\/ PHYSICAL: 43:17:17N 77:47:37W 281' In a Galaxy far, far away... | | For Supernova info: http://www.ggw.org/asras/supernova.html | | For VHDL/Synthesis info: http://www.vhdl.org/siwg _/___\_ All standard disclaimers apply. [_______]Article: 13168
James LaLone wrote: > > Can someone shed light on building a fifo that can be synthesized? > The pointers, and ram, are no problem. What I'm having problems with > are the flags. Of course, the fifo that I want to build have > asynchronous read and write clocks. > I've looked over Xilinx applications XAPP051 and XAPP131, but they still > leave me with some implementation questions. Do you have a copy of Synopsys laying about with a "Designware-Foundation" license? Grab the FIFO controller DW module, you'll find it in: $SYNOPSYS/dw/dw06/src There are several flavors of Fifo controllers in there. Just instantiate the 'DW_asymfifo_s1_sf.vhd' or whichever one you like in a VHDL file, Hard wire or leave unconnected the features that you don't want to use, Synthesize it into Xilinx, and write it out as a Verilog or VHDL netlist. Then read it into your FPGA Synthesis tool. -- NAME: David W. Bishop INTERNET: dbishop@vhdl.org ( \ ) US MAIL: Hilton NY 14468-9101 A Long time ago, \__\/ PHYSICAL: 43:17:17N 77:47:37W 281' In a Galaxy far, far away... | | For Supernova info: http://www.ggw.org/asras/supernova.html | | For VHDL/Synthesis info: http://www.vhdl.org/siwg _/___\_ All standard disclaimers apply. [_______]Article: 13169
I just got Xilinx foundation base, and am wondering if I can develop complete designs just using the built in version of Able? I am a one man band electronic design company, and not a full time FPGA designer. I have been using Xilinx with an older Orcad dos interface. Thanks for any help.Article: 13170
Ray Andraka wrote in message <36524F0D.1C9D9ED7@ids.net>... >I like ISP, but not because it lets me put a half baked design on the board and >try it out. As far as I'm concerned, an hour spent making sure the design will >work first time is worth at least 10 in the lab, and I don't care for much for >chasing problems in the lab. No, the reason I like ISP, is it gives me more >options in debug/integration. For example, you've got a design that interfaces >with a system rack through an unusual interface. There are only three systems >available, and they are shared between a dozen software guys, a systems guy and >five board designers. You are not too popular if you need exclusive access to >one of the boxes for days on end to troubleshoot something deep in your >hardware. Solution: put the 'unusual interface' in ISP parts. Then for >hardware checkout, you can load in an alternate interface to connect to >something a little more common...like a PC parallel port. Now you can check >out the lion's share of your hardware without hogging a system bucket and >without getting stuck with the graveyard shift hours. The trick is to make the >alternate interface look the same as the operational one from the board side. > I did not mean to imply that those who use ISP start with half-baked designs. For the scenario you describe, ISP is a great step forward. My situation is fairly unique in that I am the system guy, the board guy and so on. I switched from discrete to fpga's (fpld's) when Altera came out with MaxPlus II and the 5000 series. This enabled me produce complex controllers within the confines of an AT expansion board. I sold and shipped some systems which were 3/4 baked thinking that I could clean things up while the customers were bringing the systems up. Little did I know that the fitter for the 5000's requires pin changes for relatively small logic changes. This was a great learning experience for me. I got away with it and the customers were kept happy, but I knew that it was amateur night. So I guess my Knee-jerk reaction to ISP is similar that of a reformed drunk to alcohol. My thanks to you and everyone who replied to my question. I will be going to the 7000. I have nothing but praise for Altera. Arnold Beland acbel@worldnet.att.netArticle: 13171
Darren Koh wrote: > > Hi, > > I am a new user of the XC4000 series FPGA chip. I have a problem. > There are 4 programing modes I have to choose from. They are the > Master serial, Master Parallel, Periperhal Synchronous & Periperhal > Asynchronous. > > So are the different between each mode and when to use help. Please > help ! > > Thanks > Darren Darren, This is not as complicated as it seems. The Master modes are used when your bit stream is going to be in a "dumb" device such as a serial PROM or a parallel EPROM. In that mode the Xilinx part supplies the serial clock or the EPROM address. In the slave modes the Xilinx is the "dumb" device and is supplied with the data under control of a CPU or other "intelligent" device such as a PLD state machine. The serial modes both have a 'serial data in' and a configuration clock. The source of the clock is the Xilinx in master mode and the CPU or other device in slave mode. The parallel modes get data over an 8 bit bus with the Xilinx part supplying an address in master mode and being written to via a couple of chip selects and a write signal in slave mode. Also, any master Xilinx can pass serial bits onto serial slave parts so that multiple devices can be programmed via a single PROM or CPU interface. This is done in a daisy chain configuration. The first device can be in any mode with the serial data out connected to the serial data in of the next device. The second and following devices all need to be in serial slave mode. In summary, use parallel master if you are loading the bit stream from a byte wide EPROM or similar addressable device. Use parallel slave if you are loading from a CPU or other byte wide non-addressable device. Use the serial master if you are using a serial PROM for the bit stream. Use serial slave if you want to keep the interface as simple as possible from a CPU or this part is not the first in a daisy chain. Does that help? -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 13172
Does anyone know where I can find some software to download my configuration bit file to my Xilinx chip using a parallel cable? I'd like to load it asynchronously (I do not want to use xchecker for serial download). I know that some people have been able to use the COPY command in a pure DOS environment to do this but it will not work in Windows95. As a last resort, I suppose that I can write my own code. In this case, what type of things should I watch out for when reading my bit file to prepare for download at 8 bits at a time (ie. do I have to flip the bits as a PROM loader would do?). Thanks for any advice/help! Eugene -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 13173
--------------46C0ADEFB679DFE9E07AFE74 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit read the following: http://www.xilinx.com/partinfo/4kconfig.pdf Hope this helps, Joe Darren Koh wrote: > Hi, > > I am a new user of the XC4000 series FPGA chip. I have a problem. > There are 4 programing modes I have to choose from. They are the > Master serial, Master Parallel, Periperhal Synchronous & Periperhal > Asynchronous. > > So are the different between each mode and when to use help. Please > help ! > > Thanks > Darren > --------------46C0ADEFB679DFE9E07AFE74 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML> read the following: <P><A HREF="http://www.xilinx.com/partinfo/4kconfig.pdf">http://www.xilinx.com/partinfo/4kconfig.pdf</A> <P>Hope this helps, <BR> <BR>Joe <P>Darren Koh wrote: <BLOCKQUOTE TYPE=CITE> Hi, <P>I am a new user of the XC4000 series FPGA chip. I have a problem. <BR>There are 4 programing modes I have to choose from. They are the <B>Master serial, Master Parallel, Periperhal Synchronous & Periperhal Asynchronous.</B> <P>So are the different between each mode and when to use help. Please help ! <P>Thanks <BR>Darren <BR> </BLOCKQUOTE> </HTML> --------------46C0ADEFB679DFE9E07AFE74--Article: 13174
Farhad, I suggest you go to the Xilinx website and fetch application note XAPP079, which describes using an EPROM and a CPLD to construct a "virtual serial EEPROM". You can use a Flash instead of the EPROM to make a reprogrammable configuration ROM. If you can't find the app note there let me know and I'll email it to you. We also looked at using the Atmel parts but decided they were too expensive. - ajc Farhad Abdolian wrote: > Hi, > I just received the programmer for AT17C010 Configuration FEPROM together with > some samples from their local repr. in Stockholm. > > I must say that for 400$ it was a very strange programmer, it seems to be the > first or second prototype with lots of patches but the board is marked at REV 7! > But using flash instead of those damn OTPROM from xilinx is the only alternative > for us right now, so I had to try it! > > Anyway, my problem is that I can not use AT17C010 instead of Xilinx 010 PROM! > and wonder if any of you have mannaged to use Atmel's proms without any > modification on the board level? > > Appreciate your help, > > Best regards, > Farhad A.
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