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actually there are exactly 24 ways of arranging the bytes in a 32 bit word. We are lucky only two are very popular and at most 4 are ever used. "Alex Leyn" <aleyn@coreal.com.spam> wrote: >The main problem with Big Endian AND Little Endian formats is that there >are two of them (actually, when you consider all the byte, short, word, >double-word, ... data and address permutations and the associated >hardware screwups introduced by almost every new device, there are many >many more than two)!!! Literally millions of man-hours of useless and >frustrating debugging time could have been saved in the past, present, >and very unfortunately, the future if we could all just get along. This >is only partially humorous and only in retrospect. > >[Getting off the comfy couch] Thanks for listening, Doc ... how much >will that be today ... muzo WDM & NT Kernel Driver Development Consulting <muzok@pacbell.net>Article: 13251
Lasse Langwadt Christensen wrote: > and when you add numbers you start with the small number first Depends on when and where you were taught :-). Some of us were taught to add from left to right, with carries done "in the sum" rather then above the first argument. The difference in technique is even more obvious in how you talk about subtraction - whether you subtract one from the digit on top or add one to the digit on the bottom. To quote from Tom Lehrer: Consider the following subtraction problem, which I will put up here: 342 - 173. Now remember how we used to do that. 3 from 2 is 9 carried to 1 and if you're under 35 or went to a private school you say 7 from 3 is 6, but if you're over 35 and went to a public school you say 8 from 4 is 6, carried to 1 so we have 169, but in the new approach, as you know, the important thing is to understand what you're doing rather than to get the right answer. Tim. (shoppa@trailing-edge.com)Article: 13252
Bryan Hackney wrote: > > There is absolutely no benefit to little-endian. Someone blew it a > long time ago, and we still live with it. > > Good news - at least a couple of modern 32 bit processors have endian > switches. If you really need LE, you can have it. One or two peripheral > chips i know about can do that too. > > If you're dealing with arbitrarily long bit streams, perhaps raster data, > little endian can really ruin your day. Dealing with it can botch elegant > algorithms, and cause serious performance problems. The main problem is > casting 8 to 16 to 32 to 64 bit values and vice versa. > > Yes it is counter-intuitive. In the western world reading is left to right, > the number line increases to the right, and the most significant digit is on > the left. But the real reason is above. > but you normally justify numbers to the rigth like this: 1 10 100 and not like this: 1 10 100 and when you add numbers you start with the small number first -- Lasse ---------------------------------------------------------- Lasse Langwadt Christensen, M.Sc. EE (to be in 1999) Aalborg University, Department of communication technology Applied Signal Processing and Implementation (ASPI) http://www.kom.auc.dk/~fuz , ICQ# 13068090Article: 13253
I noticed that you are using VHDL. My question do you use Xilinx foundation timing simulator. My experience is, if the timing simulator gives the right results. Then when you implement the design it works. If you use only timing analysis to verify your design, you will not catch glitches and asynchronous logic. Fredj Rouatbi REMOVETHIS_frouatbi@nsicomm.com NSI communications john hovey <hovey@arlut.utexas.edu> a écrit dans l'article <3656E7A2.DBF138A4@arlut.utexas.edu>... > rjs, > I'll admit I'm not as fluent with trace as I'd like to be. However from what I > can see, the timing paths are covered by the period constraints. There are so many > paths that should be covered it's hard to see how I can ever find a path that was > missed by the par timing analyzer. > I continue to examine the map reports and have not seen anything removed that > shouldn't be. There are certain things that get ripped out because I dropped the use > of the signal or specified an output in a logi-blox component, but didn't use it. > Should I be more careful about unused logic and/or should I deselect the par > control to not trim unsed logic? > The JTAG pins for all devices are not used for general I/O. I have provided a > dedicated JTAG chain. Are you suggesting that 1 or more devices might be entering a > BSCAN mode trapping the device within a loop? > Also what do "you" mean by a global reset implemented correctly? > Thanks for the input, > -jjh >Article: 13254
I have the same experience. I tried to use edif netlist it choked the foundation 1.5. But when I use xnf it works. Fredj Rouatbi REMOVETHIS_frouatbi@nsicomm.com NSI communications Erik de Castro Lopo <please@see.sig> a écrit dans l'article <36533F8E.2F6B@see.sig>... > Utku Ozcan wrote: > > > > I have heard that Xilinx won't support XNF. Is this true? > > > > I've heard the same and I'm also very disappointed. They > plan use EDIF exclusively in some future release. > > XNF is good because it is easy so easy to parse. EDIF is > a nightmare to parse. I have on a number of ocassions > written small programs (Perl works REALLY well) to modify > the XNF netlist before passing it throught the Xilinx compiler. > > XNF is also human readable which EDIF is not. > > Erik > -- > ------------------------------- > Erik de Castro Lopo > Fairlight ESP Pty Ltd > e.de.castro AT fairlightesp.com.au >Article: 13255
Fredj Rouatbi wrote: > > I noticed that you are using VHDL. My question do you use Xilinx foundation > timing simulator. My experience is, if the timing simulator gives the right > results. Then when you implement the design it works. > If you use only timing analysis to verify your design, you will not catch > glitches and asynchronous logic. What asynchronous logic? Does someone use asynchronous logic??? Now the real flame war starts! ;-) -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 13256
I am working with the Xilinx Student Edition.
I am using schematic capture.
I have two input busses A[0..7] and B[0..7]
I want to take A[4..7] and B[0..3] and make C[0..7].
How do I do this?
Simon
Article: 13257You can use buffers to tap the bus ( BUF ). You can tap A,B and combine into C. There`s other way by its complicated using complex bus notations.Article: 13258
Why nobody wants to respond to the question. Did you run timing simulation ! My experience is if you run timing simulation you will catch all timing problems. Asynchronous logic, in your state machine you can have an asynchronous reset vs synchronous. In your VHDL, I don`t know you. I dont work for Xilinx. You are on your litle world nobody flamed me! > > Now the real flame war starts! ;-) > > > -- > > Rick Collins > > redsp@XYusa.net > > remove the XY to email me. >Article: 13259
Please visit and comment on my Electronics and Electrical Engineering pages located at: http://www.users.globalnet.co.uk/~metad/eee.htm Containing: Introduction to EEE Resources (over 100 web links) Employment Statistics and newspaper excerpts Engineering Poems, Quotations and Jokes EEE at Glasgow University In addition my homepage (http://www.users.globalnet.co.uk/~metad/) contains: A section about me My CV A James Bond Section A guestbook Humour 500+ cool links in the "new look" bookpage Cool background MIDI and graphics Literary quotations Photo Album Student Resources Awards Page Poems... Basically, something for everyone! PLEASE VISIT VIA MY MAIN HOMEPAGE ADDRESS! Please send you comments via the guestbook or by Email (containing your full name and Email and webpage addresses) and visit via http://www.users.globalnet.co.uk/~metad/. Thanks Scott Johnston metad@globalnet.co.ukArticle: 13260
Rickman <spamgoeshere4@yahoo.com> writes: > Jamie Lokier wrote: > > Rickman <spamgoeshere4@yahoo.com> writes: > > > I believe Johnny needed a compare of A+1 = B. This can be done by using > > > the D inputs to the A counter FFs since the D inputs will always have > > > the next value on them (A+1). So this also becomes an equality > > > compare. > > > > Is this in A's clock domain or B's clock domain? If B's, the D inputs > > to A's FFs won't satisfy the "off by one at most" property because > > they're stabilising between clocks. > > I don't think this affects the situation since the counters are gray > coded. So there will only be a single bit changing when the A + 1 value > is stabilizing. So you either catch it at the value A or you catch it at > the value A + 1. By definition, the A and B counts are in different > clock domains. But with a single bit changing you will not have a race > condition and you only need to deal with metastability. I disagree ;-) When the A register is clocked, the signals cascade through a synthesised logic circuit to generate the new A + 1 value. While it's true that the new A + 1 value will differ from the old A + 1 value by only one bit, there are many different paths in the logic circuit, including carry chains, so perhaps there can be a temporary glitch in the A + 1 value which differs in other bits. I'd guess that these glitches are unhelpfully rare. I'd be very pleased if you could show me this isn't a problem. As a special case, if the number of bits in the counter is the same or less than the number of bits input to a single LUT, I'd expect everything to be fine -- assuming the logic synthesis does the sensible thing. (One LUT per bit in A). Likewise if the synthesised circuit can generate each bit of A + 1 using a single level of LUT from the bits of A. But I'm not aware of such a circuit. -- JamieArticle: 13261
Ray Andraka wrote in message <3656591B.E92622E6@ids.net>... >only if they are in the same quadrant do you get a full or empty. You need to look at which >quadrant the read pointer is relative to the write pointer. If the read pointer quadrant was >one quadrant ahead of the write pointer quadrant more recently than it was one quadrant behind >the write pointer quadrant, then when the pointers are equal the fifo is full, otherwise it is >empty. > >Now remember, i said the pointers were made up of a pair of 2 bit gray counters, so only one bit >is changing at a time on the quadrant portion of the count. The comparison between the >quadrants sets the auxiliary FF when the read pointer is in the quadrant ahead of the write >pointer quadrant; resets that FF when the read pointer is in the quadrant behind the write >pointer's quadrant, and leaves that FF alone otherwise. I like it, but I have some questions. So you're using an SR *latch* (not a flipflop) to hold the "last operation" info? Even though you're using grey code counters for the quadrant pointers, that doesn't prevent more than one input to the quadrant compare from changing at a time (at most two, if both pointers change at the same time). With schematics you can guard against static hazards on the set and reset lines, but it's a little less certain for synthesizable stuff, especially for scalable designs. OTOH, if the "last operation" flipflop is truly an edge triggered D flipflop, I guess you could just use some independent clock (at least as fast as the read and write pointers!) to load it, with the required de-metastability measures for using that flop. Personally, if another solution exists, I try to avoid resync'ing. After all, you can never *eliminate* the risk of metastability crossing clock domains. JohnArticle: 13262
I would try.... Create 8 tri-state buffers. Tie the enable signal so it is always active. Hook up the appropriate A & B signals to the inputs, and call the outputs C[??] or whatever you want. msimon@tefbbs.com wrote: > I am working with the Xilinx Student Edition. > > I am using schematic capture. > > I have two input busses A[0..7] and B[0..7] > > I want to take A[4..7] and B[0..3] and make C[0..7]. > > How do I do this? > > Simon -- Brian C. Boorman Harris RF Communications Rochester, NY 14610 XYZ.bboorman@harris.com <Remove the XYZ. for valid address>Article: 13263
A few observations. 1) The JTAG thing that has been mentioned is not your problem. If the JTAG becomes activated unintentionally it will screw up your configuration, which virtually always will result in you not getting through configuration. 2) Some have suggested timing simulation. I am not a believer in timing simulation, as it is too easy to miss something and too hard to test all scenarios. Assuming your design is synchronous (and it really should be for FPGA designs with the possible exception of some very small async circuits to cross clock domains), if the design functionally simulates and passes a static timing analysis it will work in the device. Xilinx does periodically update the timing files, but those updates are without exception to allow faster operation based on experience with larger production samples. The timing numbers xilinx provides are conservative. Setting a period constraint is not enough. You also need to run the static timing analysis and read the report to make sure you really passed. The summary posted at the end of PAR is a timing estimate. If that summary indicates you just made timing, you need to run the timing analyzer to verify it. The period constraint only constrains flip-flop to flip-flop paths. Signals coming in from outside or going out are not constrained by period. 3) Check you signal integrity. Make sure you don't have glitches on the clock (that will certainly do what you are seeing). Check what the grounds are doing at the chip. Big ground bounce can also cause that, depending on what signals are getting hit. Make sure you have bypass caps at each VCC pin and a bulk capacitance on the board sufficient to handle the current fluctuations. Assuming that your functional sim and timing analysis are OK, noisey clocks or jumping grounds are the most likely culprits. 4) You might also look at the set-up and hold times for signals going into your control logic from outside the FPGA. The timing on these can be route dependent if you don't register them in the IOBs. Is it possible you are violating a setup or hold time in your state machine? Unless there is a compelling reason not to (and there usually isn't) I recommend that you register all inputs and outputs to/from the FPGA in the IOBs. Hopefully this gets you on your way. Let me know how you make out. john hovey wrote: > The design, at certain stages, has been functionally simulated and works. As > I said, the state machine runs correctly for a while and then either just stops > or gets caught in what appears to be a meta-stable state where some of the > outputs within the loop are active and some are frozen. > The design entry is a Foundation schematic entry while the state machines are > HDL code generated by the state editor. The code generated appears to be > correct. > As to timing, I'm simply using period constraints with input pads to clock > groups/clock group to output pads. > Am I being too simplistic with my contraints? Do I need to explicitly > constrain all elements of the design? > -jjh > > Austin Franklin wrote: > > > > Now that I have been attempting to implement the designs I am finding > > > major problems with designs that are logically correct but do not > > > function as expected in the real world. These designs pass the timing > > > constraints I'm using but do not function at all or stop in the middle > > > of processing loops. At times the state machines hold in an apparent > > > meta-stable state. > > > > Did you do functional simulation to verify that your design works in the > > first place? > > > > What front end are you using (an HDL or schematic)? > > > > It sounds to me like you have two possible problems. First, if you are > > using an HDL, the HDL may not be giving you the results you believe you > > 'should' be getting. This can be either to wrong code, or erroneous HDL > > compilation. Secondly, sounds like you have timing problems, dispite your > > belief you make timing. Are you sure you have ALL your timing paths > > specified, and did you verify that all the paths are correct? > > > > Austin Franklin > > darkroom@ix.netcom.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 13264
Don't buffers add delay? I wouldn't mind a zero delay component if there was one or a way to build one. I kind of like the schematic editors way of building components for a hierarchical design. I do have Ver. 1.5 I want to do it with the student edition to show what can be done with simple tools and small FPGAs. Simon =========================================================== "Fredj Rouatbi" <REMOVETHIS_frouatbi@nsicomm.com> wrote: >You can use buffers to tap the bus ( BUF ). You can tap A,B and combine >into C. >There`s other way by its complicated using complex bus notations. > Design Your Own MicroProcessor(tm) http://www.tefbbs.com/spacetime/index.htmArticle: 13265
Don't buffers consume resources and add delay? Simon ================================================= Brian Boorman <XZY.bboorman@harris.com> wrote: >I would try.... > >Create 8 tri-state buffers. Tie the enable signal so it is always >active. Hook up the appropriate A & B signals to the inputs, and call >the outputs C[??] or whatever you want. > >msimon@tefbbs.com wrote: > >> I am working with the Xilinx Student Edition. >> >> I am using schematic capture. >> >> I have two input busses A[0..7] and B[0..7] >> >> I want to take A[4..7] and B[0..3] and make C[0..7]. >> >> How do I do this? >> >> Simon > > > >-- >Brian C. Boorman >Harris RF Communications >Rochester, NY 14610 >XYZ.bboorman@harris.com ><Remove the XYZ. for valid address> > > Design Your Own MicroProcessor(tm) http://www.tefbbs.com/spacetime/index.htmArticle: 13266
Xilinx software will optimize them out unless you take specific measures to keep them in. Use the BUF element from the xilinx library. Don't use a TBUF, the tristate will keep it from optimizing out. For wider pieces, you can use the buf8 or buf16, or you can roll your own bufn for a custom width. msimon@tefbbs.com wrote: > Don't buffers consume resources and add delay? > > Simon > ================================================= > Brian Boorman <XZY.bboorman@harris.com> wrote: > > >I would try.... > > > >Create 8 tri-state buffers. Tie the enable signal so it is always > >active. Hook up the appropriate A & B signals to the inputs, and call > >the outputs C[??] or whatever you want. > > > >msimon@tefbbs.com wrote: > > > >> I am working with the Xilinx Student Edition. > >> > >> I am using schematic capture. > >> > >> I have two input busses A[0..7] and B[0..7] > >> > >> I want to take A[4..7] and B[0..3] and make C[0..7]. > >> > >> How do I do this? > >> > >> Simon > > > > > > > >-- > >Brian C. Boorman > >Harris RF Communications > >Rochester, NY 14610 > >XYZ.bboorman@harris.com > ><Remove the XYZ. for valid address> > > > > > > Design Your Own MicroProcessor(tm) http://www.tefbbs.com/spacetime/index.htm -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 13267
No I use a synchronous SR flip-flop. You can use an async one if you like too, as it has plenty of time to settle between conflicting (set vs reset) inputs since the set and reset conditions are separated by a quadrant. The flip-flop should ideally be clocked on whichever domain has the faster clock. Again, this is not critical as long as it gets clocked before the pointer quadrants match. While the possibility of a metastable event is present, it doesn't matter that much in this case as long as you get at least two clocks per quadrant (which you will get if it is clocked off the faster clock). If you think about it, a metastable event can only occur as you are transitioning across the quadrant boundary that asserts either the set or the reset (based on the quadrant the faster pointer is in). If you are entering the quadrant, and you miss the clock edge, you will get it on the next clock. The only case where you might miss it is if the pointer in the clocked domain changes at the same time so that you cross back out of the active quadrant (in the opposite direction). There it doesn't matter because if you are on the pointers equal side of the active quadrant the flip-flop is already set the correct way since you had to go through that active quadrant to get there in the first place. If you are on the pointers opposite quadrant, it doesn't matter which way the flip-flop is set because you have to cross one of the active quadrants to get to the pointers equal state. To cross a quadrant takes at least four clocks, so you have at least 3 clocks to resolve the metastable condition. The second clock is guaranteed to get you out of a metastable condition caused by not meeting the setup/hold at the first clock. (remember, we are dealing with a single ff here), as the quadrant inputs will be stable at the second clock if you are crossing the quadrant. The point is, you can use clocked logic here as long as it is clocked by the clock in the faster domain (or faster) without worrying about the effects of metastability. The circuit requires no additional synchronizer, as its action already provides plenty of protection against metastability. BTW, I can't take credit for this scheme. I believe Peter Alfke (xilinx) used it in one of his fifo app-notes. I have used it successfully many times however. Johnny Smooth wrote: > So you're using an SR *latch* (not a flipflop) to hold the "last operation" > info? Even though > you're using grey code counters for the quadrant pointers, that doesn't prevent > more than > one input to the quadrant compare from changing at a time (at most two, if both > pointers > change at the same time). With schematics you can guard against static hazards > on > the set and reset lines, but it's a little less certain for synthesizable stuff, > especially for > scalable designs. > > OTOH, if the "last operation" flipflop is truly an edge triggered D flipflop, I > guess you could > just use some independent clock (at least as fast as the read and write > pointers!) to load it, > with the required de-metastability measures for using that flop. Personally, if > another solution > exists, I try to avoid resync'ing. After all, you can never *eliminate* the > risk of metastability > crossing clock domains. > > John -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 13268
>BTW - how did you do the S-boxes? The CLB tables are just a bit too
>narrow to implement a S-box each. Last time I looked at this, just for
>fun, I would have put the S-boxes in an external EPROM. Then you can
>do it in a much smaller FPGA.
Any 6 input 4 output function can be fit into 10 clbs as a rom.
For some values this is not optimal.Check with basic logic minimization
techniques.
The Bearded Dave Praise your lord
dwp@po.cwru.edu
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Article: 13269Yes asychronous is still alive and well. It's called multiple clock domains. -jjh Rickman wrote: > Fredj Rouatbi wrote: > > > > I noticed that you are using VHDL. My question do you use Xilinx foundation > > timing simulator. My experience is, if the timing simulator gives the right > > results. Then when you implement the design it works. > > If you use only timing analysis to verify your design, you will not catch > > glitches and asynchronous logic. > > What asynchronous logic? Does someone use asynchronous logic??? > > Now the real flame war starts! ;-) > > -- > > Rick Collins > > redsp@XYusa.net > > remove the XY to email me.Article: 13270
Jamie Lokier wrote: > I disagree ;-) When the A register is clocked, the signals cascade > through a synthesised logic circuit to generate the new A + 1 value. > While it's true that the new A + 1 value will differ from the old A + 1 > value by only one bit, there are many different paths in the logic > circuit, including carry chains, so perhaps there can be a temporary > glitch in the A + 1 value which differs in other bits. I'd guess that > these glitches are unhelpfully rare. > > I'd be very pleased if you could show me this isn't a problem. This is the Gray sequence I will work with. 0000 0001 0011 0010 0110 0111 0101 0100 1100 1101 1111 1110 1010 1011 1001 1000 0000 The logic for each stage is (in peusdo VHDL): Repeat for each bit of register ignoring edge effects at ends of register: CarryUp(n) <= not Q(n) and CarryUp(n-1); CarryIn(n) <= Q(n-1) and CarryUp (n-2); IF (CarryIn(n) = TRUE) THEN D(n) <= not Q(n+1); ELSE D(n) <= Q(n); ENDIF There is one ripple chain. This chain along with the next lower bit controls the select mux between Q(n) and not Q(n+1). D(0) input is always not Q(1). It is much easier to see if you draw out the logic, but the ripple chain does not work like a binary adder. In essence, the ripple is the only path that propagates a change when any higher bit is to be enabled. It is also turned off for three of each four clock cycles. So each time the two LSBs become 00 (because the lsb changed from 1 to 0) the carry is propagated up the chain to the next FF past the first 1. No glitching is possible, because they were ALL disabled before the LSB changed from 1 to 0. The only possible source of glitches would be in the select mux and that is typically not a problem in FPGAs (at least in Xilinx I know). This is much easier to see if you draw the schematic and trace the sequences. -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 13271
brian@shapes.demon.co.uk (Brian Drummond) writes: > Consider for example, adding two numbers, in assembly language, with an > 1 byte wide accumulator. You have to add the LSByte first, to get the > "carry" for the next addition, and so on. That's a pain with a > big-endian format, and an even bigger pain with a mixture of 16-bit and > 32-bit big-endian... (do you look at address n+1 first, or n+3???) > > Byte order for a 64-bit (or greater) add would be: > > little-endian system: > > bytes 0,1,2,3,4,5,6,7 (...) > > big-endian system: > bytes 1,0,3,2,5,4,7,6 (if it's a 16-bit machine) > bytes 3,2,1,0,7,6,5,4 (if it's a 32-bit machine) Huh? Why would you store 64-bit numbers as a little-endian sequence of big-endian words? There is a famous document called "On Holy Wars and a Plea for Peace" (a web search will find it) which discusses big- vs. little-endian, and the conclusion is that it doesn't much matter: the important thing is to be consistent, from the word level on up (or for serial communications, from the bit level on up). As your example shows, inconsistant endianness at different levels causes pain. The consistent big-endian system: bytes 7,6,5,4,3,2,1,0 This is in fact the way 64-bit integers are typically implemented on 32-bit big-endian machines. > NOW which is cleaner??? ;) Neither, if you are consistent. > and by the way, you have to write your own memory addressing routine... What, for indirect addressing? > Of course when you have 32 bit accumulators this is an irrelevant pain, > but let's not forget what people were up against. With those > constraints, IMO little endian was far cleaner, and nowadays any > overhead costs required to live with it, are arguably less than the > costs of scrapping the system and starting again... What system? If the two machines on my desk, one is little-endian and one is big-endian. (Though I agree that isn't a very representative sample of anything other than my desk.) > p.s. hands up if you can read text from a big-endian binary dump! On a byte-addressed machine? For text, endianness makes no difference: Successive characters are stored at successive locations. On word-addressed machines with multiple characters packed into a word? Depends on the convention for that machine, and some machines had more than one convention. Some were saner than others. Dave WraggArticle: 13272
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Article: 13273Hi, I'm curious is anyone has used the Xilinx XChecker cable with a Spartan XL part (3.3V)? Any problems? Do you hook VCC on the pod up to 5V or 3.3V? Thanks, AustinArticle: 13274
Hi there! Why don't you go for a Wallace tree multiplier design, which is quite suitable for implementation in FPGAs. In fact, i have also synthesized a 32 x 32 binary multiplier that is based on the Wallace tree design. Its a purely structural design.Its a fast impementation too!! Mohsin Riaz Computers & Communication Security Lab, Faculty Of Engineering, Memorial University Of Newfoundland, St.John's,Newfoundland,Canada. email:mohsin@engr.mun.ca Web:www.engr.mun.ca/~mohsin On Mon, 16 Nov 1998 smeiyapp@my-dejanews.com wrote: > Try some floating point circuits. They are challenging and > you will *LEARN* a heck of a lot in modelling! > > In article <72g0mm$uud$1@nnrp1.dejanews.com>, > leslie.yip@asmpt.com wrote: > > Hello > > > > I think that a 16-bit x 16-bit binary multiplier will be quite challenging. > > After you implemented your project, would you place on the web site or give me > > to have a look? > > > > Leslie Yip > > > > In article <3ej22.1081$4S.3996@weber.videotron.net>, > > "Stephane Marcouiller" <mars02@gel.usherb.ca> wrote: > > > I have to find a suitable VHDL project for my course Computer Architecture > > > II > > > Suggestions are welcome > > > > > > Currently I have a couple of ideas like : branch prediction buffer, > > > pipelined CPU, L1 et L2 cache,... > > > > > > Do you have other ideas ? > > > > > > P.S. It must be possible to do it whitin 3 weeks * 5 hours/week = 15 hours > > > approx. > > > > > > Thx > > > > > > > > > > -----------== Posted via Deja News, The Discussion Network ==---------- > > http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own > > > > -----------== Posted via Deja News, The Discussion Network ==---------- > http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own > >
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