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Why don't you presample your 5 bit bus with the input flops using your 8x clock, and THEN route the newly synchronized bus to your 8 sets of capture registers. This will guarantee matched prop delay and you won't have to fuss with manual placement and routing. Regards ospyng@yahoo.com (spyng) wrote in message news:<b34a8c79.0206240917.7140fb66@posting.google.com>... > hi, > any one know is it possible to control the skew betwen different > signal on Virtex2. for i.e, between i_data[0], i_data[1] > ....i_data[7]. > > from what I understand NET "i_data[*]" MAXSKEW = 4 ns, will only > constraint the skew of the individual signal. > > the problem I have is that my external data(5 bit) and clock is not > align properly (don't ask me why, I have try that), so we are trying > to sample the input data with 8 different phase of the internal clock > and then determind which phase is the best to use. > > so there will be 8 set of input data sample register and they can not > be in the IOB. But we will have to make sure that all the 5 bit input > data have the same delay to all the 8 set of data sample reg. > > Xilinx actually have a app note on this (xapp 255), but I am not > convince that they are able to control the skew between different > signal. correct me if I am wrong. > > any help? > thanks > pyngArticle: 44626
Don't do you circuit with 2 seperate domains if you want your life to be easy. Generate your "one every N" pulse just the same but use it as a condition for your other circuit that is still clocked at the main clock rate but just sits idle for most clocks, but one in N, gets to change state. In FPGAs the clocks have to follow specific rules even though the HDL will let you code any configuration you desire. You can use DLLs and async FIFOs when you REALLY have no choice but multiple domains. Regards "Ken Mac" <aeu96186@yahoo.co.uk> wrote in message news:<af7c2v$a5k$1@dennis.cc.strath.ac.uk>... > Hello folks, > > The VHDL at the end describes a clock divider that will divide the input CLK > by any integer DIV and produce a clock pulse on CLKDIV that has the same > duration of CLKs period. The clock pulse on CLKDIV happens every DIV clock > edges of CLK (obviously :-) ) > > After synthesis in Synplify (targetting Xilinx Spartan-II) it looks pretty > good - very small and should run well over 100MHz apparently. > > So, the questions: > > It is my intention to pass data between two clock domains: CLK and CLKDIV - > can I use the VHDL below to synthesise CLKDIV and use this as the source > clock for the CLKDIV domain? > > Will this avoid metastability issues? > > Will I have to specify CLKDIV as having special status as a clock so that > the tools will put it on the global clock lines (hope that is the right > terminology)? > > Any other issues my inexperience has allowed me to miss? > > Am I on the right lines here in general or have I got the wrong end of the > stick? > > Thanks in advance for your time, > > Ken > > PS - I know I could use an asynchronous FIFO to cross the domain but I want > the smallest solution possible in terms of slices and want to avoid state > machines... > > > // START VHDL code > > > library IEEE; > use IEEE.std_logic_1164.all; > > entity eMetastabilityTesting is > port ( > CLK : in STD_LOGIC; > CLKDIV : out std_logic > ); > end eMetastabilityTesting; > > > architecture aMetastabilityTesting of eMetastabilityTesting is > > constant DIV : integer := 5; > signal cnt : integer range 0 to DIV := 0; > > begin > > process(clk) > begin > if rising_edge(clk) then > if cnt <= (DIV-1) then > cnt <= cnt + 1; > else > cnt <= 1; > end if; > end if; > end process; > > process(cnt) > variable tmp : std_logic; > > begin > if cnt <= (DIV-1) then > tmp := '0'; > else > tmp := '1'; > end if; > > clkdiv <= tmp; > end process; > > > end architecture; > > > // END VHDL codeArticle: 44627
Peter Alfke wrote: > > Your fingertip is a pretty good thermometer: > If you can maintain contact, the package is below 60 or 65 degree C. > If you pull away fast, it is above 70 degrees > If it sizzles, it is above 100 degrees. And if you can read the part number off your finger with a mirror, it's latched up.Article: 44628
Hi, from my experience The gate count for an ASIC technology will be usually smaller than the number given by the XC tool. The design will probably run faster in an ASIC technology, but it depends on your ASIC target technology. The VIRTEX devices are fabricated in a .22 u technology and are quite fast. So if you're using an older ASIC technology (.35 or .5 u) you should meet timing but it can be not so easy to reach. Study your ASIC vendor docs to see if RAMs are available. RAMs are technology dependent so you have to instantiate them. You will get a timing model from the ASIC vendor for synthesis and sta and probably a simulation model as well but this depends on your ASIC vendor. BTW the same is true for other technology dependent instances, e.g. PLL, ... HTH Ansgar "Nagaraj" <nagaraj@accord-soft.com> schrieb im Newsbeitrag news:9c782518.0206242122.34c3c4cc@posting.google.com... > Hi, > I have a design working with Xilinx Virtex FPGA Device. The design > is in VHDL. > I want to migrate from FPGA to ASIC. I have few questions about this. > > 1. The MAP report gives "Total Equivalent gate count for the design" > and "Additional JTAG gate count for IOBs". Is sum of these the true > indication of ASIC gates? What i mean is if i migrate to ASIC can I > safely assume that i will be utilizing only these many number of > gates? > > 2. What happens to maximum operating speed of my design? Will it > remain same as given in "Post place and Route Static Timing report" ? > or will it increse or decrease? > > 3. What happens to BlockRAMs? Will they become external to ASIC or > they still work as they were inside FPGA? > > Could anyone please answer these questions?Article: 44629
if the device gets that hot something is wrong. You should check if you have connected any "reserved" pins to VCC or GND potential or left open any GND or VCC pins. This typically causes an Altera FPGA to get extremely hot. Get appropriate information from Altera P&R report file and compare it to pcb connections.Article: 44630
Hello Community! I am looking for programming examples for my Spartan II Demo Board by Insight Electronics. It uses the Xilinx X2C100 FPGA. Does anyone have an idea, where to download functional source codes for this equipment? (I couldn´t find too much on the companies´ websites...) Thanx a lot, ThomasArticle: 44631
Hi,
I check all the things, and you're right. I find that the board
oscillator (80 Mhz/2) is different of the datasheet one (60MHz/2), and i
change the frequency in the mhs file and now, the communication is working.
Thanks,
"Matthew P. Ouellette" <matt.ouellette@xilinx.com> a écrit dans le message
news: 3D177237.75182D04@xilinx.com...
> Vincent,
>
> Verify UART communications in the other direction. Can you display STDOUT
via
> the HyperTerminal? The "Hello World" example would test communication in
this
> direction. Verify that your board clock frequency is the same as what is
set in
> the MHS file. Make sure the SD and EN UART signals are driven properly in
the
> MHS file. Verify your UCF pin settings.
>
> Matt
>
> Vincent JADOT wrote:
>
> > Hi,
> >
> > I m a beginer on xilinx fpga, i used to work with altera fpga. I'm
> > trying to compare, both embedded processor solution for a typical
> > application, for choosing the best one (speed of calculations).
> > So, i try to run the Xilinx's microblaze examples on the memec
spartan2
> > demo board.
> > When i try the interrupt_controller examples, i can't send data
(number)
> > with the windows "hyper terminal" ( i configure all my com port:
> > 19200bps,8bits,no parity,1 stop bit,noflow control).
> > There'snt number echoes on screen. The program run, but i can change
the
> > frequency of LED rotation.
> > Thanks.
>
Article: 44632
Falk/Newman/Jay,
Thanks for the replies.
Clock enables it is then!
I have recoded and come up with the code at the end - does this mean I can
run my lower speed logic using the CLKEN signal as follows:
if rising_edge(CLK) then
if (CLKEN = '1') then
--lower clock rate code
end if;
end if;
Thanks for your help...
Ken
library IEEE;
use IEEE.std_logic_1164.all;
entity eMetastabilityTesting is
port (
CLK : in STD_LOGIC;
CLKEN : out std_logic
);
end eMetastabilityTesting;
architecture aMetastabilityTesting of eMetastabilityTesting is
constant DIV : integer := 5;
signal cnt : integer range 0 to DIV := 1;
begin
process(clk)
begin
if rising_edge(clk) then
if cnt <= (DIV-1) then
cnt <= cnt + 1;
CLKEN <= '0';
else
cnt <= 1;
CLKEN <= '1';
end if;
end if;
end process;
end architecture;
"Jay" <kayrock66@yahoo.com> wrote in message
news:d049f91b.0206242208.65b9a8a3@posting.google.com...
> Don't do you circuit with 2 seperate domains if you want your life to
> be easy. Generate your "one every N" pulse just the same but use it
> as a condition for your other circuit that is still clocked at the
> main clock rate but just sits idle for most clocks, but one in N, gets
> to change state.
>
> In FPGAs the clocks have to follow specific rules even though the HDL
> will let you code any configuration you desire. You can use DLLs and
> async FIFOs when you REALLY have no choice but multiple domains.
>
> Regards
Article: 44633
Hi,
Try this address,
www.insight-electronics.com/solutions/kits/xilinx
There 're board datasheet and example of the counter.
Vincent,
"Thomas" <ThoLei@gmx.net> a écrit dans le message news:
ee77875.-1@WebX.sUN8CHnE...
> Hello Community!
>
> I am looking for programming examples for my Spartan II Demo Board by
Insight Electronics.
> It uses the Xilinx X2C100 FPGA.
>
> Does anyone have an idea, where to download functional source codes for
this equipment? (I couldn´t find too much on the companies´ websites...)
>
> Thanx a lot,
>
> Thomas
Article: 44634Hi kuldeep, try this : http://www.xilinx.com/xapp/xapp215.pdf kuldeep wrote: > Hi, > 1. is there any coding guidelines to use carry chains in xilinx fpga > (Virtex E) or i have to use coregen. > 2. is there any better method of coding a 12 bit adder than using > sum <= input1 + input2 > where sum, input1 and input2 are vectors. > > TIA > regards > KuldeepArticle: 44635
I tried the syn_reference_clock attribute and something weird happens. Synplify understands the constraints, since the Synplify log file is OK. However, Synplify does not pass this constraint to Xilinx (via the .ncf or .edf file). Ken McElvain <ken@synplicity.com> wrote in message news:<3D1660A2.5010908@synplicity.com>... > newman wrote: > > > "Ghys" <gagnon77@hotmail.com> wrote in message news:<SIoR8.268$Wm5.95145@wagner.videotron.net>... > > > >>The counter is already pipelined. > >>Does the syn_reference_clock garantee that the maximum delay on the clock > >>enable signal is one high-frequency period (4 ns) - setup & hold time ? > >> > > > > I believe the reference to the added pipeline stage was to back-up the > > counter decode one or more cycles, where it could be re-registered > > (pipelined) to help the fanout issues. > > > > For example, if the pulse is generated on count number 4, if you could > > generate it on count number 3, you could take that pulse and register > > it into perhaps 5 other flip-flops in parallel, to reduce your > > critical path clock enable fanout by a factor of 5. The change in > > code to account for the new clock enable distribution might be a pain, > > but is probably worth the effort. > > > > If sounds like you have only one clock domain (250 MHz), so I believe > > the tools will understand the 4 ns timing constraint as specified in > > your constraints file. You might investigate the use of multicycle > > path constaints to relax datapaths that do not have to propagate at 4 > > nS. > > The syn_reference_clock attribute takes care of this. Paths between > enabled flops will have 20ns because they are "clocked" by the virtual > clock clk50. > > > > > > I noticed in a VirtexE design, some portion of the Xilinx Tool Set > > (FPGA Express?) used a gbuf to route a synchronous reset sigal to a > > whole slew of flip-flops. I don't believe Virtex allowed this. If you > > have a gbuf to burn, and VirtexII allows routing of global lines to > > non-clock CLB inputs, and the global routing delay is fast enough, you > > might try instantiating a gbuf to route the Clock Enable, but probably > > only as a last resort. > > > > > > Newman > >Article: 44636
Kevin Neilson wrote: > I know Xilinx says that they don't yet support XP, but I've been using it > and have had no problems (other than those I would normally have). On the > contrary, I'm much happier, because instead of rebooting ~6 times per day on > ME I'm rebooting once every six days. > -Kevin > You mean MS have got a third of the way back to where they were with NT4+SP6A ? It makes me want to scream derision every time I see ``Built on NT technology'' in the Win2K banner.Article: 44637
CAN ANY ONE OF YOU GIVE ME A READY MADE POWERSUPPLY AND DEMO BOARD DESIGN FOR JTAG PROGRAMMING OF CPLDS IT WILL BE GREAT IF YOU GIVE ME THE PCB LAYOUTArticle: 44638
Petter Gustad wrote: > Is there a Windows equivalent to the cpld program (available under > Solaris)? I noticed that there is a C shell script with the same name > in the ISE 4.2iSP3 Windows distribution, but how can I run it? I can't > seem to find a supplied C shell? > > Petter > -- > ________________________________________________________________________ > Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.com One way would be to (1) Install Cygwin from http://sources.redhat.com/cygwin (2A) Convert the script from csh run under Cygwin's Bourne shell variant - bash. (2B) Convert the script to a makefile and use Cywin's make. Once you take the time (and it does take a couple of hours to download and install the whole shooting match) you won't regret it. There's even a, separately downloadable, good xemacs for Windows (works under NT & 2K at least, don't know about XP, 98, ME). About the only Unixy thing Cygwin can't provide you with is links that will be recognised by native Windoze programs compiled with VC/C++. I've been told that the way FAT and NTFS were designed makes the notion of a link impossible to achieve but, sadly, that's what you get with NIH.Article: 44639
Phil Hays <SpamPostmaster@attbi.com> wrote: > 3) Contact the vendor. After they are reasonably assured that you have > eliminated other issues and that your simple test case is reasonable, > they should be happy to get the part back, and should update their test > patterns to find this (and similar) flaws. Getting the part back seems to be the difficult part - you have to get it off your board in a fashion that doesn't destroy it, and then ideally fit a new part in its place. Non-trivial with 800+ pin BGA packages. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 44640
Rick Filipkiewicz <rick@algor.co.uk> writes: > Petter Gustad wrote: > > > Is there a Windows equivalent to the cpld program (available under > > Solaris)? I noticed that there is a C shell script with the same name > > in the ISE 4.2iSP3 Windows distribution, but how can I run it? I can't > > seem to find a supplied C shell? > > > > Petter > > -- > > ________________________________________________________________________ > > Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.com > > One way would be to > > (1) Install Cygwin from http://sources.redhat.com/cygwin I'm already using cygwin and bash. > (2A) Convert the script from csh run under Cygwin's Bourne shell variant - > bash. This script is almost 600 lines long. It's probably easer to fork out the various programs from within cpld using Wine under Linux. Petter - still can't see why Xilinx didn't port their Solaris version to Linux rather than using the Windows distribution and wine. -- ________________________________________________________________________ Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.comArticle: 44641
"Ken Mac" <aeu96186@yahoo.co.uk> schrieb im Newsbeitrag
news:af82bn$99l$1@paris.btinternet.com...
>
> Falk,
>
> Thanks for the reply.
>
> > > Will this avoid metastability issues?
> >
> > I would suggest to use a clock enable for your lower speed logic. This
> will
> > keep the whole thing on one clock doamin. No problem.
>
> Sounds good - how do I ensure the clock enables are used on the device
from
> my VHDL?
-- clock enable generation
process(clk)
begin
if clk='1' and clk'event then
if cnt=0 then
cnt <= div-1;
clk_en <= '1';
else
cnt <= cnt -1;
clk_en <='0';
end if;
end if;
end process;
-- use clock enable to slow down clocking
process(clk)
begin
if clk='1' anc clk'event then
if clk_en='1' then
-- place your statements here
end if;
end if;
end process;
>
> I get the feeling I am a small snippet of code away from making the leap!
You are. ;-)
--
MfG
Falk
Article: 44642On another note: even if your device is not operating at an abnormal temperature, it *is* possible that for a tightly timed design you could actually have a problem at 'normal' temperatures. If you find that the heat dissipation you are creating is not a problem then you might want to check to see if you are close in timing... if so, try nudgind down the close constraints a little, by a couple nanoseconds maybe.Article: 44643
My understanding is that while ISE4.1 was not released with offical XP compatibility is that it often is compatible. The upgrade to 4.2 is supposed to be compatibile. I have the Xilinx ISE Webpack and ModelSimXE installed on my home computer which runs XP and it runs fine.Article: 44644
Anyone here had any experiences yet using the new Virtex chips that include embedded PowerPC cores? Any papers posted or projects to look at?Article: 44645
"Kevin Neilson" <kevin-neilson@removethistextattbi.com> writes: > I know Xilinx says that they don't yet support XP, but I've been using it > and have had no problems (other than those I would normally have). On the > contrary, I'm much happier, because instead of rebooting ~6 times per day on > ME I'm rebooting once every six days. Even though SUN's are expensive they are very stable: scims:pegu $uptime 3:28pm up 91 day(s), 39 min(s), 4 users, load average: 1.02, 1.01, 1.01 91 days ago they had to remove the power in the entire office building. I was struggling with a problem with a faulty BSDL file the other day. iMPACT crashed and caused Win2k to freeze. I ended up debugging the BSDL file under Solaris (writing to an SVF file) where impact simply gave an error and bailed out. At least it didn't crash the OS. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.comArticle: 44646
newman5382@aol.com (newman) wrote in message news:<e6038423.0206241853.57847ecf@posting.google.com>... > Ray Andraka <ray@andraka.com> wrote in message news:<3D175C91.A17D20D6@andraka.com>... > > Nope, non that I am aware of. The clock nets are designed for low skew, but not > > necessarily low delay. I suspect even if you coerced the tools into letting you abuse > > the global clock distribution that you would find the delay unacceptable. The clock > > nets are wired just to the flip-flop clock inputs with an ability to get off the clock > > net onto the general routing. > > > Ray, > It does not take much to coerce the tools into letting you abuse the > global clock distribution ... > I had an external reset input that I wanted to register in an IOB, I > then routed that output to the asynchronous reset signal that went to > my inferred flip-flops to see whether I would meet timing (only 50 > MHz). Either FPGA Express or the Xilinx tools inferred a bufg between > the IOB register, and the asynchronous reset net. I called Xilinx, > and asked why it did this, and they told me because VirtexE had better > global routing resources. I had met all my timing constraints, so I > did not pursue the investigation any further or try to improve the > timing more than it had to be because I had other things to get done. > I'm sorry that one of my collegues wasted his time on what is > apparently a more aggressive design. You probably did, but I have to ask... did you have specific constraints on the resets? I don't believe they are constrained by your normal clock constraint because the target of the reset net is async. BTW, Ray, thanks for the ideas on the clock enable. I don't have trouble meeting timing with it, but it does chew up routing resources unnecessarily. MarcArticle: 44647
Greetings all, in VHDL we have the following way of telling the simulator/synthesis tool where to find the description of components that have not been explicitely declared within the source code: ------------------------------------------- library myLibrary; use myLibrary.my_package.my_component; ------------------------------------------- How do I do the same in Verilog? Thanks.Article: 44648
"Endric Schubert" <endric_@_bridges2silicon.com> ha scritto: >One of the reasons Leo may have reported much less LE is the fact that LEO >can extract RAM and ROM and implement it in embedded memory blocks. I don't >know whether Quartus can do that. In my design I use some LPM blocks (RAM) that appear black box in Leo, because I don't give him the entity description, but only the "component" one. So the EAB bits stay always to 0/106496 (for example). Then when I go in Quartus with the edif, it also recognize the LPM RAM and implements them on EAB RAM. How can you implement EAB bit also in Leo? As is said, they stay at 0% usage in my design. -- Per rispondermi via email sostituisci il risultato dell'operazione (in lettere) dall'indirizzo -- To reply via email write the correct sum (in letters) in the email addressArticle: 44649
Hi, Where can I find the release notes, or information describing the bugs fixed etc, for 4.2i service pack 3? (and SP1 and SP2 for that matter.) I have searched the Xilinx site and the closest I came was finding release notes for 4.1i service pack 1. Is this information available for 4.2i? Thanks Andrew
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z