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Messages from 87200

Article: 87200
Subject: Re: pricing of Virtex-4
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Tue, 19 Jul 2005 12:43:32 +0100
Links: << >>  << T >>  << A >>
Going by what I see your company makes then you could have a serious volume. 
As Peter has said the cost will come down in time but it also worth talking 
now to your distributor, or if you are large enough, your direct Xilinx 
representative. The newsgroup is not the place for these kinds of 
negotiations but picking up the telephone to the appropriate person could be 
well worth while. And as general hint for such a conversation have a 
projected usage plan ready. It is the first or second thing they will ask 
you.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development 
Board.
http://www.enterpoint.co.uk


"Vladislav Muravin" <muravinv@advantech.ca> wrote in message 
news:2GSCe.1415$Qi4.230573@news20.bellglobal.com...
> Peter,
>
> First, thank for very much for the answer.
>
> Yeah, I understand that giving V4 1-2 more years on the market will result 
> in something like 20%-30% or more price reduction
> and yet giving birth to Spartan-4-like family of cost-reducted V4 FPGAs, 
> but... we need them yesterday :o() as always
>
> Anyway, thanks again, appreciate it a lot.
>
> Vladislav
>
>
>
> "Peter Alfke" <peter@xilinx.com> wrote in message 
> news:1121711124.732297.69260@o13g2000cwo.googlegroups.com...
>>I am sorry that you did not get a quote from any distributor.
>> I usually stay out of such issues, but here is some help:
>> Single quantity LX15 in SF363 package used to be around $ 125
>> LX 25 was around $ 200.
>>
>> For reasonable quantities and a few months out, I think the price will
>> be half those numbers.
>> For really large quantitities and even further out it might be cut in
>> half again.
>> Just my guess, based on a few decades of experience...
>> This is a public newsgroup, and I don't want to contradict our
>> marketing and sales folks.
>> Peter Alfke
>>
>
> 



Article: 87201
Subject: simulation troubles
From: "zoinks@mytrashmail.com" <zoinks@mytrashmail.com>
Date: 19 Jul 2005 05:15:11 -0700
Links: << >>  << T >>  << A >>
hey all,

I still can't get the system-wide behavioral simulation of a
VirtexII-pro system to work, the entire system is "dead", it is not
executing any instructions, or so it seems

(what is the init-time for a standard PowerPC generated architecture
with no peripherals besides GPIO and UART?) I simulated 10ms but no
indication that anything was executed.

But now for my real question: When I try to simulate an XPS generated
design into modelsim using the "Start HDL Simulator" from the tool
menu, everything goes ok (I generated all the libs and VHDL simulation
files). But when Modelsim opens, I get the following error:

# Project file C:/<VERY OLD PATH>ModelSimTest.mpf was not found.
# Unable to open project.

The pathname given in this error is a path from a previous simulation
test which I gave up on a long time ago. I can't find any indication of
this path in any XPS settings. My question is: Where does it come from,
and how can I get my XPS to use the path of the system actually being
simulated?

Another big thanks from me,

Jim Tuilman


Article: 87202
Subject: Re: setting XUP new board
From: elinore2005@yahoo.fr
Date: 19 Jul 2005 05:16:02 -0700
Links: << >>  << T >>  << A >>
Hi

Yes, 'blinking in red' was not a problem ....
I followed 'quick start' example in the DIGILENT web site.....'hello
world' with microblaze is now okay
Thankyou all for nice remarks


Article: 87203
Subject: July 20th Altera Net Seminar: Stratix II Logic Density
From: "Paul Leventis \(at home\)" <paulleventis-news@yahoo.ca>
Date: Tue, 19 Jul 2005 08:53:43 -0400
Links: << >>  << T >>  << A >>

On Wednesday, July 20th @ 11 AM PST, two of my colleagues (Alex Grbic and 
Paul Ekas) will be giving a net seminar comparing Stratix II and Virtex-4 
logic densities.  They will describe the logic architectures of these two 
families, compare logic densities between these two families, discuss our 
benchmarking methodology and results, and provide software settings to 
maximize logic packing in Stratix II FPGAs.  Details can be found at 
http://www.altera.com/education/net_seminars/all/ns-stratix2_density.html.

Stratix II utilizes an innovative logic element we've called an "Adaptive 
Logic Module" or ALM.  This logic structure can efficiently implement two 
4-LUTs, one 6-LUT, some 7-input functions, a 3-LUT + 5-LUT, plus other 
combinations sharing inputs and/or portions of the LUT mask.  This 
capability translates into increased logic density, but complicates matters 
when it comes to comparing Stratix II results with those of traditional 
4-LUT based architectures such as Stratix I and Virtex.

I should point out that as part of this talk Alex will be providing results 
gathered from publicly available benchmark designs, allowing others to 
replicate the results he will present.

We will answer questions provided during the Net Seminar and I look forward 
to a healthy newsgroup discussion afterwards!

Regards,

Paul Leventis
Altera Corp 



Article: 87204
Subject: Re: Lattice MachXO is LAUNCHED NOW!
From: "Unbeliever" <alfkatz@remove.the.bleedin.obvious.ieee.org>
Date: Tue, 19 Jul 2005 23:33:48 +1000
Links: << >>  << T >>  << A >>

"Luc" <lb.edc@pandora.be> wrote in message
news:u6opd15kd7bi8rviq10fjkhb7hqbd22ek9@4ax.com...
> Alf,
>
> 100p TQFP is a quite useful package, don't you think?
They're all useful packages.  There exist, hovever, a class of applications
and hence a market that doesn't require lots of I/O, does require
significant logic and RAM, and does require small low cost 2-4 layer PCBs
without the luxury of the acres of real estate required to get signals out
of a larger, tighter package.  Of course, I don't know the physical die
sizes, so smaller packages may not be possible.

>
> If you're looking for a big 'MachXO', then you end up with the
> LatticeXP - 10K LUT's. The only trade off is that you'll need a BGA
> package, I'm afraid.
>

Yes, the XPs are nice (for me they'd be better with even more RAM), I've
been looking at the LFXP6 which *is* available in PQFP (and 208 pins is
ideal for this app).   My private company's motto is "Good, fast, cheap:
pick any two", the motto of FPGA vendors seems to be "Large, Non-volatile,
cheap, pick any two", probably for similar economic reasons.  It's only been
relatively recent that FPGAs are competitive with small hard processors in
cost constrained markets, and prices are coming down - though never fast
enough ;o)

Cheers,
Alf



Article: 87205
Subject: Re: Driving the FPGA output.
From: Kolja Sulimma <news@sulimma.de>
Date: Tue, 19 Jul 2005 15:41:10 +0200
Links: << >>  << T >>  << A >>
Antti Lukats schrieb:
> "vssumesh" <vssumesh_asic@yahoo.com> schrieb im Newsbeitrag
> news:1121753487.138517.30330@g14g2000cwa.googlegroups.com...
> 
>>Hello all,
>>     I am working on a ARM development board. I am modifting its system
>>FPGA which controls the peripherals. A signal output from the fpga is
>>now in the high impedance stete from the fpga and is pulled up with a
>>10k resistor. VCC is 3.3V. Another signal is pulled down to gnd using a
>>4.7K resistor. is it possible to drive these signals from the FPGA. if
>>yes what is the necessary modifications to be done in the ucf file
>>(about the drive strength, pad type etc). i tried with
>>LVTTL,PULLEDUP,Drive strength 12. But the value didnot changed. I
>>working with a Xilinx VirtexE FPGA. Please advice me on this issue.
>>Sumesh
>>
> 
> yes, it is possible. you need some meaningful and useful design into FPGA.
> nobody else except you know what you want to implement so nobody can help
> with that. as long as FPGA output is not driving the value on those pins
> will remain controlled by those ext. pullup pulldown resistors as the FPGA
> pullup/down resistors are very large nominal comparing to 10Kohms.

I was in the same situation once: I had a board with an CPLD that should
do something usefull later, but at the time of the first use the only
job of the CPLD was to set the OE of a Flash to '1'.
So I build a design with no inputs and a single output that was tied to
'1'. Unfortunately the sanity check of the fitter told me that a design
with 0 inputs was to large for the device that I had chosen ;-)
So I added unused inputs to the design which were optimized away by
synthesis.
Lucky me, there was an input connected to a constant 0 signal (constant
for that application) so I changed the CPLD into an inverted and it worked.

Kolja Sulimma

Article: 87206
Subject: Power PC Stall ??
From: "Vaggelis" <vlachos@nospam-dot-ics-dot-forth-dot-gr>
Date: Tue, 19 Jul 2005 09:43:25 -0400
Links: << >>  << T >>  << A >>
Hi everyone,

i am trying to connect a design of mine to the OCM interface of a Power PC
on a virtex II Pro FPAG. I need sometimes to stall the Power PC for
several clock cycles until my design fetches and deliver the correct data
to the PPC. I am trying to stall the processor by using a combination of
two specific signals (CPMC405CPUCLKEN and DBGC405DEBUGHALT). While this
approach works satisfactory, there are some cases (in simulation)where
after a stall the processor enters an undefined state forcing all of its
signals to xxx. 
 Do you have any idea why this happens? Have anyone ever tried to stall
the Power PC?

Thanks...


Article: 87207
Subject: Re: EHLO, board designers
From: Ray Andraka <ray@andraka.com>
Date: Tue, 19 Jul 2005 09:49:26 -0400
Links: << >>  << T >>  << A >>
Arash Salarian wrote:

>The problem is that the number of applications usefull for normal users 
>where a "tiny" FPGA like Spartan3 can make a significant speed-up in 
>comparision to a 3.8GHz Pentium IV, is quite small. Do you notice that 
>currently, GPUs for example are monsters with 300+ million transistors? 
>FPGAs, even the fattest ones are way too small to justify their application 
>in GENERAL processing markets. Don't take me wrong, I do DSP in FPGA and not 
>with processors exactly for performance reasons but I use it for very 
>special applications not for say, accelerating games or CAD applications as 
>you suggest. If you could get an FPGA board with a capacity of 10 million 
>gaits in less than $200 in the market, then I could start thinking of some 
>small applications for it in general PC market. With smaller FPGAs, just 
>forget it. 
>  
>
I disagree, there are quite a bit of applications where a Spartan3 can 
make a significant speed-up in
comparison to a 3.8 GHz P4.  These designs, however, are generally not 
trivial and take a considerable
amount of expertise in the generally non-overlapping disciplines of FPGA 
design and algorithm design.
The upper end of the spartan3 line is bigger, faster, and much more 
capable than the biggest FPGAs
were a couple years ago (which I successfully used in many DSP 
applications that beat the pants off
the software equivalents, thank you very much). The issue is not the 
capability of the 'cheap' FPGAs,
rather it is the complexity of the design required to make efficient use 
of the parts in computationally
intensive applications.  Tools for hardware DSP are still in their 
infancy, and the combined expertise for
 an efficient design that will fit these parts and still perform well is 
exceptionally rare.  Bottom line is
programming FPGAs is not like driving your father's CPU:the design has 
many more degrees of freedom,
which makes it harder both for a designer as well as for automated tools 
to arrive at the 'right' solution.
A high volume low cost FPGA accelerator for garden variety PCs isn't 
going to happen until the automated
tools make hardware DSP as easy as computer programming.  Until that 
happens, there just isn't going
be enough demand to amortize the development and support costs over 
enough units to make the cost of
the components the major cost of the board.

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 87208
Subject: ISE7.1 Map:Portability/export/Port_Main.h:127:1.22.234.1
From: Jens <j.doering@systektum.de>
Date: Tue, 19 Jul 2005 15:57:12 +0200
Links: << >>  << T >>  << A >>
when I switch on register duplication in MAP I get this FATAL ERROR.

Any Ideas about it.

I didn't find something about it on XILINX sites

Article: 87209
Subject: Re: ISE7.1 Map:Portability/export/Port_Main.h:127:1.22.234.1
From: "Antti Lukats" <antti@openchip.org>
Date: Tue, 19 Jul 2005 16:12:57 +0200
Links: << >>  << T >>  << A >>
"Jens" <j.doering@systektum.de> schrieb im Newsbeitrag
news:dbj0mi$k1g$1@news01.versatel.de...
> when I switch on register duplication in MAP I get this FATAL ERROR.
>
> Any Ideas about it.
>
> I didn't find something about it on XILINX sites


.h:127 is a FAMOUS common FATAL error, it gives no actual info what is
wrong. Xilinx tools internal BUG
need to contact xilinx or wait next service pack. nothing you can do to fix
the Xilinx tools.

you can try different things to get around it, if you are lucky you get it
working somehow.

Antti



Article: 87210
Subject: Re: "Tbufs don't exist"
From: jhallen@TheWorld.com (Joseph H Allen)
Date: Tue, 19 Jul 2005 14:26:37 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <18umd1l3thd7eb8kfli94bq4mvlv8scitv@4ax.com>,
Bob Perlman  <bobsrefusebin@hotmail.com> wrote:
>Personally, I liked the internal TriState buffers, real or pseudo;
>they were useful for building things like slow processor readback
>paths.  And as best I can recall, they were free of errata.  Those
>were the days.

I don't care that they're gone: you can make wide input OR gates with carry
chains, which end up being faster.

A problem with real TBUFs was that they were very limiting as far as
placement: you would end up with this giant array of host registers
overlayed on the rest of your design.

Another issue is that I wish all verilog synthesizers understood the "wor"
(wired-or) type.  I know Altera doesn't, but does understand tristate, which
is just weird because it's going to synthesize into a big OR gate.

[Also gone in recent Xilinx: the and-or structure for simulating PALs]

-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

Article: 87211
Subject: Re: July 20th Altera Net Seminar: Stratix II Logic Density
From: "Peter Alfke" <peter@xilinx.com>
Date: 19 Jul 2005 08:48:13 -0700
Links: << >>  << T >>  << A >>
I am glad to see that Altera has joined the world in acknowledging
Virtex-4 as The Gold Standard for FPGAs.
Peter Alfke, Xilinx Applications


Article: 87212
Subject: re:Virtex-4 5V tolerance
From: bigboytemp@hotmail-dot-com.no-spam.invalid (Big Boy)
Date: Tue, 19 Jul 2005 11:16:24 -0500
Links: << >>  << T >>  << A >>
Note that app. notes also specify, and this is important, that your
power regulator must support inverse voltage.

Imagine a case where your 3.3V network draw 50mA (for FPGA IO, 3.3V
devices, ...).  Then, the regulator that supply the 3.3V will output
50mA.

Now, take a few IO that you put 5V on them, with resistors to limit
the current to 10mA.  The way the FPGA is done, the IO pins have
protection diodes, which will take cut excess voltage at any IO to
Vcco + 0.7V (diode at IO connected to the Vcc).  Now, if you limit
current to 10mA, with a resistor for example, the primary MOS
transistor at IO pin won't draw more current (still only some pico or
nano-Amps).  So, the 10mA that goes through the IO end-up feeding the
3.3V Vcco network.

In the case above, having only one IO feeded by 5V (with 10mA going
through the IO), will feed the Vcco 10mA, while the regulator will
now only provide 40mA.  You will still have 3.3V on Vcco.  The
problem get if you feed more current than what is needed devices
connected to Vcco.  If you get too much current through the IO, then,
the 3.3V regulator will no longer supply current.  All the current
will come from the FPGA through the protection diodes.  The very BAD
thing is that the Vcco line will no longer be regulated to 3.3V, but
will get up higher (4.3V or more).

So, you must ensure that the regulator can also sink excess current,
to maintain the voltage to 3.3V.


Article: 87213
Subject: Re: ISE7.1 Map:Portability/export/Port_Main.h:127:1.22.234.1
From: "pasacco" <pasacco@gmail.com>
Date: 19 Jul 2005 10:15:22 -0700
Links: << >>  << T >>  << A >>
How about checking settings again, for example, device family, property
and preference for each step.


Article: 87214
Subject: Xilinx equivalent of simplify constrains.
From: "vssumesh" <vssumesh_asic@yahoo.com>
Date: 19 Jul 2005 10:29:03 -0700
Links: << >>  << T >>  << A >>
Dear friends i am now converting synplify project to the Xilinx
environment. I need help on the constrain conversion from Synplify 7.5
to XilinxISE6.2i.

1. What is the equivalent constrain of the "defineinput_delay" and
"define_output_delay". is "pad to setup" delauy in the Xilinx is
equivalent to this. Also there is a refeence to the clock in the
constrians. 

Sumesh


Article: 87215
Subject: ChipScope Pro : how to set up trigger
From: "pasacco" <pasacco@gmail.com>
Date: 19 Jul 2005 10:52:17 -0700
Links: << >>  << T >>  << A >>
Hi

I need some help with 'ChipScope Pro 6.3i inserter' in ISE 6.3.

As an exercise, I want to insert 'logic analyzer(ILA)' to simple
'counter' (below).

With respect to the user guide, I did was the following,

In ISE 6.3
* Implementation
* Bitstream generation and configuration on V2pro. ('counter.bit' - it
seems okay)

After that, in 'ChipScope Pro Inserter' setting
* Input trigger setting : 3 triggers
  - One port for 'reset' signal(width 1), one port for 'count'
signal(width 1), one port for 'Q' output signal (width 4)  )
  - Match type : 'Basic w/edge' type
  - Data type : "Data Same as Trigger"
* Connect
  - 'clock port' to 'CH0:clock_BUFGP'
  - 'trig0' to 'CH0:count_IBUF'
  - 'trig1' to 'CH0:reset_IBUF'
  - 'trig2' to 'CH0:Q_tmp_n0000<3>,
               'CH0:Q_tmp_n0000<2>,
               'CH0:Q_tmp_n0000<1>,
               'CH0:Q_tmp_n0000<0>
  - Insert  ('counter.cdc' - it seems okay, but not quite sure)

After that, in 'ChipScope Pro Analyzer'
* Jtag Chain -> cable selection
* To configure FPGA, load 'counter.bit' to device 2.
* To import project file, load 'counter.cdc'

Then finally some waveform appears.

Problem is that I do not know how to set up 'input trigger ports' (in
this case, 'count_IBUF', 'reset_IBUF', 'Q_tmp_n0000' - 5 signals ).

We need some input vectors (something like 'test vector' in
simulation). So far :) I could not find how to do that in user guide.

Thankyou for reading and some comment too

regards

----------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
port( clock: in std_logic;
      reset: in std_logic;
      count: in std_logic;    -- counter : enable
      Q:     out std_logic_vector(3 downto 0)
);
end counter;

architecture behv of counter is
    signal Q_tmp: std_logic_vector(3 downto 0);
begin
    Q <= Q_tmp;
    process(clock, count, reset)
    begin
	  if reset = '1' then
 	    Q_tmp <= "0000";
	  elsif (clock='1' and clock'event) then
	    if count = '1' then
		    Q_tmp <= Q_tmp + '1';
	    end if;
	  end if;
    end process;
end behv;
------------------------------------------------------


Article: 87216
Subject: Re: Xilinx equivalent of simplify constrains.
From: "Antti Lukats" <antti@openchip.org>
Date: Tue, 19 Jul 2005 20:04:21 +0200
Links: << >>  << T >>  << A >>
"vssumesh" <vssumesh_asic@yahoo.com> schrieb im Newsbeitrag
news:1121794143.274474.182880@g47g2000cwa.googlegroups.com...
> Dear friends i am now converting synplify project to the Xilinx
> environment. I need help on the constrain conversion from Synplify 7.5
> to XilinxISE6.2i.
>
> 1. What is the equivalent constrain of the "defineinput_delay" and
> "define_output_delay". is "pad to setup" delauy in the Xilinx is
> equivalent to this. Also there is a refeence to the clock in the
> constrians.
>
> Sumesh
>

get cgd.pdf from xilinx website and read it, it helps :)
no really the CGD.PDF is VERY important document explaining all the
constraints

Antti



Article: 87217
Subject: Re: ChipScope Pro : how to set up trigger
From: "Antti Lukats" <antti@openchip.org>
Date: Tue, 19 Jul 2005 20:08:18 +0200
Links: << >>  << T >>  << A >>
"pasacco" <pasacco@gmail.com> schrieb im Newsbeitrag
news:1121795536.937621.44040@g14g2000cwa.googlegroups.com...
> Hi
>
> I need some help with 'ChipScope Pro 6.3i inserter' in ISE 6.3.
>
> As an exercise, I want to insert 'logic analyzer(ILA)' to simple
> 'counter' (below).
>
> With respect to the user guide, I did was the following,
>
> In ISE 6.3
> * Implementation
> * Bitstream generation and configuration on V2pro. ('counter.bit' - it
> seems okay)
>
> After that, in 'ChipScope Pro Inserter' setting
> * Input trigger setting : 3 triggers
>   - One port for 'reset' signal(width 1), one port for 'count'
> signal(width 1), one port for 'Q' output signal (width 4)  )
>   - Match type : 'Basic w/edge' type
>   - Data type : "Data Same as Trigger"
> * Connect
>   - 'clock port' to 'CH0:clock_BUFGP'
>   - 'trig0' to 'CH0:count_IBUF'
>   - 'trig1' to 'CH0:reset_IBUF'
>   - 'trig2' to 'CH0:Q_tmp_n0000<3>,
>                'CH0:Q_tmp_n0000<2>,
>                'CH0:Q_tmp_n0000<1>,
>                'CH0:Q_tmp_n0000<0>
>   - Insert  ('counter.cdc' - it seems okay, but not quite sure)
>
> After that, in 'ChipScope Pro Analyzer'
> * Jtag Chain -> cable selection
> * To configure FPGA, load 'counter.bit' to device 2.
> * To import project file, load 'counter.cdc'
>
> Then finally some waveform appears.
>
> Problem is that I do not know how to set up 'input trigger ports' (in
> this case, 'count_IBUF', 'reset_IBUF', 'Q_tmp_n0000' - 5 signals ).
>
> We need some input vectors (something like 'test vector' in
> simulation). So far :) I could not find how to do that in user guide.
>
> Thankyou for reading and some comment too
>
> regards
>
> ----------------------------------------------------
> library ieee ;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_unsigned.all;
>
> entity counter is
> port( clock: in std_logic;
>       reset: in std_logic;
>       count: in std_logic;    -- counter : enable
>       Q:     out std_logic_vector(3 downto 0)
> );
> end counter;
>
> architecture behv of counter is
>     signal Q_tmp: std_logic_vector(3 downto 0);
> begin
>     Q <= Q_tmp;
>     process(clock, count, reset)
>     begin
>   if reset = '1' then
>       Q_tmp <= "0000";
>   elsif (clock='1' and clock'event) then
>     if count = '1' then
>     Q_tmp <= Q_tmp + '1';
>     end if;
>   end if;
>     end process;
> end behv;
> ------------------------------------------------------
>

its only you yourseld who knows on what event you want to trigger.
just select the 1 0 R F B or in the trigger setting and arm the ILA

Antti
BTW I dont understand why you defined 3 trigger ports not one, doesnt seem
to make sense in this example.








Article: 87218
Subject: Re: July 20th Altera Net Seminar: Stratix II Logic Density
From: "tim" <tkellis4520@yahoo.com>
Date: 19 Jul 2005 11:30:23 -0700
Links: << >>  << T >>  << A >>
Paul

You and the rest of your team at Altera should be absolutely
embarrassed that you continue with this marketing analysis of the
Stratix II logic superiority over the Virtex 4.  And keep in mind that
I have no opinion of one Company over the other.

Looking at the Stratix II 180 vs. the Virtex 4 200, as an example:

In your analysis you claim that the Altera Stratix II "180" with
186,576 "4-input LUTs" is bigger than the Xilinx Virtex 4 "200"
with 178,176 "4-input LUTs".

The point is that the Altera 180 part has 143,520 "ALUTs" and
179,400 "Logic Elements" while the Virtex 200 part has 178,176
"LUTs" and 200,448 "Logic Cells".

The concluding point is that in the Altera uses its higher 179,400
(actually increasing the number to 186,576) number and compares it with
the lower Xilinx 178,176 number in stating its superiority.

You must be kidding that you are using higher Altera count to compare
with the smaller Xilinx count.  You must honestly believe that you are
dealing with idiots.  Anyhow, you should really be comparing the ALUT
number with the LUT number anyhow, because that is your closes
architectural comparison.  Look-up-tables are look-up-tables,
regardless of what you call them.

I could elaborate more on the multiplier and memory comparisons, but I
won't, and the conclusions are the same.

You guys actually had the guts to release a press release with this
analysis:

http://www.altera.com/corporate/news_room/releases/products/nr-density.html

And would you quit marketing your variable input LUT architecture.
Xilinx has had a variable input LUT archtecture since the Virtex was
introduced in 1998.

You really don't think that smart engineers buy this "analysis", do
you?

Just trying to get to the truth.

Tim


Paul Leventis (at home) wrote:
> On Wednesday, July 20th @ 11 AM PST, two of my colleagues (Alex Grbic and
> Paul Ekas) will be giving a net seminar comparing Stratix II and Virtex-4
> logic densities.  They will describe the logic architectures of these two
> families, compare logic densities between these two families, discuss our
> benchmarking methodology and results, and provide software settings to
> maximize logic packing in Stratix II FPGAs.  Details can be found at
> http://www.altera.com/education/net_seminars/all/ns-stratix2_density.html.
>
> Stratix II utilizes an innovative logic element we've called an "Adaptive
> Logic Module" or ALM.  This logic structure can efficiently implement two
> 4-LUTs, one 6-LUT, some 7-input functions, a 3-LUT + 5-LUT, plus other
> combinations sharing inputs and/or portions of the LUT mask.  This
> capability translates into increased logic density, but complicates matters
> when it comes to comparing Stratix II results with those of traditional
> 4-LUT based architectures such as Stratix I and Virtex.
>
> I should point out that as part of this talk Alex will be providing results
> gathered from publicly available benchmark designs, allowing others to
> replicate the results he will present.
>
> We will answer questions provided during the Net Seminar and I look forward
> to a healthy newsgroup discussion afterwards!
> 
> Regards,
> 
> Paul Leventis
> Altera Corp


Article: 87219
Subject: Re: July 20th Altera Net Seminar: Stratix II Logic Density
From: "Antti Lukats" <antti@openchip.org>
Date: Tue, 19 Jul 2005 21:01:02 +0200
Links: << >>  << T >>  << A >>

"tim" <tkellis4520@yahoo.com> schrieb im Newsbeitrag
news:1121797823.215527.11170@g44g2000cwa.googlegroups.com...
> Paul
>
> You and the rest of your team at Altera should be absolutely
> embarrassed that you continue with this marketing analysis of the
> Stratix II logic superiority over the Virtex 4.  And keep in mind that
> I have no opinion of one Company over the other.
>
> Looking at the Stratix II 180 vs. the Virtex 4 200, as an example:
>
> In your analysis you claim that the Altera Stratix II "180" with
> 186,576 "4-input LUTs" is bigger than the Xilinx Virtex 4 "200"
> with 178,176 "4-input LUTs".
>
> The point is that the Altera 180 part has 143,520 "ALUTs" and
> 179,400 "Logic Elements" while the Virtex 200 part has 178,176
> "LUTs" and 200,448 "Logic Cells".
>
> The concluding point is that in the Altera uses its higher 179,400
> (actually increasing the number to 186,576) number and compares it with
> the lower Xilinx 178,176 number in stating its superiority.
>
> You must be kidding that you are using higher Altera count to compare
> with the smaller Xilinx count.  You must honestly believe that you are
> dealing with idiots.  Anyhow, you should really be comparing the ALUT
> number with the LUT number anyhow, because that is your closes
> architectural comparison.  Look-up-tables are look-up-tables,
> regardless of what you call them.
>
> I could elaborate more on the multiplier and memory comparisons, but I
> won't, and the conclusions are the same.
>
> You guys actually had the guts to release a press release with this
> analysis:
>
>
http://www.altera.com/corporate/news_room/releases/products/nr-density.html
>
> And would you quit marketing your variable input LUT architecture.
> Xilinx has had a variable input LUT archtecture since the Virtex was
> introduced in 1998.
>
> You really don't think that smart engineers buy this "analysis", do
> you?
>
> Just trying to get to the truth.
>
> Tim
>
>
> Paul Leventis (at home) wrote:
> > On Wednesday, July 20th @ 11 AM PST, two of my colleagues (Alex Grbic
and
> > Paul Ekas) will be giving a net seminar comparing Stratix II and
Virtex-4

[altera marketing skipped]

S180 has more memory then LX200, what is LOGIC optimized, not memory
optimized. besides that the large memory blocks can not be loaded from
config memory so its not fair comparison anyway. SX and FX devices way
smaller than S180 have way more memory. So Virtex beats the S180 on memory

S180 has more multipliers than LX200, what again is LOGIC optimized not DSP
optimized, SX is DSP optimized and again way smaller device has more DSP
slices than the S180 has multipliers

on total pin count, well here Altera currently beats Virtex-4 offering.

on the overall I am 100% with Tim that all the Altera comparison is totally
unfair. of course its hard to have the total truth, the suitability depends
on the application and the quality of the tools and many other things. S180
is possible largest single device 1 for all from Altera, where Xilinx has
splitted the high end family into 3 offering what is needed for different
applications.

Antti
PS Paul, it would be much more interesting to see the Altera Stratix-2 GX
announced, or is really delaying so loong? I would have expected it to be
released by now. It still is coming? Could be that Lattice high end FPGAs
come out before S2GX, and will beat the S2GX similary as machXO beats MAX2.
Not saying that MAX2 isnt nice, it is but the things Altera forgot, they are
all in machXO, and try to pronounce it
MAX2 machXO sounds even similar :), I bet some Lattice guy made the name
deliberatly to sound like MAX2 nice move, ;) and no trademarks violated!






Article: 87220
Subject: Re: Xilinx equivalent of simplify constrains.
From: "Vladislav Muravin" <muravinv@advantech.ca>
Date: Tue, 19 Jul 2005 16:06:06 -0400
Links: << >>  << T >>  << A >>
there is a very nice table is XST constraints guide which shows Synplicity & 
their equivalent XST constraints

Vladislav


"vssumesh" <vssumesh_asic@yahoo.com> wrote in message 
news:1121794143.274474.182880@g47g2000cwa.googlegroups.com...
> Dear friends i am now converting synplify project to the Xilinx
> environment. I need help on the constrain conversion from Synplify 7.5
> to XilinxISE6.2i.
>
> 1. What is the equivalent constrain of the "defineinput_delay" and
> "define_output_delay". is "pad to setup" delauy in the Xilinx is
> equivalent to this. Also there is a refeence to the clock in the
> constrians.
>
> Sumesh
> 



Article: 87221
Subject: Re: ISE7.1 Map:Portability/export/Port_Main.h:127:1.22.234.1
From: "Vladislav Muravin" <muravinv@advantech.ca>
Date: Tue, 19 Jul 2005 16:08:42 -0400
Links: << >>  << T >>  << A >>
I opened the same issue in Xilinx webcase and they said this is a known bug 
which is being worked on.
And Xilinx say that if I do not send them the NGC file within two business 
days, this case is going to be closed.
This is the way it is now, but it's probably gonna be fixed in the next 
release.

Vladislav

"Jens" <j.doering@systektum.de> wrote in message 
news:dbj0mi$k1g$1@news01.versatel.de...
> when I switch on register duplication in MAP I get this FATAL ERROR.
>
> Any Ideas about it.
>
> I didn't find something about it on XILINX sites 



Article: 87222
Subject: Re: pricing of Virtex-4
From: "Vladislav Muravin" <muravinv@advantech.ca>
Date: Tue, 19 Jul 2005 16:20:22 -0400
Links: << >>  << T >>  << A >>
John,

The company I work in does not produce 100,000+ volumes on the yearly basis.
Also, I never intend to negotiate here, but I just wanted to get the 
APPROXIMATE range of the price while considering FPGA device(s) for the next 
project(s).

Funny thing, I have been waiting for the quotation for 4 weeks, but as i 
posted this one, the next day i got it in my e-mail... Strange...

But thanks for your hints.

Vladislav


"John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> wrote in 
message news:1121773408.32068.0@echo.uk.clara.net...
> Going by what I see your company makes then you could have a serious 
> volume. As Peter has said the cost will come down in time but it also 
> worth talking now to your distributor, or if you are large enough, your 
> direct Xilinx representative. The newsgroup is not the place for these 
> kinds of negotiations but picking up the telephone to the appropriate 
> person could be well worth while. And as general hint for such a 
> conversation have a projected usage plan ready. It is the first or second 
> thing they will ask you.
>
> John Adair
> Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development 
> Board.
> http://www.enterpoint.co.uk
>
>
> "Vladislav Muravin" <muravinv@advantech.ca> wrote in message 
> news:2GSCe.1415$Qi4.230573@news20.bellglobal.com...
>> Peter,
>>
>> First, thank for very much for the answer.
>>
>> Yeah, I understand that giving V4 1-2 more years on the market will 
>> result in something like 20%-30% or more price reduction
>> and yet giving birth to Spartan-4-like family of cost-reducted V4 FPGAs, 
>> but... we need them yesterday :o() as always
>>
>> Anyway, thanks again, appreciate it a lot.
>>
>> Vladislav
>>
>>
>>
>> "Peter Alfke" <peter@xilinx.com> wrote in message 
>> news:1121711124.732297.69260@o13g2000cwo.googlegroups.com...
>>>I am sorry that you did not get a quote from any distributor.
>>> I usually stay out of such issues, but here is some help:
>>> Single quantity LX15 in SF363 package used to be around $ 125
>>> LX 25 was around $ 200.
>>>
>>> For reasonable quantities and a few months out, I think the price will
>>> be half those numbers.
>>> For really large quantitities and even further out it might be cut in
>>> half again.
>>> Just my guess, based on a few decades of experience...
>>> This is a public newsgroup, and I don't want to contradict our
>>> marketing and sales folks.
>>> Peter Alfke
>>>
>>
>>
>
> 



Article: 87223
Subject: Re: Lattice MachXO is LAUNCHED NOW!
From: Luc <lb.edc@pandora.be>
Date: Tue, 19 Jul 2005 23:00:15 +0200
Links: << >>  << T >>  << A >>
Alf,

There will always be designs that need something different than what
the majority of the design community can use.

Look at it from another point of view: if the company you're working
for can cover 80% of your targetted customers with the latest design,
wouldn't you be happy?

your 2nd remark: don't generalize the fact that both Xilinx and Altera
are playing it hard on the high end side of the FPGA market - and it
can't be big enough.
Lattice's emphasis has been last couple of years to introduce some
parts with unique features in the low end side. Look at XP and last
year the EC and ECP families. All good, fast and cheap parts. Isn't
that what you were looking for? ;o))

Regards,

Luc

On Tue, 19 Jul 2005 23:33:48 +1000, "Unbeliever"
<alfkatz@remove.the.bleedin.obvious.ieee.org> wrote:

>
>"Luc" <lb.edc@pandora.be> wrote in message
>news:u6opd15kd7bi8rviq10fjkhb7hqbd22ek9@4ax.com...
>> Alf,
>>
>> 100p TQFP is a quite useful package, don't you think?
>They're all useful packages.  There exist, hovever, a class of applications
>and hence a market that doesn't require lots of I/O, does require
>significant logic and RAM, and does require small low cost 2-4 layer PCBs
>without the luxury of the acres of real estate required to get signals out
>of a larger, tighter package.  Of course, I don't know the physical die
>sizes, so smaller packages may not be possible.
>
>>
>> If you're looking for a big 'MachXO', then you end up with the
>> LatticeXP - 10K LUT's. The only trade off is that you'll need a BGA
>> package, I'm afraid.
>>
>
>Yes, the XPs are nice (for me they'd be better with even more RAM), I've
>been looking at the LFXP6 which *is* available in PQFP (and 208 pins is
>ideal for this app).   My private company's motto is "Good, fast, cheap:
>pick any two", the motto of FPGA vendors seems to be "Large, Non-volatile,
>cheap, pick any two", probably for similar economic reasons.  It's only been
>relatively recent that FPGAs are competitive with small hard processors in
>cost constrained markets, and prices are coming down - though never fast
>enough ;o)
>
>Cheers,
>Alf
>


Article: 87224
Subject: Xilinx sysace + xmd -jprog options.
From: "tony.p.lee@gmail.com" <tony.p.lee@gmail.com>
Date: 19 Jul 2005 15:27:02 -0700
Links: << >>  << T >>  << A >>
We have multiple Xilinx FPGAs on our jtag chain.  The main
VP20 ppc is loaded first.  It detects what other cards/FPGA
plug into the system, connect those devices to jtag chains
and load their ace files.

Everything works fine except when we start to the
-jprog options on the secondary loading of line card/fpga's
ace files.

It seems that we the load the line card's ace file
(build with -jprog flag), the main FPGA/ppc's configuration
memory also being clear.

It looks like the genace's -jprog option is not just for the
selected device but impact all the devices in the jtag chain
when it programs.

Does anyone know if this is the correct diagnostic
of our problem?

If so, we really need to clear the secondary device's
configuration memory when we do upgrade those
device without power cycle the system.  What's the
best way to do that?


Thank you very much.

-Tony




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