Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 86800

Article: 86800
Subject: Re: fastest FPGA speed grade?
From: "B. Joshua Rosen" <bjrosen@PleaseDontSpamMEpolybus.com>
Date: Wed, 06 Jul 2005 18:17:34 -0400
Links: << >>  << T >>  << A >>
On Tue, 05 Jul 2005 21:49:09 -0600, Dave wrote:

> Is the Xilinx Virtex 4 the fastest FPGA available in in-circuit 
> reprogrammable format?
> 
> Their data sheet claims 450MHz PPC and 500MHz DSP.  The -12 speed grade of 
> the XC4VFX40 or 60 devcies sound like they won't be available until next 
> year, though.
> 
> I couldn't find definitive data in the Altera literature about the speed of 
> the Stratix II parts.  Do these parts run at speeds approaching the Virtex 4 
> parts?
> 
> Does Lattice offer high-speed devices with built-in microprocessor, DSP, and 
> RAM support?  It appears the EC family supports RAM at up to 200MHz.
> 
> Thanks.
> 
> Dave

Even though the Xilinx and Altera FPGA appear very similar there are
subtle differences which leads to different choices depending on the
target for you design. I'll give you a simple example, Block RAMs. The
Block RAMs in Virtex2P are faster then the Block RAMs in the Stratix II in
single pipeline mode, i.e. no output register. However the Stratix II
includes an optional output register in the Block RAM component, the
Virtex2P doesn't have an output register (the Virtex4 does). If you use
the output register in the Stratix II then the Stratix II will be faster,
if you don't then the Virtex2P will be faster. So if you were targeting a
design for the Virtex2P you probably won't register the outputs of your
Block RAMs unless you are shooting for a very high frequency because the
registers use up precious flip flips. If you then move the design to a
Virtex2P it will run slower. However if you were designing for the Stratix
II you would use output register because they are free and they'll
simplify routers task because it will have a easier time meeting timing.
If you then move the design to a Virtex2P it will be bigger and it might
be slower because the output register would have to be instantiated in
flip flops. There are lots of choices like that, another example is LUT
RAMs and LUT based shift registers which Xilinx has and Altera doesn't.
because they are there you'll use them if you are targeting Xilinx which
means that that design will be bigger and slower if you put it into an
Altera part. This sort of thing goes both ways, the Altera M512 RAM is 32
deep so if you are targeting an Altera part you will probably make your
small FIFOs 32 words deep, if you then move it to a Xilinx part you'll
need 4 LUTs per bit which will make the design bigger and slower in the
Xilinx part.

The bottom line is that if Altera and Xilinx each gather up a 1000 designs
from their own customer bases and then build for both architectures each
will find that their own architecture is 20% faster then the other guy's.
Neither will be lying, the results will clearly show that their own
architecture is significantly better in an overwhelming number of cases.
The problem is in the sample, if you ask Germans and Englishmen which is
better Lager or Ale you'll get a different answer.



Article: 86801
Subject: for sale: two spartan-3 dev boards, $50 each (normally $100)
From: Adam Megacz <megacz@cs.berkeley.edu>
Date: Wed, 06 Jul 2005 15:34:25 -0700
Links: << >>  << T >>  << A >>

I have two Spartan-III development boards; I bought two of Xilinx's
dev kits a while ago and no longer need them.  Here's the link to the
product on Xilinx's site:

 http://www.xilinx.com/products/spartan3/s3boards.htm

Brand new they're $100 each, one is on Ebay with several bids at $68;
I'll part with them for $50 each.  You get just the board, power
adapter, and parallel-to-JTAG cable; everything else that comes with
the kit can be found on Xilinx's website (ISE WebPack, pdf's of the
manual).

Here's a picture of them:

  http://www.megacz.com/tmp/spartan.boards.jpeg

sorry it's so blurry; my camera stinks.  Let me know if you have any
questions about part numbers, etc.

You can pick them up from me in SoMA (San Francisco), Berkeley, or I
can send them to you FedEx or UPS.  I'm willing to sell them
separately, but would prefer to get rid of both at the same time.

  - a

Article: 86802
Subject: Has anybody run Virtex-4 FPGAs at 300MHz+ interface speed?
From: "azam" <azamirfan@gmail.com>
Date: 6 Jul 2005 15:35:52 -0700
Links: << >>  << T >>  << A >>
I was trying to determine the max frequency that can be clocked thru
the Virtex-4 FPGA pins. While referring the Virtex-4 User Guide the (DC
and Switching characteristics) Section of the book has blank columns.
Although the Virtex-4 FPGA Handbook mentions the capabiltiy to meet
different I/O standards, I was wondering has anyone been able to
exercise the I/Os of the Virtex Family above 300MHz.

Thanks
-Azam


Article: 86803
Subject: Re: EDK/ISE 7.1 SmartModel Set-up Issue with ModelSim 6.0a
From: "Nju Njoroge" <njoroge@stanford.edu>
Date: 6 Jul 2005 17:52:04 -0700
Links: << >>  << T >>  << A >>
Nju Njoroge wrote:
> Duane Clark wrote:
> > Nju Njoroge wrote:
> > > Hi,
> > >
> > > I'm using ModelSim SE 6.0a with ISE 7.1 (SP 2) and EDK (SP 1). I get
> > > the following error with the PPC SmartModel.
> > >
> > > # Loading work.ppc405_0_wrapper(structure)
> > > # Loading C:/simlib/EDK_Lib/ppc405_v2_00_c/.ppc405_top(structure)
> > > # Loading C:/simlib/unisim/.ppc405(ppc405_v)
> > > # Loading C:/simlib/unisim/.ppc405_swift_bus(ppc405_swift_bus_v)
> > > # Loading C:/simlib/unisim/.ppc405_swift(smartmodel)
> > > # Loading c:\Modeltech_6.0a\win32/libsm.dll
> > > # ** Error: Unable to read LMC SmartModel library file "** Fatal:
> > > Foreign module requested halt.
> > > #    Time: 0 ps  Iteration: 0  Instance:
> > > /system/ppc405_0/ppc405_0/ppc405_i/ippc405_swift/ppc405_swift_inst
> > > File: C:/Xilinx/smartmodel/nt/wrappers/mtivhdl/smartmodel_wrappers.vhd
> > > # FATAL ERROR while loading design
> > > # Error loading design
> > > # Error: Error loading design
> > >
> > > The VHDL file,
> > > C:/Xilinx/smartmodel/nt/wrappers/mtivhdl/smartmodel_wrappers.vhd, is
> > > where it is supposed to be and it looks legit when I open it. Also, I
> > > recently upgraded from EDK 6.3, in which the SmartModel worked well. In
> > > the upgrade, I followed the usual set of procedures
> > > (http://www.xilinx.com/ise/embedded/ps_ug.pdf, page 120). Additionally,
> > > all the simulations were re-compiled for the new versions of ISE and
> > > EDK.
> >
> > The smartmodel_wrappers.vhd does not appear to be your problem. The
> > error message claims the problem is with the "LMC" library. This would
> > probably be defined in your modelsim project file with a line like:
> >
> > libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
> >
> > Have you made sure that the combination of the environment variable and
> > the rest of the line points to the correct file?
> Yes, I have these variables set appropriately (as instructed by the
> Platform Studio User Guide, page 120). In my modelsim.ini, I have:
>
> libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
>
> where $LMC_HOME points to %XILINX%\smartmodel\nt\installed_nt.
>
> I did not change this configuration when upgrading from 6.3 to 7.1. In
> 6.3, this used to work, but it no longer does for 7.1.
I resolved the issue and now the error goes away: I noticed that my
installation of ISE was an evaluation one (the one that comes with the
EDK CD's), so I installed the real version (the one that comes in the
ISE CD packages). For some reason, the eval version wasn't properly
compiling the libraries and/or preventing the usage of the
SmartModel... In any case, using the non-eval version got it running.

NN


Article: 86804
Subject: Re: fastest FPGA speed grade?
From: "Dave" <starfire151@cableone.net>
Date: Wed, 6 Jul 2005 19:25:50 -0600
Links: << >>  << T >>  << A >>
Many thanks to all who responded.  Very helpful input.  It's given me some 
good data to examine.

My application requires multiple stamps of very fast DSPs (for data 
acquistion and filtering), a high-speed RAM interface (to store the 
acquistion results), failry high-speed disk operations (to off-load and 
archive the acquistion results), and several slower-speed housekeeping tasks 
(user control input and display output, etc.), which could be handled by an 
embedded "soft" processor.

It sounds like the Virtex 4 or the Stratix II is probably the right approach 
in this application.


Dave


"Dave" <starfire151@cableone.net> wrote in message 
news:11cml61qpqtaq81@corp.supernews.com...
> Is the Xilinx Virtex 4 the fastest FPGA available in in-circuit 
> reprogrammable format?
>
> Their data sheet claims 450MHz PPC and 500MHz DSP.  The -12 speed grade of 
> the XC4VFX40 or 60 devcies sound like they won't be available until next 
> year, though.
>
> I couldn't find definitive data in the Altera literature about the speed 
> of the Stratix II parts.  Do these parts run at speeds approaching the 
> Virtex 4 parts?
>
> Does Lattice offer high-speed devices with built-in microprocessor, DSP, 
> and RAM support?  It appears the EC family supports RAM at up to 200MHz.
>
> Thanks.
>
> Dave
>
> 



Article: 86805
Subject: Re: Cheking out Linux Kernel Source
From: praetorian <Hua.Zheng@jpl.nasa.gov>
Date: Wed, 06 Jul 2005 18:31:26 -0700
Links: << >>  << T >>  << A >>
Sewook Wee wrote:
> Hello,
> 
> I am using VIIPro on ML310 board, and trying to port Linux on it.
> While I was trying to check out the Linux Kernel Source using 
> BitKeeper(BK), it complained that BK is not free anymore.
> 
> Is there anyone who knows where can I get the kernel source?
> The version that I need is v2.4.21.
> 
> Thank you.
> 
> Sewook Wee
you could get the source from ELDK. http://www.denx.de

Article: 86806
Subject: Re: ModelSim Timing Simulation Signal Names
From: "PeterC" <peter@geckoaudio.com>
Date: 6 Jul 2005 19:17:05 -0700
Links: << >>  << T >>  << A >>
Thanks again Phil,

I'll definitely get rid of the clock mux and see what happens to the
output. I've tested the re-loading of coefficients by applying an unit
pulse input and could see that the filter output (impulse response) was
as expected, ie. out came the coefficient set which was loaded in. So
I'd clearly expect the loading of coefficients to be identical under
conditions where the input was a sine wave, but something is clearly
wrong somewhere. So I'm willing to resort to re-designing using good
techniques, and clearly clock muxing is not one of them, even if
chipscope seems to be telling me that things are ok. If this fails then
I will look at the constraints issues.

--Peter Celinski
peter (AT) geckoaudio dot com


Article: 86807
Subject: Actel vs. Xilinx and Altera
From: "Joel Kolstad" <JKolstad71HatesSpam@yahoo.com>
Date: Wed, 6 Jul 2005 19:46:43 -0700
Links: << >>  << T >>  << A >>
Hi,

It's been a couple of years since I've been a heavy FPGA user, but it appears
that I'll now be getting back into them.  As of a few years back, I was using
Xilinx Virtex IIe parts and was quite happy with them... I kept up with what
Altera was doing as well, and while it always seemed to me that for DSP
applications Xilinx tended to have the edge, in many ways Xilnx and Altera
were the Coke and Pepsi of FPGAs -- both were good, solid products where
either could have gotten the job done in the vast majority of applications.

Where I am now there's been some historical use of the Actel 54SX parts,
something I've never used.  However, I do recall that -- as of a few years
ago -- the deal with Actel was always that the parts were antifuse-based, so
while you _might_ be able to gain something in speed, you gave up a lot in the
way of being able to issue field upgrades, bug fixes, etc.  However, I now see
that Actel has their ProASIC line of parts so they can perhaps compete
somewhat closer to Xilinx and Altera than previously.  Could anyone summarize
how the ProASIC parts stack up to the contemporary Xilinx and Altera parts?
(E.g., Xilinx Virtex II or 4, Altera Stratix II.)  In particular I'm
interested in:

-- DSP usage.  Things seemed to get a lot easier when Xilinx starrted
introducing fixed DSP blocks (e.g., multiply-accumulate blocks) within the
FPGA fabric.
-- Embedded processor usage.  I never used them, but Xilinx and Altera's
embeeded "soft cores" (microblaze and NIOS) both seemed pretty neat, and
Xilinx was offering ARM hard cores if you really wanted "big iron."
-- Debugging support.  Xilinx had some "soft probe" thing that would let you
poke around the internal nets of the FPGA as it was running, and I believe
Altera had something like this even before Xilinx.
-- Tool support.  I used to use Synplify for VHDL synthesis, which worked
quite well.  I tried Xilinx's built-in synthesis tool, and given the price
(vs. Synplify), it was really pretty good as well.

How does Actel performs in these area?  I realize they're very general
questions, but I'm trying to get a feeling for how viable ProASICs are for
something like a software defined radio (i.e., plenty of "real" DSP, desire
for some "supervisory" soft core CPU, etc.) vs. just going with what I know
would work -- Xilinx or Altera.

Thanks,
---Joel Kolstad



Article: 86808
Subject: Re: Spartan-3e order of availability?
From: "Andrew FPGA" <andrew.newsgroup@gmail.com>
Date: 6 Jul 2005 20:09:37 -0700
Links: << >>  << T >>  << A >>
If the 200 part die is pad limited then the die size(and therfore
cost?) is more closely related to the number of pads(IO) rather than
the amount of logic.

Maybe the 400 is not pad limited.

Who knows how Xilinx do their pricing, if its based on value to the
customer - maybe IO is more important to the customer than logic at
those logic densities.

If you are looking at small production volumes I would choose a single
part to minimise development cost. If larger volumes then I would have
thought this pricing is not so relevant anyway.


Article: 86809
Subject: Re: Spartan-3e order of availability?
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 6 Jul 2005 20:51:36 -0700
Links: << >>  << T >>  << A >>
It used to be that packages were simple and cheap. The TQ144 is really
just a lead-frame for direct bonding to the die pads, and some plastic
on either side.
FT256 is a much more complicated package, a multi-layer pc-board at the
bottom that routes all die pads from the periphery to their individual
locations that are evenly spread over the package area. And the routing
is done with attention to the characteristic impedance, to avoid
reflections.
The result is much better signal integrity, and a smaller packege, i.e.
potentially a smaller pc board.
You pay for that with a few dollars at these single-quantity prices.
Of course far less in production quantities...

When it comes to really large, 1500-ball packages, there are:
10 metal layers on the die, 10 metal layers in the package, and perhaps
10 to 20 layers in your pc board.
Maybe the electrons go dizzy with all this complicated routing...
Peter Alfke


Article: 86810
Subject: Re: Cheking out Linux Kernel Source
From: Peter Ryser <peter.ryser@xilinx.com>
Date: Wed, 06 Jul 2005 21:05:41 -0700
Links: << >>  << T >>  << A >>
A good source is the MontaVista Linux Preview Kit for the ML300 board 
available from http://www.mvista.com/previewkit

The preview kit includes tools and Linux kernel and is free.

- Peter


Sewook Wee wrote:
> Hello,
> 
> I am using VIIPro on ML310 board, and trying to port Linux on it.
> While I was trying to check out the Linux Kernel Source using 
> BitKeeper(BK), it complained that BK is not free anymore.
> 
> Is there anyone who knows where can I get the kernel source?
> The version that I need is v2.4.21.
> 
> Thank you.
> 
> Sewook Wee


Article: 86811
Subject: Re: PS/2 interface
From: "greenplanet" <greenplanet@hotmail.com>
Date: 6 Jul 2005 23:06:40 -0700
Links: << >>  << T >>  << A >>
I've visited the xess website; however, there's only one example for
mouse and the source codes are in Spanish.  Anyways, I tried to figure
out what those codes mean and downloaded the bitstream to the fgpa;
however, that doesn't work.  I am not sure whether the code is not
working or I have set something wrong.  Anybody has experience using
the PS/2 port of XSA-3S1000 board with XST 3.0?
If I just wanna read the mouse, do I have to initialize the mouse
first? If then, how?


Article: 86812
Subject: Re: PC104 (ISA) bus in FPGA (Spatan 2E)
From: =?ISO-8859-1?Q?Johan_Bernsp=E5ng?= <xjohbex@xfoix.se>
Date: Thu, 07 Jul 2005 08:54:42 +0200
Links: << >>  << T >>  << A >>
amko wrote:
> Hello!
> 
> Currently I design FPGA design which will have pc104(ISA) bus. First at
> all I cannot find detailed ISA bus specification on Internet (I think
> for free).
> Also PCI to ISA bus bridge(national: CS5530) which is located on
> processor card (that I use) and generate PC104 timing does not contain
> any useful information in datasheet.
> 
> I read on this forum a lot about ISA bus and I am little confused :)...
> if ISA bus signals are synchronized on ISA bus clock or are received
> and transmitted  on (rising ?)edge of IOR# and IOW# signals.
> Also I am not sure If I need address latch signal (BALE) or I can latch
> address bus on IOR# and IOW# signals???
> 
> 
> I see example: http://www.jacyltechnology.com/documents/AP002.pdf
> and it is all synchronized to PC104 clock signal...... Is it only
> special case??
> 
> In my design FPGA must act as slave on ISA bus and should support 8-bit
> and 16-bit I/O mode and DMA.
> 
> So my question is where I can get detailed ISA bus specification (free
> :)) and how much this specification are depend on devices.. I think
> setup time, hold time...
> How is better to implement PC104 bus design sync or async? (Here I also
> have in mind possible problems with async design if i change FPGA)
> 
> Thank you and regards,
> 
> AMIR
> 


Hi Amir,

When I did my masters project a while back I did have some good use of 
ISA System Architecture by Tom Shanley and Don Anderson. They've also 
writen a book on EISA. You should be able to find it in almost any 
academic engineering library. If you need a review on the timing details 
of a standard 16-bit I/O device ISA cycle you can have a look in my 
report: http://www.ep.liu.se/exjobb/isy/2004/3440/exjobb.pdf
I didn't look anything into DMA though, but the book I mentioned covers 
that.

/Johan

-- 
-----------------------------------------------
Johan Bernspång, xjohbex@xfoix.se
Research engineer

Swedish Defence Research Agency - FOI
Division of Command & Control Systems
Department of Electronic Warfare Systems

www.foi.se

Please remove the x's in the email address if
replying to me personally.
-----------------------------------------------

Article: 86813
Subject: about fast adder
From: "Giox" <giovanniparodi79@yahoo.it>
Date: 7 Jul 2005 00:37:07 -0700
Links: << >>  << T >>  << A >>
I'm interested in the implementation of a fast adder for 32 bit data.
The CLA is too expensive so I'm searching for something different, can
you provide me some reference?
I think that Ling adder can be a good choice, but I don't know..
Thanks a lot


Article: 86814
Subject: Re: fastest FPGA speed grade? Not the only measure, but ...
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 07 Jul 2005 09:15:15 +0100
Links: << >>  << T >>  << A >>
Austin Lesea <austin@xilinx.com> writes:

<snip>
> http://www.xilinx.com/products/virtex4/overview/performance.htm
> 
> is a good review of V4, which illustrate how we beat all other FPGAs
> in EVERY category.
> 

Interesting - why did you not use Synplify for the Altera side of
things - was it worse than Altera's synthesiser?

Cheers,
Martin

-- 
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

Article: 86815
Subject: Re: Xilinx Virtex 4 device technology
From: Kolja Sulimma <news@sulimma.de>
Date: Thu, 07 Jul 2005 12:22:34 +0200
Links: << >>  << T >>  << A >>
Austin Lesea schrieb:

> In order to remove or minimize the variation in timing in SOI from the
> floating wells, one needs to add taps.  The addition of the taps to
> every well, results in the area increasing dramatically.  That makes the
> FPGA cost too much, hence the process is not commercially viable.  This
> has been one of the reasons for its non-use.

Also, without knowing as much detauls as austin, I suspect that in a
design as heavily dominated by interconnect as an FPGA the area increase
results in longer wires which increases capacitance and therefore power
consumption and delay. This mitigates the two main advantages of SOI.

Kolja Sulimma

Article: 86816
Subject: Re: ppc 405 in debug halt mode
From: jagadeesh <reddy.jagadeesh@gmail.com>
Date: Thu, 7 Jul 2005 03:27:45 -0700
Links: << >>  << T >>  << A >>
hello...any pings to my above problem is highly appreciated....

thanking you

jaggu

Article: 86817
Subject: Problems with Timing Simulation
From: ALuPin@web.de
Date: 7 Jul 2005 03:30:08 -0700
Links: << >>  << T >>  << A >>
Hi,

I have performed a functional simulation and static timing analysis
of my design. Both are OK.

But when trying to perform timing simulation my state machine
does not change from the first state.

I have an external asychronous Reset which I sychronize ...
In the following code "Rst90_n" is the synchronized Reset.
What could go wrong?

PROCESS(Rst90_n, Clk90)
 BEGIN
   IF Rst90_n='0' THEN
      ls_ddr_state           <= s_ini_a;
      ...

   ELSIF rising_edge(Clk90) THEN
      ls_ddr_state           <= next_ls_ddr_state;
      ...
   END IF;
 END PROCESS;

 PROCESS( ls_ddr_state,...)


 BEGIN
   next_ls_ddr_state           <= ls_ddr_state;
   ...


   CASE ls_ddr_state IS

        WHEN s_ini_a => next_ls_ddr_state <= s_ini_b;
             next_ls_ddr_csn <= '1';
        WHEN s_ini_b => next_ls_ddr_state <= s_ini_c;
             next_ls_ddr_csn <= '1';
        WHEN s_ini_c => next_ls_ddr_state <= s_ini_d;
             next_ls_ddr_csn <= '1';
        WHEN s_ini_d => next_ls_ddr_state <= s_init0;
             next_ls_ddr_csn <= '1';
        WHEN s_init0 =>
             -- first actions
             ...

   END CASE;
 END PROCESS;


Article: 86818
Subject: SELV - power supply specification
From: "vssumesh" <vssumesh_asic@yahoo.com>
Date: 7 Jul 2005 03:45:08 -0700
Links: << >>  << T >>  << A >>
Hello i bought a development board frm the ARM. It says that for safety
use SELV (safety extra low power supply). Whats mean by SELV. Can i use
home made power( using 7805 and 3.3V zener) supplies insted of SELV.


Article: 86819
Subject: Re: EDK 6.3, Xilinx ML40x ML402, XBD files
From: abgoyal@gmail.com
Date: 7 Jul 2005 04:04:00 -0700
Links: << >>  << T >>  << A >>
HI Allan,

I am myself looking for the same. Am using EDK6.3/ISE6.3i. I am also
told that there is no XBD included even in EDK7.1 for the ML402 board.

Allan, were you able to build the reference design without any errors?
For me, the reference design generates lots of errors about unavailable
versions of peripherals referenced in the design. What service packs
are you using. 


Any help appreciated. 

TIA,

Abhishek


Article: 86820
Subject: Re: PowerPC interrupt
From: Andi <00andi@web.de>
Date: Thu, 7 Jul 2005 04:28:13 -0700
Links: << >>  << T >>  << A >>
Hi,

how is the interrut signal specified? As low or high activ edge/level ?

How does the mhs file look like?

Article: 86821
Subject: Re: SELV - power supply specification
From: fred <not@for.mail>
Date: Thu, 07 Jul 2005 11:49:06 GMT
Links: << >>  << T >>  << A >>
In article <1120733108.522325.183490@g44g2000cwa.googlegroups.com
>, vssumesh <vssumesh_asic@yahoo.com> writes
>Hello i bought a development board frm the ARM. It says that for safety
>use SELV (safety extra low power supply). Whats mean by SELV. Can i use
>home made power( using 7805 and 3.3V zener) supplies insted of SELV.
SELV only describes the user safety aspects of the supply, you can use
any mains isolated supply that meets the voltage and current requirements
of the board.
-- 
fred

Article: 86822
Subject: Re: Problems with Timing Simulation
From: "Ben Jones" <ben.jones@xilinx.com>
Date: Thu, 7 Jul 2005 12:51:21 +0100
Links: << >>  << T >>  << A >>
> I have performed a functional simulation and static timing analysis
> of my design. Both are OK.
> But when trying to perform timing simulation my state machine
> does not change from the first state.
> What could go wrong?

If you are using the Xilinx ISE tools, then the post-map and post-PAR
simulation models will model the "power-on reset" of the FPGA for you
automatically (this is completely separate from any user-defined reset
signal you might have in your design).

When you generate the simulation models, there is a setting called "Reset On
Configuration Pulse width" which defines how long (in nanoseconds) the
synchronous elements will wait in their "INIT" states before responding to
clock edges. So, it could be that you just need to make your testbench wait
for a few hundred nanoseconds before doing anything (or reduce the value of
this pulse width when you create the model).

Hope this helps,

        -Ben-



Article: 86823
Subject: Re: Program from external memory
From: "Joey" <johnsons@kaiserslautern.de>
Date: Thu, 7 Jul 2005 13:56:41 +0200
Links: << >>  << T >>  << A >>

I dont have a ACE CF on my board. Well, I have the ACE connector, but no
card reader/card

"Peter Ryser" <peter.ryser@xilinx.com> schrieb im Newsbeitrag
news:42CC13E2.2060906@xilinx.com...
> Since you have System ACE CF in your system that is the easiest way to
> load both bitstream and ELF file. Please read up in the EDK
> documentation how to generate an ACE file for your system.
>
> - Peter
>
>
> Andi wrote:
> > Hi,
> >
> > do you want to run the program out of sdram or out of the bram? What is
the size of the c-code? Do you use the edk system as top level? Or do you
integrate the edk system in your own top level?
> >
> > The tool flow from edk supports the mechanism to fit the c-code ->
elf-file in the bram during the bitgen procedure.
> >
> > Then when the fpga is loaded the c-code starts directly.
>



Article: 86824
Subject: Re: EDK 6.3, Xilinx ML40x ML402, XBD files
From: =?ISO-8859-1?Q?Johan_Bernsp=E5ng?= <xjohbex@xfoix.se>
Date: Thu, 07 Jul 2005 14:00:07 +0200
Links: << >>  << T >>  << A >>
abgoyal@gmail.com wrote:
> HI Allan,
> 
> I am myself looking for the same. Am using EDK6.3/ISE6.3i. I am also
> told that there is no XBD included even in EDK7.1 for the ML402 board.
> 
> Allan, were you able to build the reference design without any errors?
> For me, the reference design generates lots of errors about unavailable
> versions of peripherals referenced in the design. What service packs
> are you using. 
> 
> 
> Any help appreciated. 
> 
> TIA,
> 
> Abhishek
> 

I don't know who told you that the XBD for ML402 isn't included in 
EDK7.1, it is included in my EDK7.1 (sp 1). I was also able to build it 
and run it on my board without changing anything or experience any sort 
of error. I guess this is not very helpful indeed, but at least I can 
say that it works using sp1...

cheers!
Johan


-- 
-----------------------------------------------
Johan Bernspång, xjohbex@xfoix.se
Research engineer

Swedish Defence Research Agency - FOI
Division of Command & Control Systems
Department of Electronic Warfare Systems

www.foi.se

Please remove the x's in the email address if
replying to me personally.
-----------------------------------------------



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search