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Hi! I have a big FIFO chip covered by dust, that I'd like to finally use. The most useful application I'm imagining for it is to finally make myself a logic analyzer. This FIFO (Texas Instruments SN74V3690-6PEU) is a 3.3V device, but has 5V tolerant inputs. "Great!" I thought. What I'm asking you is: should I connect the probes (just a header cable) directly to the FIFO, or should I use an high speed buffer inbetween? Consider that the chip is specced at 166MHz. Moreover, what is the cheapest way to produce a variable clock speed up to 166MHz (and possibly beyond, for other applications)? A PLL? Any chip you may suggest me? Thanks! TPMArticle: 83001
Hello > Hi Austin, > > thanks for the answer. > > >No such thing. Any OBUF can duplicate a clock by using the DDR FF. > >Tie the top FF D input to a '1', and the bottom FF D input to a '0', > >and on the rising edge you will get an outgoing rising edge, and on > the >falling edge you will get an outgoing falling edge. > > How can I set the FF connections in the IOBs manually? In the lib.pdf I > find only how to instantiate an OBUF, however I can only choose an input > and output there. > > With this construction I have only a single clock, not a differential > clk_n and clk_p. Is this correct? > > Shouldn't I generate the differential outgoing clock signal using a > OBUFDS where I have just the clk_n or clk_p input. I think you should, if you want full LVDS link. About input LVDS pair clock... It could be placed in ordinary input pair I/O P&N, don't forget about termination resistors on PCB. Look at Phase Alignment on xilinx website, 300MHz is not a toy. Best regards Jerzy GburArticle: 83002
Does anybody know a SystemC to VHDL Compiler with a reasonable price? Maybe special prices for universities? Falk S.Article: 83003
Hi Daryl, I already knows the stuff from xilinx, i was actually aiming for stuff like tutorials and HDL code examples. Regards, Moti.Article: 83004
Are there any official documents dealing with HDLs (Hardware description languages like VHDL, Veriolog, SystemC,...) in safety critical applications? Regards Falk S.Article: 83005
Sebastian Weiser wrote: > On Tue, 19 Apr 2005 16:51:50 -0400, Brijesh wrote: > > >>I sample the strobe signal at 133MHz and detect the edge. That way I kno >>w when new data is present on the IOB's. > > > So you have a clock domain crossing here. Could it be a problem of > metastable flipflops? What are your constraints of the inter-domain > paths? How many stages has your synchronizer logic? I use two stages to synchronize the Strobe signal. I doubt its metastable issue. Cause there are 8 channels of IDE and only one channel always gives the error. It cannot be that selective :-). One thing that points this not being metastable issue or synchronization issue is that, the frequency of CRC errors seems to be data dependent. By that I mean, the CRC errors occur more frequently when data toggles a lot of bits. Iam rigging up test to check this more thoroughly. New observation is that new model of hard disks are more prone to CRC errors than older ones I was testing with. Probably they have stronger drivers :-). Will find out once I have scope to properly measure the rise time and ringing. I will also try out what Peter suggested, regarding checking for double clocking. I have been hesitant to make code changes or a new place and route before understanding the issue. But now I guess I am pretty confident there is nothing wrong in the design and/or timing constraints. So will go ahead with above changes. Once again thanks for all the help. Brijesh > > > SebastianArticle: 83006
Kolja, I respectfully disagree. If I want a uP, I can optimize it until I have only those transistors I need. If the job is to run any program whatsoever, I can not choose to implement just the logic I need, as that would be an infinite amount fo logic (for an unbounded set of programs). Now that I have an instruction set defined, it takes far more transistors to do the same in a FPGA, than in a ASIC uP (or ASSP uP). Austin Kolja Sulimma wrote: > Not really related to the original question but intresting nonetheless: > > austin wrote: > > >>FPGAs have long been known to take thirty transistors to do the job of a >>single transistor in an ASIC. The same is true for a microprocessor. It >>takes many more tranistors to the the job in an FPGA, than it does in a uP. > > > That is not entirely true. > Similar to FPGAs uP are extremly inefficient because they are universal. > > If I want to add two numbers in a uP, something that basically takes a > few dozen gates, thousands of of gates start working. Lot's of stuff > that is there to preform the ISA abstraction like instruction > reordering, scoreboards and reservation stations. Security measures like > MMU, and stuff to hide memory access time like caches and translation > lookaside buffers. At the same time many, many more gates are sitting > around idle like unused cache parts and unused execution units. > In a high and processor it takes half a billion transistors to execute > something like six operations per clock cycle. > But it is universal an can run any algorithm any time. > > On the other extreme you have an asic implementation of the algorithm > that only does work that is required for the task but can do nothing > else. This of course is a lot more efficient. (By a factor of 100.000 or > so for many algorithms) > > The FPGA is a compromise between the two. It can use asic like > algorithms getting away without all the CPU overhead stuff but you have > to pay the factor of thirty for the implementation because you can > change the algorithm universaly. > > As a result it takes a lot - and I mean a lot - less transistors per > operation e.g. to perform a smith-waterman computation in an FPGA than > in a uP. > > > Kolja SulimmaArticle: 83007
Here is code snippet for generating clock using DDR filpflops and LVDS
output.
clkn <= not clk;
Instantiate DDR flip flops. clk_out is now a replica of clk signal but
with same delay as the data bits being clocked out using clk signal.
U1 : FDDRRSE
port map ( Q => clk_out,
C0 => clk,
C1 => clkn,
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0'
);
Use LVDS buffers for clk_out signal. In UCF file lock the location of
atleast the clk_out_p which is the P output of the LVDS signal.
U2 : OBUFDS_LVDSEXT_33
port map(
I => clk_out,
O => clk_out_p,
OB => clk_out_n
);
I think its not necessary to instantiate the LVDS buffer. If you chose
the drive type as LVDS in the UCF file, its automatically taken care of.
Need to cross check.
Brijesh
> Hi Austin,
>
> thanks for the answer.
>
> >No such thing. Any OBUF can duplicate a clock by using the DDR FF.
> >Tie the top FF D input to a '1', and the bottom FF D input to a '0',
> >and on the rising edge you will get an outgoing rising edge, and on
> the >falling edge you will get an outgoing falling edge.
>
> How can I set the FF connections in the IOBs manually? In the lib.pdf I
> find only how to instantiate an OBUF, however I can only choose an input
> and output there.
>
> With this construction I have only a single clock, not a differential
> clk_n and clk_p. Is this correct?
>
> Shouldn't I generate the differential outgoing clock signal using a
> OBUFDS where I have just the clk_n or clk_p input.
>
> regards,
> Benjamin
Article: 83008CODE_IS_BAD wrote: > Hi all... > i have been trying to simulate some code in which there is a data bus > that is declared to be of INOUT type. I have simulated my VHDL code and > for both read and write operations it works fine, also the data bus > gets tri-stated (Z) when not in use. > Now this simulation was done by directly putting the values of signals > in the ModelSim environment. Then I thought to write a testbench to > simulate the same. In this case when I write some data on the databus > it does not get tri-stated when not in use. So i tried to debug the > problem and found that since in my testbench I am forcing some value on > the bus say '3B' and also in code i force 'Z' when not in use, then > STD_LOGIC being a resolved type resolves the value and gives '3B' since > 'Z' has got least priority. Your test bench also needs to behave properly and put a 'Z' out when it has relenquished the control of the bus and not continue forcing '3B'. Brijesh > Why it worked directly on ModelSim environment was bcoz i was > "Depositing" the value on bus and not "Freezing" it. If i freeze the > value there then in that case also i cud not make the bus tri-stated. > > So i would like to know how in our testbench we can write code such > that i can see all the correct results. I think in practice this will > work fine but it's better if in simulation also we can see the desired > results. Hope somebody can help. Thanx a lot >Article: 83009
Hi People, I am interested to build AND gate (as neural network) using FPGA. I am using Xilinx webpack 7. If anyone can advice on how can I build one using basic components such as adder, multiplier.. lookup table etc... thanks in advance. JohnArticle: 83010
Symon wrote: > I use blowers from http://www.sunon.com/english.htm > HTH, Syms. > <junkmail@fastertechnology.com> wrote in message > news:1112969312.502975.189710@o13g2000cwo.googlegroups.com... > >I am looking for heat sinks with an attached fan for use on a Xilinx > > FF1152 package on a PCI card. Thank you Symon. Sunon also has the fan sink combination that I am interested in. An FAE also pointed me to a Xilinx user guide that has a list of heat sink vendors, ug112.pdf page 74. I have considered using a blower such as the Sunon or Delta models, but I really want to save that extra board space for other stuff. Regards, John McCaskill.Article: 83011
hello Brijesh... yes yaar i have already done that... But i wanted to know wether there is any mechanism with which we can also u know 'deposit' values instead of 'freezing' it as we do in modelsim. Waise thanx again for the suggestion. PuneetArticle: 83012
"soos" <marcsok@yahoo.com> wrote in message news:1114079555.335373.322570@g14g2000cwa.googlegroups.com... > The LVDS is a rather exotic option which requires special handling > compared to USB2.0 and TCP/IP. Hi! Since Ron seem to be away ATM, I'll offer this explanation: Like mentioned, LVDS is simply an electrical signalling standard. USB defines both an electrical interface and a binary communication protocol, and TCP/IP defines a communications protocol usually using Ethernet as the electrical interface. So yes, it will probably be easier for you to use USB or TCP/IP. There are some very easy to use chips out there, that are designed to integrate USB and/or TCP/IP into your design without you having to know the details of the protocols. Amongst these are specially adapted microcontrollers (or modules) with "everything" built in, including the electrical interface and the software protocol stack. Talking to (through) these chips can be as simple as just reading and writing your data from/to a serial or paralell port, and the chip will handle buffering, transmission and reception transparently. DJ --Article: 83013
"soos" <marcsok@yahoo.com> wrote in message news:1114079555.335373.322570@g14g2000cwa.googlegroups.com... > With the new information it seems that if my main goal is to transfer > data into a pc (putting the TS aside for a moment) then in this > perspective > The LVDS is a rather exotic option which requires special handling > compared to USB2.0 and TCP/IP. Actually, as far as total transistor count/lines of code goes, LVDS is utterly trivial to use compared to USB or TCP/IP. However, the fact that USB and TCP/IP and the associated software come with your PC already tend to weight the choice in their favor. LVDS is quite popular for communication between various embedded devices, however, that don't already have the hardware and/or software to do USB or TCP/IP.Article: 83014
Moti Cohen wrote:
> I already knows the stuff from xilinx, i was actually aiming for stuff
> like tutorials and HDL code examples.
Start by reading some data sheets of real CAMs:
http://www.google.com/search?q=content+addressable+memory+data+sheet+CAM
There are not many HDL level code examples
because a CAM does not fit well in an FPGA.
The basic idea is to search through a
register array to match an input tag
in one clock cycle. The read code is just a
FOR loop. The problem is the large amount
of wiring and logic generated between all the
register outputs and the match bit.
What will fit in an FPGA is a very small
array at a very low Fmax compared to
an off-the-shelf CAM.
-- Mike Treseler
Article: 83015"ALuPin" <ALuPin@web.de> wrote in message news:b8a9a7b0.0504202323.342f42e4@posting.google.com... <snip> > I am NOT talking of DQ with regard to DQS. > > I am talking about the bits of the bus DQ and the bits of the bus > DQS ! They have different tCO. > I already know DDR basics ;o) I'm still not answering your question but posing you another question: Are the clock-to-out times different by about 1/4 of your DDR clock period? I know that timing analysis from other vendors tend to illustrate timing from the positive edge of the appropriate clock. If the Lattice implementation uses a 2x clock for the data signals, the DQ "bus" and the DQS "bus" (neither of which are a bus, really - they're coupled into byte lanes) would be clocked on opposite edges of that clock. If the clock-to-out timing is referenced to the rising edge only, the difference would be half the 2x clock period. Is that what you're seeing? Either a Lattice FAE or timing report numbers published here might give others a better idea of what's happening.Article: 83016
Synplify DSP does indeed support multi-rate systems. It utilizes the sample rate capabilities that are native in the Simulink environment from The MathWorks. Synplify DSP fully understands all of a users sample rate designations, and will exploit this information to create an optimal implementation. All the designer needs to do is specify the sample rate on the design inputs. This can be done explicitly, or inherited from the signals that drive the system. Sample rates are then propagated automatically through all blocks, changing when requested through an upsample or downsample instance. All sample rates domains are derived automatically from this infrastructure, and Synplify DSP infers the required interface between sample domains during hardware implementation. It may even create a multi-rate system from a single-rate specification in order to achieve this most efficient hardware implementation. The goals is to ease the specification process through automation, and relieve the designer from the tedious tasks of system level clock definition and interface specification in a multi-rate design. Our product overview can be found here: http://www.synplicity.com/products/synplifydsp/index.html A white paper that may be more helpful can be found here: http://www.synplicity.com/literature/index.html#dsp I hope this helps. AndrewArticle: 83017
nospam@nospam.com wrote: > Hi! > I have a big FIFO chip covered by dust, that I'd like to finally use. > The most useful application I'm imagining for it is to finally make > myself a logic analyzer. This FIFO (Texas Instruments SN74V3690-6PEU) > is a 3.3V device, but has 5V tolerant inputs. "Great!" I thought. > > What I'm asking you is: should I connect the probes (just a header > cable) directly to the FIFO, or should I use an high speed buffer > inbetween? Consider that the chip is specced at 166MHz. > > Moreover, what is the cheapest way to produce a variable clock > speed up to 166MHz (and possibly beyond, for other applications)? > A PLL? Any chip you may suggest me? > > Thanks! > TPM > Why not a CPLD or FPGA. And do your own frequency synthesizer using an accumulator. For high speed accumulator, use pipeline methodology. Laurent www.amontec.comArticle: 83018
VHDL, Verilog and SystemC are HDL's They describe hardware.... If you have a safety critical application you would have to design the redundancy into your HDL model. You can insure the reliability of your design by: 1) Using a redundant polling method, where you have 3 identical logic paths and if two out of three paths agree that is your answer. 2) Run some built in self-test periodically to make sure the logic is what you think it is. As far as I know there is no inherent safety protocols built into any Development software, you must define the safety factors into your design. EricArticle: 83019
Miron Abramovici, Melvin A. Breuer, Arthur D. Fiedman "Digital Systems Testing and Testable Design", Wiley-Interscience, 1990. This is a good book for designing Built in self test into you HDLs. EricArticle: 83020
In article <3cq8miF6qu5etU1@individual.net>, Mike Treseler <mike_treseler@comcast.net> wrote: >Moti Cohen wrote: > >> I already knows the stuff from xilinx, i was actually aiming for stuff >> like tutorials and HDL code examples. > >Start by reading some data sheets of real CAMs: >http://www.google.com/search?q=content+addressable+memory+data+sheet+CAM > >There are not many HDL level code examples >because a CAM does not fit well in an FPGA. >The basic idea is to search through a >register array to match an input tag >in one clock cycle. The clock cycles for commercial CAMs seem pretty long; I wonder whether a solution that stored the data in the first part of each of a large number of block RAMs, with a very simple counter for addresses and a comparator, running at a much quicker internal clock, might get better results. This feels as if it could be made a bandwidth problem, and FPGAs lack not in bandwidth. I suppose block RAMs are seldom wide enough; this feels like a case where Altera's 512-bit memory blocks might come into their own [OK, you need four to store a 64-bit word; with 318MHz not-to-exceed speed, you probably can't fit more than 16 words per set of four blocks if you want clock rates competitive with the 20Mhz of MUSIC; but you could fit sixteen sets of four blocks on even the smallest Stratix]. Though that's 256x64, whilst MUSIC offers 4096x64 in their larger devices. TomArticle: 83021
Have anyone got Impact working in Fedora Core 3? Or any similar Linux? I have tried this: http://www.fpga-faq.org/FAQ_Pages/0044_Xilinx_Parallel_on_Linux.htm but I probably get 1000 compile errors. Is there any other possibilities for programming xilinx FPGA's? I have read about NAXJP but can't find any places to download it, I have tried http://www.nahitech.com/nahitafu/naxjp/naxjp-j.html#down but can't find any links to click on to download it. I'm using a spartan 2E at the moment. Why don't just Xilinx program against the parallelport in user-space (ppdev) Instead of having two drivers?? TEGArticle: 83022
Trond Egil Gran <nospam@for.me> writes: > Have anyone got Impact working in Fedora Core 3? Or any similar > Linux? I have an old RH8 based machine which I have connected to my device under development in the lab. I run impact in batch mode (even from home). This was an old celeron which I saved from the recycling bin. > Is there any other possibilities for programming xilinx FPGA's? I've made a prototype for an Ethernet-based programmer. I simply upload my embedded programming file using tftp hence no device driver is required, only a tftp client. Keep an eye www.etherblaster.com for progress information (I'm doing this on my spare time so I'm moving slowly). Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 83023
I have run into a roadblock with my project. Trying to get the PPCs in the V2P to share a BRAM. I have gotten it to work via the PLB bus (both PPCs with their own bus, each bus connected to the same BRAM), but haven't been able to make it work via the DSOCM. I followed pretty much the same steps to connect both DOCM buses to the same BRAM as I did for the PLB set up, but it seems that writes are not working. I get no errors, but every write fails (can check the contents via XMD--always 0x0). Tried looking at some Xilinx-provided designs for clues/inspiration to no avail. Is there some nuance to the OCM stuff that I am missing? I have gone through the OCM documetation, but if anyone thinks they know what I have missed or what I need to do to fix this, I would appreciate any advice. I can provide more details if helpful... Thanks, JoeyArticle: 83024
Have you simulated the design? Paul Joseph wrote: > > I have run into a roadblock with my project. Trying to get the PPCs in > the V2P to share a BRAM. I have gotten it to work via the PLB bus > (both PPCs with their own bus, each bus connected to the same BRAM), > but haven't been able to make it work via the DSOCM. I followed pretty > much the same steps to connect both DOCM buses to the same BRAM as I > did for the PLB set up, but it seems that writes are not working. I > get no errors, but every write fails (can check the contents via > XMD--always 0x0). Tried looking at some Xilinx-provided designs for > clues/inspiration to no avail. > > Is there some nuance to the OCM stuff that I am missing? I have gone > through the OCM documetation, but if anyone thinks they know what I > have missed or what I need to do to fix this, I would appreciate any > advice. I can provide more details if helpful... > > Thanks, > > Joey
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Compare FPGA features and resources
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