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Messages from 83575

Article: 83575
Subject: Re: 200+ MHz through a SCSI cable
From: =?ISO-8859-1?Q?Benjamin_Menk=FCc?= <benjamin@menkuec.de>
Date: Tue, 03 May 2005 18:17:14 +0200
Links: << >>  << T >>  << A >>
Hi,

after I set the optimization effort to "high", I can get the whole 
270MHz now (thats all the DCM can generate out of 100 MHz).

Any comments how to make my design better are still welcome though :)

regards,
Benjamin

Article: 83576
Subject: Re: Force sequential assigment
From: "Berty" <wooster.berty@gmail.com>
Date: 3 May 2005 09:40:49 -0700
Links: << >>  << T >>  << A >>
When you say you want the count to inc after the correct data for
example do you mean one clock later so when correct data is inc the
count will keep it value for this clock duration or you mean that you
simple want to see in the simwave or what ever waveform you use that
the state get change later.
If it is mearly for visual than you can use after the <= #1 or #2 etc
HOWEVER keep in mind that using different value can cause simulation to
look correct but work incorrect in real. I would strongly advise use
only #1 for continent for all FF's and not play with different
values.
If on the other hand you want the count not to increment while
incorrect or correct get update than your code is somewhat unclear in
the sense that as long as count is below 255 either correct or
incorrect get update so your count will never count if you want to
prevent it in those both cases.

You might also want to consider unless you are working in really high
speed changing the code so your code use only one incrementor and not
two.

For example instead of

If (a)
   x <= x + 1
else
   y <= y + 1

write something like

inc_var = a ? x : y
inc_tmp = inc_var + 1'b1

If (a)
   x <= inc_tmp ;
else
   y <= inc_tmp ;

Have fun.


Article: 83577
Subject: I got it!
From: =?ISO-8859-15?Q?Benjamin_Menk=FCc?= <benjamin@menkuec.de>
Date: Tue, 03 May 2005 18:42:33 +0200
Links: << >>  << T >>  << A >>
Hi,

I am running my design now with two dcms cascaded. The max. clk2x output 
of my device is 360 MHz, which I am using now. That gives me for my LCD 
panel a frame rate of about 54 Hz, still not too much. Maybe I have to 
switch to a faster speed grade or experiment with external clocks.

regards,
Benjamin

Article: 83578
Subject: Re: JTAG without parallel port
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Tue, 3 May 2005 18:03:03 +0100
Links: << >>  << T >>  << A >>
Digilent have a low cost USB cable listed. Can not confirm if it is good or 
bad as I have yet to play with one.

John Adair
Enterpoint Ltd. - Home of low cost FPGA Development Board MINI-CAN.
http://www.enterpoint.co.uk


"Rafa" <rafaelgonzalez@ono.com> wrote in message 
news:4vxde.37140$dr.24490@news.ono.com...
>I have a Xilinx Spartan 3 board, and comes only with the parallel JTAG 
>cable. My big problem is that any of my computers have parallel port, and I 
>can't program it. As I work with a desktop and a laptop I had to discard 
>buying a pci parallel card. I know that they have an usb and serial cable, 
>but are very expensive and the shipping too. I'd like to know if there is 
>any alternative, such as a homemade serial or usb cable, or if any of those 
>parallel-to-usb adapters work with this.
>
> Thanks
> 



Article: 83579
Subject: Re: Xilinx input path: Why does the optional delay element with inputFF help me?
From: "Peter Alfke" <peter@xilinx.com>
Date: 3 May 2005 10:26:41 -0700
Links: << >>  << T >>  << A >>
Preben, here again, slowly:
The input flip-flop is different, since it gets its data from the
outside, not created by the internal clock.

The delay from the chip's clock input  to the clock arriving at the
input flip-flop (or any other flip-flop) is much longer than the delay
between Data input to arriving at the D input of the input flip-flop.
The clock must drive thousands of destiantions, the data only one.

Whenever the clock arrives later than the data, data must be held (hold
time) which is an ugly parameter that most flp-flops do not specify.

That's why it helps to delay the data input, and Xilinx has done that
for the past 18 years on all our parts, but in Virtex-4 it has become
much more sophisticated.
Peter Alfke


Article: 83580
Subject: Re: Performing Readback from Impact
From: Neil Glenn Jacobson <n.e.i.l.j.a.c.o.b.s.o.n.a.t.x.i.l.i.n.x.c.o.m.>
Date: Tue, 03 May 2005 10:33:03 -0700
Links: << >>  << T >>  << A >>
Antti,

I didn't say it was impossible.  I said it wasn't supported :-)


Antti Lukats wrote:
> Hi Neil,
> 
> I think what you say is not entirely correct - impact doesnt do FPGA
> readback, not because it can not support it because Xilinx decided not to
> include this feature (available to the user).
> 
> doing verify with FPGA in iMpact actually DOES readback of FPGA into
> internal buffer, then compares it to the .BIT file using the .MSK file and
> then trashes the internal readback. So the FPGA readback is internally used
> by impact, just the readback can not be saved to a file.
> 
> sure the readback would not be the same as the programmed bitstream if the
> FPGA has been started, eg you would only get the proper .bit being read if
> the readback is done after JTAG configuration, but before jstart
> instruction, which I agree would be very rare case indeed. So I kind of
> understand why the FPGA readback is 'left out' from impact, but it doesnt
> mean its not possible. the usefullness of the readback is sure a question,
> there are only a few cases where it could be useful.
> 
> Antti
> 
> 
> "Neil Glenn Jacobson" <n.e.i.l.j.a.c.o.b.s.o.n.a.t.x.i.l.i.n.x.c.o.m.>
> schrieb im Newsbeitrag news:d569t5$qaa2@cliff.xsj.xilinx.com...
> 
>>Praveen,
>>
>>The readback operation is supported in iMPACT only for PROMs and CPLDs
>>in Boundary-Scan and Desktop modes.  Since iMPACT is a generic Xilinx
>>device configuration tool it indicates the complete set of operations
>>available for ALL devices but disables the ones that are not supported
>>for the selected device.
>>
>>This is not unusual.  For instance, in "Word" you may not be able to Cut
>>or Paste a protected document yet the operation is visible but disabled.
>>
>>
>>Praveen wrote:
>>
>>>Thanks Glenn. Why list that option when we can't use it? ;). I read in
>>>the Impact help file that it can be used when using desktop
>>>configuration mode. But, I read elsewhere (in Xilinx help file) that
>>>suggested it can be used in SMAP and JTAG config modes. Doesn't make
>>>any sense.
>>>
>>
>>
>>-- 
>>
>>     *CAUTION:* Shameless self-promotion follows...
>>
> 
> 
> 


-- 

     *CAUTION:* Shameless self-promotion follows...


Article: 83581
Subject: Multiply Accumulate FPGA/DSP
From: "bart" <larsonbr@gmail.com>
Date: 3 May 2005 11:04:52 -0700
Links: << >>  << T >>  << A >>
I have been tasked with trying to implement a FFT algorithm in a
FPGA/DSP architecture.  The algorithm would be a N point FFT with 1000
frequency bins.  Each frequency bin would require a multiply, by the
constant e^jx, and then accumulate every 1 microsecond.  This turns out
to be 1000 multiply accumulates happening in parallel every 1
microsecond.  Does anyone have experience doing something similar in an
FPGA/DSP and can they point me in the  right direction as far as
choosing a FPGA/DSP development board?  Any help would be appreciated.


Article: 83582
Subject: Re: JTAG communication Problems in Quartus using Signal Tap
From: Markus Knauss <markus.knauss@gmx.net>
Date: Tue, 03 May 2005 19:08:13 +0100
Links: << >>  << T >>  << A >>
> Hi Markus,
> I use 1k pullup ,pulldown.
> I had some problems with 10k pulldown on TCK.
> The following is from "ALTERA Support Find Answers":

Hi Thomas,

thank you for the hint.

Today I have tried 1k pulldown on TCK. The result was even worse.
The TCK signal breaks down to 2V.
I get the jtag comm errors earlier.

Maybe my USB Blaster has a defect.

With the Byteblaster MV it works also with 1k on TCK.

Regards

Markus

Article: 83583
Subject: Re: JTAG communication Problems in Quartus using Signal Tap
From: Markus Knauss <markus.knauss@gmx.net>
Date: Tue, 03 May 2005 19:13:19 +0100
Links: << >>  << T >>  << A >>
> Is the flex-cable soldered directly on the pcb of USB Byteblaster?
> How is this flex cable connected to the USB ByteBlaster?
> 
> Thanks,
> Larry

Hi Larry,

I opend the case (there is just one screw and no warranty seal).

The flex cable is connected to the usb blaster PCB with a 10 pole 
connector (2 x 5 poles, 2,54mm pitch).

Regards

Markus

Article: 83584
Subject: Re: Negative hold time from Quartus
From: "Berty" <wooster.berty@gmail.com>
Date: 3 May 2005 11:28:29 -0700
Links: << >>  << T >>  << A >>
In general while it might take a bit more time and thinking it is much
more easier for the tolls as well as for your design to use instead of
the counter result as clock to use it as clock enable

For example instead of

reg	[1:0]	cnt;
always @ (posedge clk...
...
   cnt <= #1 cnt + 1'b1 ;
new_clk = cnt[1] ;

and than something like
always @ (posedge new_clk ....

Use clock enable
reg	clk_en	;
always @ (posedge clk ...
...
   clk_en <= #1 &cnt ;

and than

always @ (posedge clk ...
...
if (clk_en)

And if you need also negedge you can generate clk_en_neg and use it in
similar way

This way all your design use the same clock clk so it is easier for you
and the tool to find timing issue as well as if needed you can add
constrain to show that those FF's are multicycle.

Another BIG disadvangage using the code the way you wrote is that
passing information from the clock domain to the "new clock" which
is the output of the counter are no more in sync and can cause you
timing violation while when using clock enable (Notice that clock
enable is NOT gated clock) will allow you to pass signal back and forth
with no concern (most likely you will need however not to use
multicycle in those crossing signals, at least one way) 

Have fun.


Article: 83585
Subject: Re: JTAG communication Problems in Quartus using Signal Tap
From: "Amontec, Larry" <laurent.gauch@ANTI-SPAMamontec.com>
Date: Tue, 03 May 2005 20:30:53 +0200
Links: << >>  << T >>  << A >>
Markus Knauss wrote:
>> Is the flex-cable soldered directly on the pcb of USB Byteblaster?
>> How is this flex cable connected to the USB ByteBlaster?
>>
>> Thanks,
>> Larry
> 
> 
> Hi Larry,
> 
> I opend the case (there is just one screw and no warranty seal).
> 
> The flex cable is connected to the usb blaster PCB with a 10 pole 
> connector (2 x 5 poles, 2,54mm pitch).
> 
> Regards
> 
> Markus
Thank you for taking time opening the case. Very interesting, since we 
are building our own USB2.0 JTAG Emulator.

We have to find the best connection for the best signal integrity.

Larry
www.amontec.com
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Article: 83586
Subject: VHDL help with adding modules
From: walterwang@gmail.com
Date: 3 May 2005 11:33:34 -0700
Links: << >>  << T >>  << A >>
Hey guys, I'm fairly new to vhdl. Trying to test a small portion of an
mp3 player to work. Seems that If I add my synchronizer only, Model Sim
will show in the simulation that the signals are assigned to the
correct values as it should. However If I add another module (bit
reservoir) all the signals go to 'U' (undefined) except for clk and
reset.  However the modules do not share any outputs so that is not a
problem. Portion of my code below. Any ideas? thanks.



	   component synchronizer
       port( clk   : in  std_logic;
             rst   : in  std_logic;
             start : in  std_logic;
             done  : out std_logic;
             gr    : in  std_logic;
             si    : in  stream_in_type;
             so    : out stream_out_type;
             bri   : in  br_out_type;
             bro   : out br_in_type;
             frm   : out frame_type
           );
     end component;


	component bitreservoir
    port( clk   : in  std_logic;
          rst   : in  std_logic;
          start : in  start_type;
          bro   : out br_out_type;
          bri   : in  br_in_array_type
        );
  end component;





begin
    sync_unit: synchronizer
      port map( clk => clk,
                rst => rst,
                start => start.synchronize,
                done => done.synchronize,
                gr => start.granule,
                si => si,
                so => so_sync,
                bri => bri,
                bro => bro(0),
                frm => frame );



	 br: bitreservoir
    port map( clk => clk, rst => rst, start => start, bro => bri, bri
=> bro );


 -----------------------------clock generator
-----------------------------
  process
  begin
    loop
      clk <= '1';
      wait for 21 ns;
      clk <= '0';
      wait for 21 ns;
    end loop;
  end process;

------------------------------------------------------------------------


Article: 83587
Subject: Re: Xilinx V4 Power Calculations
From: "JD_Design" <JDDesignAndConsulting@hotmail.com>
Date: 3 May 2005 11:47:32 -0700
Links: << >>  << T >>  << A >>
Austin,

Thanks for looking into it; power analysis and regulator sizing are not
exactly the FUN part of the design process, but they still must be done
:-(

Any info appreciated.

Jim Davis
JDDC


Article: 83588
Subject: Re: DCM, constraints and routing (Xilinx Spartan 3)
From: "Berty" <wooster.berty@gmail.com>
Date: 3 May 2005 12:02:15 -0700
Links: << >>  << T >>  << A >>
Never had a case where I wanted all DCM to have same source but Why not
connect the input source to all 4 input clock on the board so all 4 DCM
get the same clock, you might want to use clock distributor and equal
trace or any other technique but this way you can get the input clock
of all DCM to be as closest as you can.
To send a signal across the FPGA you can use either the Global clock or
low skew lines. In global clock it mean most likely in your case after
the DCM and the drawback is that you cascade DCM and this have its own
problem of jitter and such.
As for the feedback this come from either x1 (or x2 if you use x2) and
not from the shifted phase output
0 and 180 do not need to have two output if they go to FF as you can
always use the inverted prior to the FF in the CLB, and this you simple
get by writing negedge instead of posedge. Same go to 90 and 270, use
the 90 and negedge it for 270.
As for not using BUFG you can do it and if the design is simple (small)
and not "too fast" there is more than good chance the tool will be able
to do it for you without your intervention.
So I would suggest try it first and only if it fail look on the report
and than you can move the FF and locate them where you want.
As for looking I assume you look on the floorplaner, try looking also
in the FPGA editor.
Have fun.


Article: 83589
Subject: Simulating custom peripherals
From: "Joseph" <joeylrios@gmail.com>
Date: 3 May 2005 12:26:06 -0700
Links: << >>  << T >>  << A >>
Any pointers or advice on simulating a peripheral created by the wizard
in Xilinx EDK?  I started this thing a while ago and I checked the
option that had to do with creating simulation files for you (and was
prompted to download some things to make them work), but now that I am
at the stage I want to run some simulations, I am pretty lost.  I am
using ISE 6.3 to edit the files.  I created a test bench (once!) before
for another (separate) project so I am vaguely familiar with the idea
of testbenching.  I thought that it would be a bit simpler to use an
automatically generated testbench than worry about all the PLB signals
that might be necessary.  Am I missing something straightforward?  Any
advice appreciated... I can provide more info if it would be helpful...

Thanks,
Joseph


Article: 83590
Subject: Re: Xilinx V4 Power Calculations
From: "JD_Design" <JDDesignAndConsulting@hotmail.com>
Date: 3 May 2005 13:01:39 -0700
Links: << >>  << T >>  << A >>
Austin,

One more thing; I noticed that the same is true for the DCM (no
variance over temperature; I did not have the data for the DCM
previously so I had not entered it).

Since it is about 38mW (3 for VCCINT, 5 for VCCAUX dynamic and 30 for
VCCAUX standby) it could be a factor at 85 degrees C if it does indeed
vary over temperature.

Thanks for any help!

JD


Article: 83591
Subject: Re: Xilinx input path: Why does the optional delay element with inputFF
From: Preben Holm <64bitNOnoSPAMno@mailme.dk>
Date: Tue, 03 May 2005 22:08:45 +0200
Links: << >>  << T >>  << A >>
> The input flip-flop is different, since it gets its data from the
> outside, not created by the internal clock.

And this is the only difference?
So it get's instantiated automatically when writing a process and this 
process is taking input from the "outside" of the FPGA?

> The delay from the chip's clock input  to the clock arriving at the
> input flip-flop (or any other flip-flop) is much longer than the delay
> between Data input to arriving at the D input of the input flip-flop.
> The clock must drive thousands of destiantions, the data only one.

But can a "minimum" delay of the clock be guaranteed - all these 
parameters is based on maximum delay of clock, maximum delay of 
input-buffer and so on.. But in my case I find the minimum a rather 
usefal value, since the data is valid after 7ns (3ns before rising edge, 
when 100MHz) and delaying this a 5ns total is bad for me if the internal 
clock isn't delayed more than 2ns (the data will not be ready to the 
rising edge of the clock). So a minimum 2ns delay is a very useful value 
whether or not to use the delay element (it works fine in my 
test-application, but only 50MHz testing and supposed to run 100MHz in 
the end).


> Whenever the clock arrives later than the data, data must be held (hold
> time) which is an ugly parameter that most flp-flops do not specify.
> 
> That's why it helps to delay the data input, and Xilinx has done that
> for the past 18 years on all our parts, but in Virtex-4 it has become
> much more sophisticated.

Okay, I'm very new to FPGA's and is in the learning part - I just 
learned about VHDL a few years ago, and now I'm really trying to learn 
about the FPGA's..

Xilinx has very nice XAPPs for many things, but this is one place where 
explanations is missing.


Thanks
Preben Holm

Article: 83592
Subject: Re: Xilinx tools from the commandline
From: Eric Smith <eric@brouhaha.com>
Date: 03 May 2005 13:09:22 -0700
Links: << >>  << T >>  << A >>
Marc Randolph wrote:
> My WAG is that they mistakenly thought they needed to go binary to

Rudolf Usselmann wrote:
> "WAG" !!! Wow ! Last time I heard WAG was about 10+ years ago
> when I was working at Tandem. We also used EWAG (E=educated).

Around here it's a SWAG (Scientific...).

Article: 83593
Subject: Re: Xilinx V4 Power Calculations
From: Austin Lesea <austin@xilinx.com>
Date: Tue, 03 May 2005 13:13:07 -0700
Links: << >>  << T >>  << A >>
Jim,

The Vccaux has so little running off it, that there is hardly any 
significant difference in current with temperature.

The 405PPC is always there on die, so the static leakage is also there, 
if you use it or not.  The dynamic current of the 405PPC hardly varies 
with temperature:  the stronger and faster at cold balances with the 
weaker and slower at hot.  Faster edges spend less time not being a 0 or 
a 1, slower edges spend more time between 0 and 1.  Stronger transistor 
draw more current (but for less time).  Weaker transistors draw less 
current (for more time).

Yes, we could be more accurate for a particular process corner, but it 
would not be worth it:  we need to be safe for all process corners.

Austin

JD_Design wrote:

> Austin,
> 
> Thanks for looking into it; power analysis and regulator sizing are not
> exactly the FUN part of the design process, but they still must be done
> :-(
> 
> Any info appreciated.
> 
> Jim Davis
> JDDC
> 

Article: 83594
Subject: Re: Force sequential assigment
From: AL <ann.lai@analog.com>
Date: Tue, 3 May 2005 13:29:17 -0700
Links: << >>  << T >>  << A >>
I meant to do it for real, not

just in visual. I am trying to do

something like a for loop but using if statement, incorrect and correct counts how many time incorrect data or correct data happens, I want the count to go

from 0 to 255 for a purpose, and then if count is 0 to 255, theoretically I should get 256 times. In a for loop, if I write, for (i = 0; i <255; i++) count <= count + 1; it will increase i then go in and increase i, so that way count will come out to be 256, and i goes from 0 to 255, in my if loop, both count and i would go from 0 to 255, is there a way i can make the count change a few nanosecond before the i change? That way, count can count how many times it happens.

Article: 83595
Subject: Re: Force sequential assigment
From: AL <ann.lai@analog.com>
Date: Tue, 3 May 2005 13:31:57 -0700
Links: << >>  << T >>  << A >>
I meant to do it for real, not just in visual.

I am trying to do something like a for loop

but using if statement, incorrect and correct

counts how many time incorrect data or correct

data happens, I want the count to go

from 0 to 255 for a purpose, and then if count

is 0 to 255, theoretically I should get 256

times. In a for loop, if I write, for (i = 0;

<255; i++) count <= count + 1; it will

increase count then go in and increase i, so

count will come out to be 256, and i goes

from 0 to 255, in my if loop, both count and i

would go from 0 to 255, is there a way i can

make the count change a few nanosecond before

the i change? That way, count can count how

many times the loop happens.

Article: 83596
Subject: Re: Multiply Accumulate FPGA/DSP
From: Sylvain Munaut <com.246tNt@tnt>
Date: Tue, 03 May 2005 22:46:31 +0200
Links: << >>  << T >>  << A >>
bart wrote:
> I have been tasked with trying to implement a FFT algorithm in a
> FPGA/DSP architecture.  The algorithm would be a N point FFT with 1000
> frequency bins.  Each frequency bin would require a multiply, by the
> constant e^jx, and then accumulate every 1 microsecond.  This turns out
> to be 1000 multiply accumulates happening in parallel every 1
> microsecond.  Does anyone have experience doing something similar in an
> FPGA/DSP and can they point me in the  right direction as far as
> choosing a FPGA/DSP development board?  Any help would be appreciated.
> 

1000 MAC in parallel ... that's a lot !
come on, just to store all the accumulators in parallel, with just like 
48 bits accumulator , that would be 48000 regs ...

1 microsecod is 1000 ns so the way to go is to have like 20 units in 
parallel and do the job every 20 ns which sounds a lot better. Then
use a block ram. Each block ram would have to "remember" 50 accumulator, 
not a problem.


	Sylvain

Article: 83597
Subject: Re: Multiply Accumulate FPGA/DSP
From: Thomas Womack <twomack@chiark.greenend.org.uk>
Date: 03 May 2005 21:47:32 +0100 (BST)
Links: << >>  << T >>  << A >>
In article <1115143492.028339.55630@f14g2000cwb.googlegroups.com>,
bart <larsonbr@gmail.com> wrote:
>I have been tasked with trying to implement a FFT algorithm in a
>FPGA/DSP architecture.  The algorithm would be a N point FFT with 1000
>frequency bins.  Each frequency bin would require a multiply, by the
>constant e^jx, and then accumulate every 1 microsecond.  This turns out
>to be 1000 multiply accumulates happening in parallel every 1
>microsecond.

Or ten MACs in parallel every ten nanoseconds; I'm imagining a little
circuit (two BRAMs, one multiplier) which reads the input, multiplies
it by a constant read from one block RAM, and adds it to an
accumulator in another, plus a sequencer over the block RAM locations,
the whole thing replicated ten times in an XC3S1000 (dev. boards are
$200 or so from www.xess.com).

Though you're using a complex multiplier, which is roughly four
integer multipliers, so you might have difficulty with ten-fold
replication in the 3S1000; and from what I've read here, running with
only five-fold replication, so a cycle time of 5ns, might require
quite elaborate design to get the speed sufficient; it might even be
too fast for the multipliers.

Have another circuit the other side which uses the other port on the
accumulator BRAMs to read out the accumulated data when the time comes.

This is a back-of-an-envelope design, I'd be really happy if someone
with actual FPGA experience could point out what's wrong with it.

Tom

Article: 83598
Subject: Re: Multiply Accumulate FPGA/DSP
From: Thomas Womack <twomack@chiark.greenend.org.uk>
Date: 03 May 2005 21:48:58 +0100 (BST)
Links: << >>  << T >>  << A >>
In article <1115143492.028339.55630@f14g2000cwb.googlegroups.com>,
bart <larsonbr@gmail.com> wrote:
>I have been tasked with trying to implement a FFT algorithm in a
>FPGA/DSP architecture.  The algorithm would be a N point FFT with 1000
>frequency bins.  Each frequency bin would require a multiply, by the
>constant e^jx, and then accumulate every 1 microsecond.

I'd not call that an FFT; I'd call it a calculation of a thousand
points of a DFT. It may well be possible to do it with less than one
complex gigaMACs, by using an FFT, but regrettably I'm not awake enough
to remember how to do that filter transformation.

Tom

Article: 83599
Subject: Re: 5V PCI interface
From: "gja" <geeja@hotmail.com>
Date: Tue, 3 May 2005 16:52:06 -0400
Links: << >>  << T >>  << A >>
Austin,
I hate to bring this up again, but I've just been made aware that the 
circuit in XAPP646 would exceed the absolute worst case conditions for the 
IDTQS3861 part. With BE and GND pins biased around 0.7v (can be as high as 
0.875v if 1.5v +5%), the IDT QS3861 datasheet states ABSOLUTE MAXIMUM 
RATINGS for the bus inputs as -0.5 to +7 volts. With GND at 0.875, this 
means 0.375v should be the lowest voltage at the bus pins. Usually TTL Vol 
is 0.4v but under light loading it's closer to 0.2v and this would violate 
the max ratings.
I would like to hear your comments on this and your comments that this 
circuit has actually been used in production by others without problems.

Thanks,
gja








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