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Messages from 82300

Article: 82300
Subject: Re: vhdl and clock-pin
From: "dfx" <mpillai@prodacc.com>
Date: 10 Apr 2005 12:02:34 -0700
Links: << >>  << T >>  << A >>
Benjamin,

DesignF/X from http://www.prodacc.com (free trial download) helps
address these kinds of issues; it assists with the import of top-level
HDL, and guides in the tagging of clock pins to specific pins and to
data busses. Once that is done, it also helps you ensure that pins
selected for your data sync are compatible and served by the clock pin
you selected. 

With best wishes,
Manu Pillai


Article: 82301
Subject: Re: ise 7.1 sp1 BEWARE !
From: Bret Wade <bret.wade@xilinx.com>
Date: Sun, 10 Apr 2005 13:49:34 -0600
Links: << >>  << T >>  << A >>
Rudolf Usselmann wrote:
> Bret Wade wrote:
> 
> 
>>Rudolf Usselmann wrote:
>>
>>>Just a short note of caution ....
>>>
>>>After installing sp1 for ise 7.1 (linux) mapper is crashing:
>>>
>>>map -p xc4vlx25-sf363-10 -timing -register_duplication -pr b -o
>>>usb_top_map.ncd usb_top.ngd usb_top.pcf
>>>Release 7.1.01i - Map H.39
>>>Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
>>>Using target part "4vlx25sf363-10".
>>>Mapping design into LUTs...
>>>Writing file usb_top_map.ngm...
>>>Running directed packing...
>>>Running delay-based LUT packing...
>>>Running timing-driven packing...
>>>
>>>Phase 1.1
>>>Phase 1.1 (Checksum:9e05bf) REAL time: 8 secs
>>>
>>><SNIP>
>>>
>>>Phase 14.5
>>>Phase 14.5 (Checksum:8583af2) REAL time: 5 mins 23 secs
>>>
>>>Invoking physical synthesis ...
>>>Abort (core dumped)
>>>
>>>Regards,
>>>rudi
>>>=============================================================
>>>Rudolf Usselmann,  ASICS World Services,  http://www.asics.ws
>>>Your Partner for IP Cores, Design, Verification and Synthesis
>>>
>>>
>>
>>This problem can be avoided if you turn off that new
>>"-register_duplication" feature.
>>
>>Bret
> 
> 
> Bret,
> 
> Before sp1, "-register_duplication" helped me meet timing when
> IO buffer registers needed to be duplicated.
> Do you know of another work around ?
> 
> Thanks,
> rudi

Hi Rudi,

We've seen one similar case and that was a Windows only failure. If you 
have access to a Linux or Solaris machine, that might work. On the other 
  hand, that case wasn't an SP1 regression like yours is, so they may be 
different problems. If that doesn't work, a webcase would be the next 
suggestion.

Regards,
Bret

Article: 82302
Subject: Re: Neural Networks in FPGA
From: e <e@yahoo.com>
Date: Sun, 10 Apr 2005 15:56:58 -0400
Links: << >>  << T >>  << A >>
OK -
Let me rephrase my question.

Has anyone who frequents this newsgroups and has a lot of experience 
with FPGAs, actually tried to make a functioning NN system and has some 
realworld experience with FPGA NN Systems.
(Mean as it may sound , this is meant to rule out present or past 
graduate students that only got as far simulation.)




JJ wrote:
> Tryin to avoid some gardening work I had to check that out.
> 
> I only see upto p76 so 760 of 9880 refs.
> 
> Even after turning off a redundancy warning it goes to 980 out of 11600
> so I guess the other 9-10k can't be reached or can they?
> 
> Is it possible to random access out there in the 9880 boonies, I don't
> usually go further than 1st few pages. And google says it won't go past
> 1000. Hint directly type in over "num=300" to jump but 1000 gate still
> there.
> 
> Anyway to save the whole thing to file in 1 go?
> (after change settings to 100 items per page)
> 
> 
> johnjakson at usa dot com
> 

Article: 82303
Subject: LVDS for lcd panel and RocketIO
From: =?ISO-8859-15?Q?Benjamin_Menk=FCc?= <benjamin@menkuec.de>
Date: Sun, 10 Apr 2005 22:21:07 +0200
Links: << >>  << T >>  << A >>
Hi,

I want to connect a LCD Panel with LVDS to my Virtex2Pro. The LVDS 
frequency is max 80 MHz. My fpga runs at 100 MHz and is speed grade -5. 
Do I have to get into the RocketIO stuff now, or does it have nothing to 
do with it?

regards,
Benjamin

Article: 82304
Subject: Re: XST -vlgincdir
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Sun, 10 Apr 2005 20:47:30 +0000 (UTC)
Links: << >>  << T >>  << A >>
Dave Colson <dscolson@rcn.com> wrote:
> Hi,

> Does anyone know what this switch really does?
> They don't explain as to what is in that directory.

> Does it mean that if you have an "`include" directive
> in your verilog code that XST will search that directory for
> the files?


Yes...

... however Xilinx screwed that option before 5.3 and after 5.3.

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 82305
Subject: Re: Neural Networks in FPGA
From: "JJ" <johnjakson@yahoo.com>
Date: 10 Apr 2005 13:54:20 -0700
Links: << >>  << T >>  << A >>
More likely than not, most regulars here probably have not dipped their
finger into NNs as they are probably busy more in DSP, or embedded
space.

But google fpga neural networks  on the web did highlight at least a
couple of may  be interesting articles for you to start with. Those
authors may or may not have been here too but AFAIK I haven't seen NN
come up that often.

google groups too to see where they hang out

regards

johnjakson


Article: 82306
Subject: Problem with appnote XAPP622 (SDR LVDS)
From: =?ISO-8859-15?Q?Benjamin_Menk=FCc?= <benjamin@menkuec.de>
Date: Sun, 10 Apr 2005 23:06:49 +0200
Links: << >>  << T >>  << A >>
Hi,

in the introduction i find:
"At SDR clock frequencies below the maximum operating frequency (420 
MHz) of the Virtex-II
Digital Clock Manager (DCM), implementing a single data rate design can 
be easily
accomplished using standard design techniques. This application note 
describes a method of
implementing an SDR interface at clock frequencies higher than the 
maximum operating
frequency of the DCM, without exceeding the AC timing specifications of 
the Virtex-II devices."

but later on, on page 3, the input ref_clk is connected to a DCM. Why is 
that possible? I thought the frequency is higher than the max DCM input 
frequency?

regards,
Benjamin

Article: 82307
Subject: Re: LVDS for lcd panel and RocketIO
From: General Schvantzkoph <schvantzkoph@yahoo.com>
Date: Sun, 10 Apr 2005 18:06:58 -0400
Links: << >>  << T >>  << A >>
On Sun, 10 Apr 2005 22:21:07 +0200, Benjamin Menküc wrote:

> Hi,
> 
> I want to connect a LCD Panel with LVDS to my Virtex2Pro. The LVDS 
> frequency is max 80 MHz. My fpga runs at 100 MHz and is speed grade -5. 
> Do I have to get into the RocketIO stuff now, or does it have nothing to 
> do with it?
> 
> regards,
> Benjamin

Nothing to do with it. RocketIO is for serial protocols like InfiniBand,
Fibrechannel or PCI Express. The data rates on those is multiple
gigabits/second not a puny 80MHz. You can easily run LVDS at 80MHz, I've
run it at 266MHz across ribbon cables using a Spartan3 which is slower
than a V2P.


Article: 82308
Subject: Shared bus on FPGA
From: "Ankit Raizada" <ankit.raizada@gmail.com>
Date: 10 Apr 2005 17:37:45 -0700
Links: << >>  << T >>  << A >>
I have a microprocessor core (Plasma from Opencores), I want to
implement a shared bus (Data as well as Address) among the this core
and a number of other cores as well. If anyone has some experience
about implememnting a shared bus please let me know. I have 2 ideas (1)
to connect the cores in a daisy chain kind of fashion (2) to connect
the cores using tri state logic. which will give me more performance
benefit? Also other experiences, ideas and knowledge about nuances of
this design are welcome.


Article: 82309
Subject: Re: Shared bus on FPGA
From: "Ankit Raizada" <ankit.raizada@gmail.com>
Date: 10 Apr 2005 17:48:26 -0700
Links: << >>  << T >>  << A >>
The entity for Plasma Core is as given below
entity mlite_cpu is
   generic(memory_type     : string  := "DUAL_PORT";
--DUAL_PORT_XILINX_XC4000XLA
           adder_type      : string  := "DEFAULT"; --AREA_OPTIMIZED
           mult_type       : string  := "DEFAULT"; --AREA_OPTIMIZED
           shifter_type    : string  := "DEFAULT"; --AREA_OPTIMIZED
           alu_type        : string  := "DEFAULT"; --AREA_OPTIMIZED
           pipeline_stages : natural := 3;
           accurate_timing : boolean := true);
   port(clk         : in std_logic;
        reset_in    : in std_logic;
        intr_in     : in std_logic;

        mem_address : out std_logic_vector(31 downto 0);
        mem_data_w  : out std_logic_vector(31 downto 0);
        mem_data_r  : in std_logic_vector(31 downto 0);
        mem_byte_sel: out std_logic_vector(3 downto 0);
        mem_write   : out std_logic;
        mem_pause   : in std_logic);
end; --entity mlite_cpu


Article: 82310
Subject: re:implement the JTAG MASTER --ACT8990 by using FPGA
From: strayblue2003@yahoo.com-dot-cn.no-spam.invalid (strayblue)
Date: Sun, 10 Apr 2005 23:50:44 -0500
Links: << >>  << T >>  << A >>
I am new to the JTAG MASTER.Could you give me some example or
document?


Article: 82311
Subject: Re: Neural Networks in FPGA
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Mon, 11 Apr 2005 15:05:45 +1000
Links: << >>  << T >>  << A >>
e wrote:
> Has anyone investigated implementimg neural nets in FPGAs?

Many (most?) classical neural networks utilise non-linear functions at 
the nodes, with fractional synapse weights and so on.  In SW 
implementations, floating point is the order of the day.

Add in the back-propagation training algorithms and you have significant 
non-integer arithmetic to contend with.

For implementation in commodity FPGA HW, this will all hurt.  Fixed 
point will help, but bring similar precision issues that arise in DSP.

Perhaps there is research on pure digital neural networks (binary 
weights, logical and/or/xor node functions) etc?  Dig around in the 
evolvable hardware research literature, they've been banging on it for 
years.

It is my expectation (not experience), that there will be significant 
practical issues in implementing reasonable sized classical NNs on FPGA 
hardware.  You will very quickly find yourself building either huge 
arrays of FPGAs, or diving into dynamic reconfig / multicontext FPGA 
territory to get the logic coverage required to implement what will be a 
very large (virtual) circuit.

Or, implement a couple of NN nodes in your FPGA fabric, with some sort 
of controller updating the weights and accumulating responses at each 
node.  Use this to simulate the entire massive (and parallel) NN operation.

Surprise surprise it's time/area trade.

Lots of fun no doubt, but not trivial either.

John

Article: 82312
Subject: Re: re:implement the JTAG MASTER --ACT8990 by using FPGA
From: "Antti Lukats" <antti@openchip.org>
Date: Mon, 11 Apr 2005 07:36:58 +0200
Links: << >>  << T >>  << A >>
"strayblue" <strayblue2003@yahoo.com-dot-cn.no-spam.invalid> schrieb im
Newsbeitrag news:iZmdnTJmKoW5n8ffRVn_vg@giganews.com...
> I am new to the JTAG MASTER.Could you give me some example or
> document?
>

Dear Chinese Student,

there are 3 kinds of people

1) those who go to school because "they teach in school" - those people
learn nothing
2) those who go to school because they want to learn - whatever they learn
is outdated info by the day they finish the school
3) those who learn that whatever there is to learn is up to them, those quit
the school and start doing things and learn on the way of doing

if you dont want to be in category [1] then start learning!

JTAG master as standalone doesnt make much sense, if there is no application
SW supporting it.

implementing JTAG MASTER in SW by any small microcontroller is very simple,
and there is NO special hardware needed, all you need is 4 general purpose
I/O pins. As example in

http://www.hydraxc.com

there is a special JTAG controller implemented in small Microcontroller, by
using regular MCU IO pins the this Processors achives JTAG data transfer
rate up to 4Mbit per second, at 8MHz processor clock, and this without any
special hardware. Any processor with higher clock rate can get even higher
JTAG clock rates.

If simple JTAG MASTER hardware speed up is required, then please take a look
at

http://gforge.openchip.org/projects/jisp/

there is verilog implementation of JISP byte code player, if Bytes are
written to it, then it converts them to JTAG, well it requires a specially
prepared (tokenized) bytestream. When using this JISP player connected to
some CPU via small fifo then very high sustained JTAG TCK speeds can be
achived

http://www.mesanet.com/software/parallel/jtag.zip

and there is JTAG is your JTAG TAP master in VHDL

but my bet is that this info does not help you to pass your exam, you need
to start LEARNING and most important DOING things yourself.

Antti












Article: 82313
Subject: Re: EDK: Microblaze with XMdstub
From: kittyawake@gmail.com
Date: 10 Apr 2005 22:56:30 -0700
Links: << >>  << T >>  << A >>
I also have an interrupt controller in my system.If I include the
xmdstub then wont it overwrite my interrupt handler which is at
0X00000010?I read somewhere that xmdstub is 800 bytes and starts from
0x00000000 memory location.How does this work then?
Does anyone has experience in dealing with a system in which microblaze
will have several interrupts through the OPB_INTC?I am having hard time
figuring out what exactly the INTC sends to the microblaze when it gets
an interrupt request.
Thanx.


Article: 82314
Subject: Re: problem in driving I2C bus through memory-mapped register
From: shankar.vk@gmail.com
Date: 10 Apr 2005 23:05:35 -0700
Links: << >>  << T >>  << A >>
Thanks to all who replied.

I forgot to add that the same C code works when executed from an ARM
core which
is part of the same fpga which contains the I2C register

So the code is perfect.

We analysed the memory access signals such as chip select,  write
enable, wait etc
using a TLA .   They look OK.

The wait signal comes as an input to  the memory controller peripheral
of ARM  from the fpga.

               thanks


Article: 82315
Subject: Re: LVDS for lcd panel and RocketIO
From: "Dave Garnett" <dave.garnett@metapurple.co.uk>
Date: Mon, 11 Apr 2005 08:42:37 +0100
Links: << >>  << T >>  << A >>
> I want to connect a LCD Panel with LVDS to my Virtex2Pro. The LVDS 
> frequency is max 80 MHz. My fpga runs at 100 MHz and is speed grade -5. Do 
> I have to get into the RocketIO stuff now, or does it have nothing to do 
> with it?

LVDS Panels use a multiplexing scheme, whereby the LVDS link runs at a 
multiple (eg 7 x) of the incoming clock. So, if what you are trying to build 
is an equivalent to the usual LVDS TX chip (90C383 or similar) then you will 
need to generate LVDS signals at (max) 80 MHz times 7, ie 560 Mb/sec

I don't know enough about V2Pro to know how you would do this.

Dave




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Article: 82316
Subject: xapp134 on sdram controllers: @ bits reordering?
From: robertp <robertp@wyig.com>
Date: Mon, 11 Apr 2005 01:17:16 -0700
Links: << >>  << T >>  << A >>
In this design, and in others I've seen around, the bank bits are MSB.

What would you think about reordering address bits, so that MSB are plugged to row bits: the idea is to avoid the ACTIVE command latency, because MSB [so row bits] are less likely to change.

Article: 82317
Subject: easyfpga is not easy
From: "yp" <ypuilee@yahoo.com>
Date: Mon, 11 Apr 2005 16:29:13 +0800
Links: << >>  << T >>  << A >>
hi,
I have brought a cyclone development board (EZ1CUSB-12) from easyfpga
(www.easyfpga.com) . The CDROM version is 0.9 There is no
documentation/software how to download software to the cyclone chip.
According to the web site/menu, it can download from USB ( passive mode) or
AS ( active mode, which I think it can download from byteblasterMV cable).
Anybody can provide the software code !!
Thanks in advance.
Regards,
YP



Article: 82318
Subject: CCD and Graphics - which FPGA?
From: "C. Peter" <die_les_ich_nicht@gmx.net>
Date: Mon, 11 Apr 2005 10:48:54 +0200
Links: << >>  << T >>  << A >>
Hi all,

some years have gone since I did something with FPGAs and I am aware that 
technology has moved forward significantly since the end of the last 
century ...

We now think about reading out some CCD sensors and doing image processing 
with an FPGA. My questions to you:
- do you think this is feasable?
- which FPGA would you recommend?
- Which language would you recommend?

We have used Xilinx and Handel-C so far and hence would prefer to stick to 
them. But if there are good arguments against it we would certainly follow 
them.

Thanks a lot for your advice,

Christian


Article: 82319
Subject: Re: implement the JTAG MASTER --ACT8990 by using FPGA
From: "Amontec, Larry" <laurent.gauch@ANTI-SPAMamontec.com>
Date: Mon, 11 Apr 2005 10:53:01 +0200
Links: << >>  << T >>  << A >>
strayblue wrote:
> I want to implement the JTAG MASTER --ACT8990 by using FPGA,Does who
> have do the same thing? Could someone give me a hand please?
> 

You may start with the Chameleon POD from www.amontec.com.

Larry

Article: 82320
Subject: Re: CCD and Graphics - which FPGA?
From: Stephane <stephane@nospam.fr>
Date: Mon, 11 Apr 2005 11:22:53 +0200
Links: << >>  << T >>  << A >>
Did you consider using CMOS imagers? They have the great advantage that 
you can focus on a (or several) ROI.

C. Peter wrote:
> Hi all,
> 
> some years have gone since I did something with FPGAs and I am aware 
> that technology has moved forward significantly since the end of the 
> last century ...
> 
> We now think about reading out some CCD sensors and doing image 
> processing with an FPGA. My questions to you:
> - do you think this is feasable?
Sure, but what kind of application? A simple one can be done in software.

> - which FPGA would you recommend?
Again, what algorithms, what size of image, how many images/second... 
and most important, how much are you eager to spend for each device?

> - Which language would you recommend?
No other choice yet than Verilog/VHDL...

> 
> We have used Xilinx and Handel-C so far and hence would prefer to stick 
> to them. But if there are good arguments against it we would certainly 
> follow them.
> 
> Thanks a lot for your advice,
> 
> Christian
> 

Article: 82321
Subject: Re: LVDS for lcd panel and RocketIO
From: "Antti Lukats" <antti@openchip.org>
Date: Mon, 11 Apr 2005 11:48:26 +0200
Links: << >>  << T >>  << A >>
"Benjamin Menküc" <benjamin@menkuec.de> schrieb im Newsbeitrag
news:d3dh00$dli$00$1@news.t-online.com...
> Hi,
>
> yes a LVDS clock of 500 MHz would be possible. I have read some appnotes
> and I guess that I need an external oscillator for that frequency.
> However I am not sure yet howto generate the fraction of 500 MHz, for
> the parallel data, 71,42 MHz. I think 500 MHz is to high as input for a
> DCM.... Thats my question about appnote xapp622 that I have posted in a
> different topic.
>
> Do I still don't need to do anything with rocketIO at 500 MHz?
>
> regards,
> Benjamin

YES positive nothign todo with RocketIO

there is no 560MHz clock involved ore needed, you can achive 560MBit/s data
rate using normal LVDS and DCM the DCM output frequency is 280MHz, that
gives you 560Mbit data rate as you use DDR io what effective doubles the
datarate.

read the xilinx appnote there is an example of this

antti



Article: 82322
Subject: Re: LVDS for lcd panel and RocketIO
From: =?ISO-8859-15?Q?Benjamin_Menk=FCc?= <benjamin@menkuec.de>
Date: Mon, 11 Apr 2005 11:48:48 +0200
Links: << >>  << T >>  << A >>
Hi,

yes a LVDS clock of 500 MHz would be possible. I have read some appnotes 
and I guess that I need an external oscillator for that frequency. 
However I am not sure yet howto generate the fraction of 500 MHz, for 
the parallel data, 71,42 MHz. I think 500 MHz is to high as input for a 
DCM.... Thats my question about appnote xapp622 that I have posted in a 
different topic.

Do I still don't need to do anything with rocketIO at 500 MHz?

regards,
Benjamin

Article: 82323
Subject: Re: Shared bus on FPGA
From: Mark McDougall <msmcdoug@no.spam.iinet>
Date: Mon, 11 Apr 2005 20:35:52 +1000
Links: << >>  << T >>  << A >>
Ankit Raizada wrote:

> I have 2 ideas (1)
> to connect the cores in a daisy chain kind of fashion (2) to connect
> the cores using tri state logic. which will give me more performance
> benefit? Also other experiences, ideas and knowledge about nuances of
> this design are welcome.

That's going to depend entirely on your traffic patterns.

Have you considered the OpenCores Wishbone?

Regards,

-- 
|              Mark McDougall                | "Electrical Engineers do it
|  <http://members.iinet.net.au/~msmcdoug>   |   with less resistance!"

Article: 82324
Subject: Re: problem in driving I2C bus through memory-mapped register
From: shankar.vk@gmail.com
Date: 11 Apr 2005 04:01:50 -0700
Links: << >>  << T >>  << A >>
Let me add that  there are  other  memory mapped registers on the fpga
.
I have a problem only accessing the I2C related register.

In terms of execution flow, what is the difference between  memory
access through :
a) Trace32 JTAG debugger
and 
b) code running on arm      ?




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