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John, you don't think I made this up? http://www.digitimes.com/news/a20050509PR202.html and I quote: "Q: Please tell us about your new FPGAs and ASIC products. Do you have market share goals for these segments? A: In 1983, Altera invented the first programmable logic device, and since the introduction of MAX CPLDs (complex programmable logic devices) back in the early 80s, we continue to be the market leader in the CPLD segment with over half of the market." End of quote. So I was justified in calling that bullshit. Your sanitized version is of course correct, all PALs before Altera were one-time programmable, and Xilinx is a year younger... Peter AlfkeArticle: 84501
Does it function with every distribution of Linux? There is a way to try the 64 bit version or I need to recompile everything by myself? Thanks MarcoArticle: 84502
"Peter Alfke" <peter@xilinx.com> wrote in message news:1116544730.002008.190410@f14g2000cwb.googlegroups.com... > John, you don't think I made this up? I don't think you were peaking the BS meter on this one. I figured you had a true quote. Precision of information is sometimes lost at the tape recorder, the editor, the keyboard, the ear, or - often im my case - the brain. I couldn't find your quote via google so I appreciate the original reference. - JohnArticle: 84503
I am trying to fine some information about simulating the virtex 2 pro rocket io model in model sim for a couple of my students. Does it work like simulating other standard xilnix components, just write down the port map ( VHDL) and include the unisim library? Any help would be appreciated regardsArticle: 84504
On Fri, 20 May 2005 10:21:53 +1000, Stephen Lohning wrote: > I am trying to fine some information about simulating the virtex 2 pro > rocket io model in model sim for a couple of my students. Does it work > like simulating other standard xilnix components, just write down the > port map ( VHDL) and include the unisim library? > Any help would be appreciated regards It uses a SMART Model, you need a SMART capable simulatorArticle: 84505
Files attached - Seems my newsreader at work cut off the files. Joel <Joel> wrote in message news:ee8e66d.-1@webx.sUN8CHnE... > The included code is used to search a serial stream for a sync word and > then set a data valid flag for the sync word and the next four words in > the stream. Simulation works fine but the post-place and route simulation > fails to set the data valid flag. I am assuming that this is a timing > problem in detecting the sync pattern but not sure how to correct it. > > In addition ISE generates three warnings that I am not sure how to > resolve. > > If anyone has the time to look this code over and offer suggestions? > > Thanks, Joel > > ---Code library IEEE; use IEEE.STD_LOGIC_1164.ALL; > > entity downlink is > > generic ( SR_WIDTH : integer := 8 ); > > Port ( rst : in std_logic; sio_clk : in std_logic; sio_data : in > std_logic; data_valid : out std_logic; sio_word : out > std_logic_vector(SR_WIDTH-1 downto 0)); end downlink; > > architecture RTL of downlink is > > constant SYNC_WORD : std_logic_vector(7 downto 0) := X"D5"; > > type t_SioState is ( SYNC, LOAD ); > > signal s_sio_word : std_logic_vector(SR_WIDTH-1 downto 0); signal > s_data_valid : std_logic; > > begin > > process ( sio_clk, rst ) > > variable bit_count : integer range 0 to 8; variable word_count : integer > range 0 to 4; > > variable SioState : t_SioState; > > variable v_sio_word : std_logic_vector(SR_WIDTH-1 downto 0); variable > v_data_valid : std_logic; > > begin > > if ( rst = '1' ) then > > SioState := SYNC; > > v_sio_word := ( others => '0'); v_data_valid := '0'; > > bit_count := 0; word_count := 0; > > elsif ( falling_edge( sio_clk )) then > > v_sio_word := v_sio_word(SR_WIDTH-2 downto 0) & sio_data; v_data_valid := > '0'; > > case SioState is > > when SYNC => > > if ( v_sio_word = SYNC_WORD ) then > > v_data_valid := '1'; SioState := LOAD; > > end if; > > when LOAD => > > bit_count := bit_count + 1; > > if ( bit_count = 8 ) then > > v_data_valid := '1'; bit_count := 0; > > word_count := word_count + 1; > > if (word_count = 4 ) then > > word_count := 0; SioState := SYNC; > > end if; > > end if; > > end case; > > s_sio_word <= v_sio_word; s_data_valid <= v_data_valid; > > end if; > > end process; > > sio_word <= s_sio_word; data_valid <= s_data_valid; > > end RTL; > > --Test Bench USE std.textio.all; USE ieee.std_logic_textio.all; > > ENTITY downlink_tb_vhd IS END downlink_tb_vhd; > > ARCHITECTURE behavior OF downlink_tb_vhd IS > > -- Component Declaration for the Unit Under Test (UUT) COMPONENT downlink > PORT( rst : IN std_logic; -- sys_clk : IN std_logic; sio_clk : IN > std_logic; sio_data : IN std_logic; data_valid : OUT std_logic; sio_word : > OUT std_logic_vector(7 downto 0) ); END COMPONENT; > > --Inputs SIGNAL rst : std_logic := '1'; -- SIGNAL sys_clk : std_logic := > '0'; SIGNAL sio_clk : std_logic := '0'; SIGNAL sio_data : std_logic := > '0'; > > --Outputs SIGNAL data_valid : std_logic; SIGNAL sio_word : > std_logic_vector(7 downto 0); > > BEGIN > > -- Instantiate the Unit Under Test (UUT) uut: downlink PORT MAP( rst => > rst, -- sys_clk => sys_clk, sio_clk => sio_clk, sio_data => sio_data, > data_valid => data_valid, sio_word => sio_word ); > > -- sys_clk <= not sys_clk after 10 ns; > > tb : PROCESS > > FILE infile : Text; > > variable inline : LINE; variable in_val : integer; variable data : > std_logic_vector(31 downto 0); > > BEGIN > > -- Wait 100 ns for global reset to finish wait for 100 ns; rst <= '0'; > > file_open( infile, "D:/VHDL/DOWNLINK/VECTOR.DAT", READ_MODE ); > > loop > > if ( endfile( infile )) then assert false report "End of Vector File" > severity NOTE; exit; end if; > > readline ( infile, inline ); hread ( inline, data ); > > for i in 31 downto 0 loop > > siArticle: 84506
For anyone that's interested, my company (Endace Technology Ltd) is looking for VHDL engineers (And embedded software people and linux driver/kernel developers). We're a small (but rapidly growing) company based in Hamilton, New Zealand developing network measurement and acceleration products. Overseas people are welcome (but have to have an appropriate degree and three years of experience for immigration). If you're interested, the company website is http://www.endace.com, and I may be able to answer a few questions - I'm an engineer, not an HR person though, so for more specific information you would need to email our HR people (vacancies@endace.com). Let me know if you're interested - we've all been asked to keep an ear out for people :) JeremyArticle: 84507
Hi Andre, The clock name doesn't look correct to me in this assignment. Remember you have to use the clock node (net) name, not the name you gave the timing constraints assigned to the clock (clock settings). You have to specify the full name of the clock net, which will be long when this comes out of a PLL. Probably the easiest way to get the name of the clock signal is to use the node finder from Assignment Editor. Click on the "To" box of the Virtual Pin Clock assignment. Click on the arrow on the right side. Bring up the node finder, and look for a name something like "pll1|alt_pll|clk0" except longer. That's the name you want. To Assignment Name Value Enabled Pin_name1 Virtual Pin On Yes Pin_name1 Virtual Pin Clock ***<enter full clock node name here>*** Yes Regards, Vaughn Altera [v b e t z (at) altera.com] <ALuPin@web.de> wrote in message news:1116403083.260631.234660@g14g2000cwa.googlegroups.com... I have tried the following: To Assignment Name Value Enabled Pin_name1 Virtual Pin On Yes Pin_name1 Virtual Pin Clock clk_90_sys Yes clk_90_sys is the clock net name of the clock coming out of the Cyclone PLL. This clock is not routet to IOs, it is an internal clock. And yet I get the warning: #WARNING: Virtual pin clock "CLK_90_SYS" for virtual pin "Pin_name1" does not exist in the design - auto-selecting clock In the HELP of Quartus I read the following: CAUSE: You assigned the Virtual Pin Clock logic option to the specified pin. However this pin does not exist in the current design. When this condition occurs, Analysis & Synthesis automatically selects an appropriate virtual pin clock. ACTION: No action is required. To avoid receiving this message in the future, assign the Virtual Pin Clock assignment to an existing clock signal in the design. But "clk_90_sys" DOES exist. So what I am still doing wrong? Interesting thing: Some virtual pins do get an external clock coming into the FPGA. For these pins I do not get any warnings. Best regards AndréArticle: 84508
B. Joshua Rosen wrote: > On Tue, 17 May 2005 17:55:45 -0700, Simon wrote: > > >>B. Joshua Rosen wrote: >> >>>On Sun, 15 May 2005 04:57:06 +0000, Ronald H. Nicholson Jr. wrote: >>> >>>Get yourself a Linux machine (x86 obviously, not Linux on PPC) to run your >>>FPGA development environment. You can use the Mac as an X-Server, but >>>thats as close as you are going to be able to get. It's inconceivable that >>>the FPGA or CAE companies would add a third platform. >> >>Well, that's nice in theory, but certainly with the Wind/U toolkit it's >>a no-go. Some X widgets (especially pulldown menus) are rendered in the >>top-left corner of the screen, and the first choice is unavailable. In >>other cases, the program simply crashes with a BadAccess error. > > > That's curious because running the Xilinx tools with a Linux X-server > works just fine, that's how I run it, I wonder what's broken in the OS-X > implementation of X. That's how I run it too. SimonArticle: 84509
Hello, I want to implement a 128bit FFT with FPGA, do you have any reference design for me? Thanks in advance, MikeArticle: 84510
John_H, I cannot be so gracious. His statement looks like arch-typical bullshit: "Sound nice, so it must be true. Facts do not matter !" Just like the statement of Altera outshipping Xilinx in 90 nm devices (the truth is of course the opposite, by a long shot), or Stratix-2 having lower power consumption than Virtex-4. (We have built boards with Xilinx and Altera devices, side -by-side. And we have demonstrated the lower power consumption of the Xilinx devices to many customers). His is smoothly packaged bullshit, without any regards for the truth. But some suckers will believe it, if it only gets repeated often enough. Too bad ! Peter Alfke, from home.Article: 84511
Bob Perlman wrote: >Phil Hays wrote: >>Suppose you were designing an FPGA that would control some part of an >>oil refinery. Or the landing of a probe to Mars. Or the engines on >>an airliner. Or the dosage of radiation given to a cancer patient. >> >>Wouldn't you want to verify the design as correct in as many ways as >>you could? > >Sure. But as a practical matter, there's never enough time or money >to verify a design in as many ways as I could think of, even if the >reliability of the product is super, super important. And were I to >come up with a prioritized list of things I could do to ensure the >correctness and reliability of a design, functional simulation with >back-annotated timing would be near the bottom. I agree that functional simulation with back-annotated timing is not the top of the list. If I'd be happy leaving it off for a high reliability project would depend on details of the project. There are other ways to improve the testing, and the best answer isn't always going to be the same for all projects. That keeps this stuff fun. My list for a high reliability project would start looking something like this: Design specification (I know, boring, but important). Full static timing constraints, fully documented. Good functional simulation with self checking test bench. Good board or system level diagnostics. As much run time in a realistic test environment as practical. Run time with temperature and voltage extremes (stress testing). Design documentation (really boring, I know, but needs to be done). Simulation reviews. Code reviews. Specification and documentation reviews (triple boring. I suggest frequent lattes with triple shots of espresso, if that helps). Back annotated simulations without timings. Back annotated simulations with timings. I didn't add in board level checks for signal quality, thermal design, clocking and such what. Just as important, but I'm focusing on the FPGA here. The project details matter a lot. Would it be better to improve function simulation or run a back annotated simulation with/with timing? Well?? I think that depends on how good the other ways of verification are at covering the design. What a back annotated simulation attempts to verify is that: 1) All of the tools did their jobs correctly. 2) There were no subtle error(s) in coding. 3) If timing included, that the static timing constraints were correct and complete, and that the tools correctly used them. A good board or system level test can find many the first two types of issues. A margin test(temperature and voltage extremes) can find some of the third type of issues. Does my list miss any method you find important? Would you put things in different order? -- Phil Hays Phil-hays at posting domain (- .net + .com) should work for emailArticle: 84512
Hi All, I am trying to speed up the FFT on my embedded system. Here are some details questions on my project. 1, For different FPGA venders, what are the Pros and Cons of Xilinx? 2. How long would it take for a 128 pt complex FFT? 3, How does my CPU connect to the FPGA? 4. How many gate or memory do I need, which Xilinx chip should I pick? Thanks for your help, MikeArticle: 84513
Hi Peter, I vote this thread be relabeled "Hypocrisy Reaches New Heights." Time to wade in... >(We have built boards > with Xilinx and Altera devices, side -by-side. And we have demonstrated > the lower power consumption of the Xilinx devices to many customers). Does side-by-side mean a fair comparison? Your demonstration can be boiled down to a few observations: 1. The most lop-sided logic & routing design you could come up with shows the chips as equal on dynamic power. As far as I'm concerned, that just validates our claim & observation that we have significantly better logic & routing power on average. 2. If a design component maps perfectly to hard IP in one vendor and not in the other, it will burn less dynamic power. 3. When you compare an above-average leakage part to a below-average leakage part, you will find it has higher static power. And the power from that above-typical part will exceed the typical spec from the vendor. 4. If you do an I/O power test and ignore the VccIO power rail, you can show an advantage, albeit with a very bizzare result with loads of VccInt power consumption... And here's a detailed version for those with more time on their hands: 1. You've shown that if you stack the deck by making a design that uses almost entirely 3-input or 4-input functions in Stratix II, Virtex-4 achieves *equal* dynamic power to Stratix II. What would happen if you have a real design which uses a range of functions from 3- to 6-inputs? I know the answer -- Stratix II comes out on top. Was showing you were equal on dynamic power on logic + routing (incidentally where about 70-80% of core dynamic power goes) the best you could concoct? 2. If a design maps precisely into the hard IP in an FPGA (in this case, Virtex-4), it will burn less power than if it must be implemented in soft logic. You show a (presumably 16- or 32-bit wide) 18K RAM, which maps perfectly to BRAM but requires 4 M4K RAMs in Stratix II -- and you've implemented it in the highest power way possible in the Straitx II device. Here's a surprise for you: If you were to instead make a 4K RAM, it would consume considerably less power in Stratix II -- because Stratix II has 4.5K RAMs, while V4 would need to wastefully use an 18K RAM! Crazy eh? You've shown some DSP filter widget that maps perfectly to the DSP48 (albeit with high latency). We could turn around and show a 36-bit multiply, which uses hard-logic in Stratix II and would require additional hardware besides DSPs in Virtex-4 -- we would have a huge power advantage here. Or we could do a complex multiplier, or some mult-accums in various modes... Overall, Stratix II has a greater variety of DSP and RAM hard IP (three RAM sizes, more flexible DSP/multiplier blocks), so I'd argue that the chances of someone's design mapping into Stratix II's hard logic is higher than mapping into Virtex-4's. But what do I know. 3. You show that a 2S90 (using a device with above typical leakage) has higher static power than a LX100 (using a device that has below typical leakage)... proving why you must use specifications to compare static power, not single-chip measurements. You had some very pretty graphs showing your data vs. the (unmentioned) typical spec. All sorts of innuendo (dare I say *bs*?) about us being out of spec. Of course, you neglect to mention that the 2S90 device still fell within Altera's published worst-case specification. Perhaps calling attention to that would generate needless questions on why Xilinx doesn't publish worst-case specs? Or maybe the FUD value of implying that our specs are incorrect was too hard to pass up? BTW, if I compare the 2S60 and LX60 devices used for your dynamic power data, and extrapolate the data back to 0 Mhz, I find that the 2S60 consumes the same static power as the LX60! But with Xilinx being a purveyor of truth, I have to assume that slide was lost and not intentionally left out... 4. You somehow got crazy I/O power behaviour such that we burned more VccInt power... I must admit that one has me stumped. If you could send me the design file and board schematics I might be able to figure out what's wrong with your design! But what really has me wondering, is why didn't you give VccIO measurements for your IO test? I wonder if the numbers weren't to your liking? With < 1/2 the pin capacitance in Stratix II vs. Virtex-4, that wouldn't surprise me. Truthfully yours, Paul Leventis Altera Corp.Article: 84514
"Peter Alfke" <peter@xilinx.com> wrote in message news:1116542484.664337.91630@z14g2000cwz.googlegroups.com... > If you want to measure the input threshold, just implement an inverting > data path from an input to an output, short the two pins together, and > decouple them to ground with a capacitor. You now have an oscillator > that switches around the threshold. > Peter Alfke, Xilinx Thanks Peter, that's a great suggestion! - JamesArticle: 84515
James A wrote: > Hi, > > I'm trying to find out when exactly the XC9572XL recognizes a falling edge. > It has a 3.3V supply, and the signal is a square wave between 0V and 5V > (this Xilinx is 5V input compatible). At what voltage would a falling edge > trigger? > Digital logic IO typically have a SINGLE threshold point despite the guaranteed values of Vil & Vih -- there is only one threshold point -- for TTL logic this has been around 1.5Vdc -- there are some logic which incorporates two threshold points for such as Schmitt Triggers called hysteresis ....Article: 84516
"Neill A" <neilla@ewst.co.uk> wrote: > We currently use WinXP, and have recently been informed that if we used > Linux, then Designer would run 10x faster. I would just like to see if > anyone out there can confirm this before trying to get a machine set up > with Linux. From who do you have this information? I used an old version under Solaris. But the runtime for Solaris and Windows is quite bad compareable du to the complete different HWs. The best thing for me was the possibillity to use a batch workflow under Solaris. bye ThomasArticle: 84517
"Symon" <symon_brewer@hotmail.com> wrote: > "Gabor" <gabor@alacron.com> wrote: > > I'm getting tired of poring over my code to find asynchronous > > inputs to my state machines that make them go "zero hot." [..] > As a born-again member of the Church of Synchronology, I would question your > design philosophy. The bible of Synchronology, the inspired word of the > supreme being Xtal, says thus:- > > Yeah, thou shalt synchronise everything to a masterclock on the way in to > the FPGA to make new signals in a single clock domain (Genesis). Clock all > your machines with this masterclock (Job). Retime stuff as needed on the way > out of the FPGA (Exodus). More work up front, but I'll finish long before > you, (Proverbs) and have a much more robust and reusable design, with easy > constraints generation (Numbers) as you're now finding out. (Lamentations) > Cheers, Syms. But is also written what to do if timing constraint meets power constraints? I like to have each design synchronous. And actually doing a _synchronous_ ASIC using several different clocks runing on various frequencies, but this is nearly impossible if it comes to do a prototype with an fpga and would be complete impossible if the design would need to hit the edge of technology, as often seen when doing high speed data processing. bye ThomasArticle: 84518
shame its so far away from Wellington Simon "Jeremy Stringer" <jeremy@_NO_MORE_SPAM_endace.com> wrote in message news:428d4af1$1@clear.net.nz... > For anyone that's interested, my company (Endace Technology Ltd) is > looking for VHDL engineers (And embedded software people and linux > driver/kernel developers). > > We're a small (but rapidly growing) company based in Hamilton, New > Zealand developing network measurement and acceleration products. > Overseas people are welcome (but have to have an appropriate degree and > three years of experience for immigration). > > If you're interested, the company website is http://www.endace.com, and > I may be able to answer a few questions - I'm an engineer, not an HR > person though, so for more specific information you would need to email > our HR people (vacancies@endace.com). > > Let me know if you're interested - we've all been asked to keep an ear > out for people :) > > Jeremy >Article: 84519
Hi Vaughn, I have inserted the name of the clock coming out of the PLL pll_bank3:PLL_B_3|altpll:altpll_component|_clk1 I do not get the warning anymore. But the strange thing is that I connect the output of the PLL in my top level file to a net with the name "clk_90_sys" So pll_bank3:PLL_B_3|altpll:altpll_component|_clk1 =3D clk_90_sys And yet it makes a difference, why? Rgds Andr=E9Article: 84520
The hardware resources used depend on your implementation but should conveniently fit in a spartan-3e from xilinx or cyclone from altera. The cpu connects to the fpga like any other device, through pins. Again your latency depends on your architecture and may range from a few clock cycles to hundreds of clock cycles. xilinx or altera will both do the job fine.Article: 84521
Hello, In http://ocw.mit.edu/NR/rdonlyres/Electrical-Engineering-and-Computer-Science/6-111Introductory-Digital-Systems-LaboratoryFall2002/0D0CD684-F7EC-45BC-80B8-F935D6971E72/0/l7.pdf, there is a short pulse catcher circuit, which uses a S-R latch and a D flip-flop. In the given VHDL source code, synthesis_off is used for telling the compiler to not optimize away the latch. ISE webpack 7.1 can not use this (attribute synthesis_off of A: signal is true;). Without this statement, after synthesis, a warning is given (the following signal(s) form a combinatorial loop: spc_inst_a, spc_inst_n_a.). Any idea for how to handle synthesis_off and remove the warning? Thanks!Article: 84522
Hi Jochen, > But please use > http://www.xilinx.com/applications/web_ds_v2pro/jitter_calc.htm > > to calculate first DCM's jitter ouput and verify that it fits to > second DCM's input requirements... Thanks for the link - I'll keep that one! I don't think I have any jitter issues however since I seem to be well within the spec of the DCMs. Cheers, KenArticle: 84523
Hi Mike,
> 1, For different FPGA venders, what are the Pros and Cons of Xilinx?
We are great. :)
> 2. How long would it take for a 128 pt complex FFT?
> 4. How many gate or memory do I need, which Xilinx chip should I pick?
You can find this information - and more - in the datasheet of our FFT
LogiCORE:
http://www.xilinx.com/ipcenter/catalog/logicore/docs/xfft.pdf
> 3, How does my CPU connect to the FPGA?
That will rather depend on your CPU, and the data bandwidth you require.
There are many different external bus standards, but most are variations on
a theme and are not too hard to get running. We have reference designs
available for certain common standards, such as the TI EMIF.
Hope this helps,
-Ben-
Article: 84524Hi, i was wondering about this... my workplace have bought a few Synopsys Designwares.. such as Filters, AMBA peripeherals IP... and i was told that they want to use this IP's in FPGA.... Xilinx. can this work?? I was told that when they generated the designware modules, they set it to use Xilinx FPGA (say Virtex2) as target.... this will generate modules based on Xilinx FPGA primitives. This module can be inserted in ISE and downloaded into the FPGA... however.. i was wondering.. is this the right way of doing it?? or is this ok??will this modules work correctly? the plan is to connect this synopsys designware ip's with some other ips.. on FPGA to make a complete system... will any issue with regards to the synopsys designware arises?? i am wondering because that i was told the synopsys designware is design for ASIC development and not FPGA... i hope someone can enlighten me about this... thanks in advance for you help :) cheers cromr
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