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"Austin Franklin" <dark9room@ix.netcom.com> wrote: >There was a time when products didn't ship with known bugs....it was a >mater of reputation, quality and standards. I also understand projects are >much vaster today, but we also have a lot more extensive tools today. Isn't that the truth. Sometimes I have to believe that software vendors don't evey try their code before they ship it. Wade PetersonArticle: 13526
Gosh, I always wanted a credit card containing > 16,000 Gate FPGA (Altera EPF6016) > PowerPC CPU > 16 MB DRAM > 2 MB Flash > Ethernet > USB and Serial Ports > LCD/TV Video > On-Board Power Supply > Credit Card Sized > Integrated POSIX RTOS, TCP/IP and Web ServerArticle: 13527
In article <366c2ff2.174116@nntp.netcruiser>, Stuart Clubb <s_clubb@NOSPAMnetcomuk.co.uk> writes >On Fri, 4 Dec 1998 12:15:46 +0000, David Pashley <David@edasource.com> >wrote: > >>If your requirements encompass productivity issues, then remember that >>FPGA Express 3 is available fully integrated within the Viewlogic 7.5 >>toolset. So you can freely combine HDL, schematics and state diagrams, >>have a single flow (including integrated place and route) for all FPGAs, >>and use a single environment for VHDL/Verilog, post-implementation and >>board-level verification. > >Hi Dave! > >I'm kind of spoilt as I have a nice setup of Renoir, Turbo Writer, >ModelSim, and Leonardo Spectrum L3. I don't like gate level schematics >any more (no, really) because I can do everything I want to do in VHDL >either graphically or textually. (And I have to deal with far too many >architectures anyhow). I am biased as I have the pleasure of selling >all four products. :-) > >You are right, that the real benefit is in the whole flow, not just a >point solution. > Stuart, Now I know that this is going to seem a bit predictable when you look at the relative strengths of my Viewlogic tools against your Mentor setup, but I'm going to take issue about whether one can, or should, do everything in VHDL. The answer is obviously that you can. But is it the best approach? One of the ways in which increasing design size has to be handled is by means of design re-use. In the "olden days" of digital design, we used to talk about hierarchichal and top-down design (now called "re-use"). At the bottom level of these designs would be gate-level schematics, very efficiently designed with the target architecture in mind. Because we would put the bottom-level modules in a library and re-use them either directly, or modified, the trick was to make them as fast and small as possible. Hand drawn schematics are often many times more efficient than what a synthesis tool can produce. Of course you can't start out on a 200,000k gate design with just a schematic editor. But a mixed approach, with highly efficient, schematic-drawn reusable elements alongside synthesized modules at the bottom level, and perhaps with a block schematic at the top does make sense. And this approach is more widely used than you may think. 5 years ago, if, as an EE, you knew VHDL, then you were a prized specimen. If I'm right, before long, designers who can work at the gate level and drive schematic editors will be the rare and sought-after commodity. The portability and productivity of HDL-based design are of undoubted benefit, but there is no reason to abandon the performance advantages of designing with schematics, while we can do both together. Given the right tools, of course. ;-) David (who works for Viewlogic's main UK VAR) -- David Pashley < --------------------------- < < < --- mailto:david@edasource.com | Direct Insight Ltd < < < < > Tel: +44 1280 700262 | | http://www.edasource.com < < < Fax: +44 1280 700577 | ------------------------------ < ---------------------------------Article: 13528
In article <366C4480.C3E82046@xilinx.com>, Peter Alfke <peter@xilinx.com> writes >As was mentioned in another recent thread: >It is o.k. and even desirable for hardware and software suppliers to >have a voice in this newsgroup, but they should ALWAYS identify >themselves properly. >We may be smart and even helpful, but we are obviously biased, and the >readers should be alerted to that bias. > >Peter Alfke, as always: Xilinx Applications Engineering > Agreed. In fact I'd say that vendor contribution is vital to the health of the newsgroup. The biggest problem facing the group seems to be the number of anonymous posts. If there were less of these, I think there would be more vendor contribution. -- David Pashley < --------------------------- < < < --- mailto:david@edasource.com | Direct Insight Ltd < < < < > Tel: +44 1280 700262 | | http://www.edasource.com < < < Fax: +44 1280 700577 | ------------------------------ < ---------------------------------Article: 13529
It is interesting to note that the techniques that Ray and Austin use are very similar to mine. It seems that independently, we have all come to the same conclusion: Viewlogic schematics and simulation, and a library of tiles that are 2 bits each of the specific function that we will want to build bigger things of. The "2 bits per" is because of the underlying structure of the XC4000 families (E, XL, XV, ...). To deal with the special case stuff at the top and bottom of a structure, there is some form of special block block that handles the special case stuff that occurs at the start and end of arithmetic based functions. I call these blocks "tiles". At the bottom of a structure is the "anchor" tile (like carry in), then there are multiple 2 bit tiles for the body of the function, and then at the top is a "cap" tile (overflow, borrow-out, terminal-count). At Fliptronics, I've been doing this for quite a while. The library of tiles has about 700 elements in it, for building a very exhaustive list of data path functions. What is somewhat different with the library that I have put together, is that I don't use it directly anymore. We have developped a suite of program that builds things from the library of tiles. This means that if I want a 25 bit down counter with synchronous load and no terminal count pin, it only takes a few seconds for the system to build it for me. On the rare occasion that the system can't build exactly what I want, as this thread is currently discussing a special cap-tile case, then I can just go in and edit the module that is built, and customize as needed. For those of you that care, I will soon begin flooding this news group with product annoucements as we are going to make this suite of programs and the tile library available as a product. Stay tuned. Philip FreidinArticle: 13530
How do I build myself the cable or the interface for printer port to program Altera isp devices? Thanks! LuigiArticle: 13531
On Mon, 07 Dec 1998 20:05:46 GMT, Todd Kline <todd@wgate.com> wrote: >I wanted an >ultra-wide/ultra-fast SCSI. What I ended up with was the same old >enhanced IDE, not even ultra-IDE! I couldn't convince my boss that disk >I/O performance was important. I would be interested in hearing what >people recommend for disk I/O. The problem with SCSI of course is the cost hit. Is there any mileage in using a big cheap IDE for bulk storage, and a small (2 or 4GB) SCSI for workspace? What would you keep on each? - Brian >Article: 13532
Luis de Funes wrote: > >How do I build myself the cable or the interface >for printer port to program Altera isp devices? According to Altera, they implement isp via a JTAG TAP (see <http://www.altera.com/html/mktg/index.html#devices>). Therefore the cable needs to provide TAP-compatible drive/load at the IC. Xilinx' parallel download cable has tristatable drivers at that end, mounted in a pod, with each driver's output fed through a series resistor (I presume for best line matching) to the IC and with a shunt capacitor to ground at the driver output pin (I presume partly to minimise generated glitches and partly to attenuate noise when the driver is OFF). There are also series-terminating resistors in the pod, but the cable itself is a plain one - no electronics at the PC end, not even terminating/matching resistors. In contrast, XESS Corp (who make experimenter units incorporating Xilinx FPGAs and CPLDs) use a cheapo parallel cable, no circuitry at the PC end and virtually no circuitry at the IC end. But Altera don't say what the relationship is between parallel port pins and the TAP, nor what circuitry is required to provide that relationship. Anyone reverse-engineered an Altera unit to find out? Why is it that some companies (eg Lattice) are so open about how to use their isp, providing lots of documentation including schematics of the "proper" units, while others keep the whole thing shrouded in secrecy? Particularly now that the majority have opted for JTAG TAP as the basis of isp, it seems really perverse to keep users in the dark. -- Tim Forcer tmf@ecs.soton.ac.uk Department of Electronics & Computer Science The University of Southampton, UK The University is not responsible for my opinionsArticle: 13533
I am having a problem with FPGA Express (bundled with Xilinx Student
Edition) detecting my resets in my final project. Basically it doesn't.
Even though I specify 0x01 as the reset value, it makes them all reset.
Could someone please help me out? Thanks!
Code fragment....
always @ ( posedge(reset) or posedge(mclk) )
begin
if (reset == 1)
lfsr_reg <= 6'b 000001; // guarantee register doesn't
load all 0's on reset
else
if (load == 1) // loading takes precedence over shift
enable
lfsr_reg <= load_data;
else if (enable == 1)
lfsr_reg <= { (lfsr_reg[5] ^ lfsr_reg[0]) ,
lfsr_reg[5:1] }; // shift right
end
FPGA Express synthesis results....
===============================================================================
| Register Name | Type | Width | Bus | AR | AS | SR | SS
| ST |
===============================================================================
| lfsr_reg_reg | Flip-flop | 6 | N | ? | ? | ? | ?
| ? |
===============================================================================
lfsr_reg_reg<3>
---------------
Async-reset: reset
lfsr_reg_reg<1>
---------------
Async-reset: reset
lfsr_reg_reg<5>
---------------
Async-reset: reset
lfsr_reg_reg<0>
---------------
Async-reset: reset
lfsr_reg_reg<4>
---------------
Async-reset: reset
lfsr_reg_reg<2>
---------------
Async-reset: reset
--
Brian C. Boorman
Harris RF Communications
Rochester, NY 14610
XYZ.bboorman@harris.com
<Remove the XYZ. for valid address>
Article: 13534Luis de Funes <fuzzy8888@hotmail.com> wrote: : How do I build myself the cable or the interface for printer port to : program Altera isp devices? : Thanks! : Luigi http://193.215.128.3/freecore/blaster.htm -- Greg Holdren gregh@wx.rose.hp.comArticle: 13535
In article <74hlik$3q0$1@nslave1.tin.it>, Luis de Funes <fuzzy8888@hotmail.com> writes >Hi! >Wath's the best way to begin to work with PLD? >I think to a 32 or 64 macrocells, ISP naturally. >Some producers give free software, but I'm confused. >Altera? Vantis? Lattice? Others? >Please, advice me! Thanks... > >Luigi > > Read everything you find at www.optimagic.com -- Kindest Regards | gerry@devantech | We manufacture Pic programmers, 8031, Gerald Coe | .demon.co.uk | 68302, 64180, 80C188EB cpu modules. http://www.devantech.demon.co.uk | Full custom uP control systems designed.Article: 13536
Rick Filipkiewicz wrote in message <366ACB4D.ABD2F174@algor.co.uk>... >Has anybody had any trouble getting the dongle'd Metamor VHDL compiler >to work under NT & if so how does one get around the problem ? As part of the installation, there should be something that loads the device driver for the dongle. It's invisible, or at least I didn't notice when it asked me if a driver was already installed or if I wanted to install one. The gotcha is that the device driver shows up in your control panel as a Multimedia device (don't ask me why). Open control panel, click on Multimedia, click the tab for "devices," then click on "other multimedia devices." you should see "sentinal for i386 systems" listed; if not, the driver never got installed. -- andy ------------------------------------------ Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters@noao.edu "In the beginning, there was darkness. And it was without form, and void. And there was also me!" -- Bomb #20, John Carpenter's "Dark Star"Article: 13537
This is a multi-part message in MIME format. ------=_NextPart_000_01C2_01BE229D.C55D79C0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Has anyone ever heard of http://www.GOVJOBS.COM? =20 ------=_NextPart_000_01C2_01BE229D.C55D79C0 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable <!DOCTYPE HTML PUBLIC "-//W3C//DTD W3 HTML//EN"> <HTML> <HEAD> <META content=3Dtext/html;charset=3Diso-8859-1 = http-equiv=3DContent-Type> <META content=3D'"MSHTML 4.72.3110.7"' name=3DGENERATOR> </HEAD> <BODY bgColor=3D#ffffff> <DIV> <DIV><FONT color=3D#000000 size=3D2>Has anyone ever heard of <A=20 href=3D"http://www.GOVJOBS.COM">http://www.GOVJOBS.COM</A>?</FONT></DIV> <DIV><FONT color=3D#000000 size=3D2></FONT> </DIV> <DIV align=3Dcenter> </DIV></DIV></BODY></HTML> ------=_NextPart_000_01C2_01BE229D.C55D79C0--Article: 13538
First Call for Papers
The First NASA/DOD Workshop on Evolvable Hardware
July 19-21, 1999
Jet Propulsion Laboratory
Pasadena, California, USA
Sponsored by:
National Aeronautics and Space Administration (NASA)
Defense Advanced Research Projects Agency (DARPA)
Ballistic Missile Defense Organization (BMDO)
Co-hosted by:
JPL Center for Integrated Space Microsystems (CISM)
JPL Center for Space Microelectronics Technology (CSMT)
The First NASA/DOD Workshop on Evolvable Hardware (EH'99) will be held at
the Jet Propulsion Laboratory in Pasadena, California. The purpose of this
workshop is to bring together leading researchers from the evolvable
hardware community, representatives of the programmable/reconfigurable
hardware community, technology developers, and end-users from the aerospace
community.
The emerging field of Evolvable Hardware is expected to have major impact
on deployable systems for space missions and defense applications that need
to survive and perform at optimal functionality during long duration in
unknown, harsh and/or changing environments. Examples of such applications
include outer solar system exploration, missions to comets and planets with
severe environmental conditions, long lasting space-borne surveillance
platforms, defensive counter-measures, long-term nuclear waste and other
hazardous environment monitoring and control. Evolvable hardware is also
expected to greatly enrich the area of commercial applications in which
adaptive information processing is needed; such applications range from
human-oriented hardware interfaces and internet adaptive hardware to
automotive applications.
The purpose of the workshop is to provide a forum for discussion on the
potential role of evolvable hardware in real-world applications, in
particular those related to space. The Workshop attendees will have the
opportunity to discuss the fundamental issues and state-of-the art of
evolvable hardware technology, plans for development of future devices and
hardware systems suitable for evolution, and needs related to space
applications. The outcome of this meeting is expected to be a technology
development roadmap that would lead to deployable evolvable hardware.
Topics to be covered include, but are not limited to:
* Evolutionary hardware design (including design of mechanical systems,
electronic circuits synthesis)
* Co-evolution of hybrid systems (including hybrids of wetware, chemical,
mechanical, and electronic components, etc.)
* Evolving hardware systems
* Intrinsic, and on-line evolution
* Hardware/software co-evolution
* Self-repairing hardware
* Embryonic hardware
* Morphogenesis
* Tools supporting evolvable hardware
* Novel devices and hardware platforms suitable for evolution
* Adaptive hardware, adaptive computing
* Adaptive flight hardware
* Real-world applications of EHW
SUBMISSION OF PAPERS:
Prospective authors are invited to submit four copies of their paper (not
exceeding 10 pages) to the address below. The paper should be submitted in
single-spaced, 10 point type on a 8.5" X 11" or equivalent paper with 1"
margins on all sides. Each submission should contain the following items:
(1) title of paper, (2) author name(s), (3) first author physical address,
(4) first author e-mail address, (5) first author phone number, (6) a
maximum 200 words abstract. Accepted papers will be published in the
workshop proceedings; details on the publication including the style for
the camera-ready paper will be posted later at the workshop web site
(http://cism.jpl.nasa.gov/events/nasa_eh).
The papers should be sent to:
Adrian Stoica
EH'99 Workshop
Jet Propulsion Laboratory, MS 303-300
4800 Oak Grove Drive
Pasadena, CA 91109, USA
IMPORTANT DATES:
Submission deadline: February 24, 1999
Author notification: April 2, 1999
Camera ready manuscript deadline: May 1, 1999
Workshop: July 19-21, 1999
Honorary Chair: John R. Koza, Stanford University
Chair: Adrian Stoica, Jet Propulsion Laboratory
Co-Chairs: Didier Keymeulen, Jet Propulsion Laboratory / Electrotechnical
Laboratory
Jason Lohn, NASA Ames Research Center
Program Committee:
Leon Alkalai, Jet Propulsion Laboratory (USA)
Forrest H. Bennett III, Genetic Programming, Inc. (USA)
Gregory Cain, Victoria University (Australia)
Silvano P. Colombano, NASA Ames Research Center (USA)
Hugo de Garis, Advanced Telecommunication Research Lab (Japan)
Stuart J. Flockton, University of London (UK)
Terry Fogarty, Napier University (UK)
David B. Fogel, Natural Selection, Inc. (USA)
Inman Harvey, University of Sussex (UK)
Hitoshi Hemmi, NTT Communication Science Labs (Japan)
Tetsuya Higuchi, Electrotechnical Laboratory (Japan)
Lorenz Huelsbergen, Bell Labs, Lucent Technologies (USA)
Alan Hunsberger, National Security Agency (USA)
Rich Katz, NASA Goddard Space Fligth Center (USA)
Daniel Mange, Swiss Federal Institute of Technology (Switzerland)
Pierre Marchal, Centre Suisse d'Electronique et de Microtechnique SA
(Switzerland)
Julian Miller, Napier University (UK)
Eric Mjolsness, Jet Propulsion Laboratory (USA)
Jose Munoz, Defence Advanced Research Projects Agency (USA)
Masahiro Murakawa, University of Tokyo (Japan)
Edward Rietman, Bell Labs, Lucent Technologies (USA)
Justinian Rosca, Siemens Corporate Research (USA)
Mehrdad Salami, Victoria University (Australia)
Eduardo Sanchez, Swiss Federal Institute of Technology (Switzerland)
Moshe Sipper, Swiss Federal Institute of Technology (Switzerland)
Stephen Trimberger, Xilinx (USA)
Adrian Thompson, University of Sussex (UK)
Anil Thakoor, Jet Propulsion Laboratory (USA)
Benny Toomarian, Jet Propulsion Laboratory (USA)
R. S. Zebulum, University of Sussex (UK)
For further information please check the workshop web site or contact:
Adrian Stoica
Jet Propulsion Laboratory, MS 303-300
4800 Oak Grove Drive
Pasadena, CA 91109, USA
adrian.stoica@jpl.nasa.gov
Tel: +1 (818) 354 2190
Fax: +1 (818) 393 4272
--
Jason
----------------------------------------------------------------------
Jason D. Lohn, PhD jlohn@ptolemy.arc.nasa.gov
Article: 13539
I would try removing the space between 6'b and 000001 in the reset
portion of your code.
Mark
Brian Boorman wrote:
>
> Code fragment....
>
> always @ ( posedge(reset) or posedge(mclk) )
> begin
> if (reset == 1)
> lfsr_reg <= 6'b 000001; // guarantee register doesn't
> load all 0's on reset
> else
> if (load == 1) // loading takes precedence over shift
> enable
> lfsr_reg <= load_data;
> else if (enable == 1)
> lfsr_reg <= { (lfsr_reg[5] ^ lfsr_reg[0]) ,
> lfsr_reg[5:1] }; // shift right
> end
>
Article: 13540http://www.algonet.se/~villeh/ I'm Ville Hokkanen from Sweden this are my links page. http://www.algonet.se/~villeh/Article: 13541
I need to buy an HDL synth tool that's not going to break the piggy-bank. It seems that there are 3 that will do the job: FPGA Express from Synopsys, Leonardo from Exemplar, or Synplify from, Synplicity. The conditions are: Verilog input, Target FPGA = Xilinx (probably Virtex ,certainly big XC4000XLs), must be command line or script driven, compatible (?) with Model Tech's simulator. Anybody have any experience with these tools ?Article: 13542
Can't see why. Does it matter whether your name is John Fitzpatrick or Patrick Fitzjohn? If you post trash time and time again, after a while nobody will read it because you will get in their killfiles :) >The biggest problem facing the group seems to be the number of anonymous >posts. If there were less of these, I think there would be more vendor >contribution. -- Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 13543
Have a look at the Philips Cool-PLD devices. They are among the very very few PLDs which are full-CMOS; most "CMOS" PLDs draw 50-200mA even at 0 MHz. I use the Philips P3Z22V10 but they do bigger stuff too, and a relatively cheap programmer. But not ISP. >Hi! >Wath's the best way to begin to work with PLD? >I think to a 32 or 64 macrocells, ISP naturally. >Some producers give free software, but I'm confused. >Altera? Vantis? Lattice? Others? >Please, advice me! Thanks... > >Luigi > -- Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 13544
The way you've defined your requirements, it looks like you're describing Exemplar Leonardo. I don't know how well Synplicity works with scripts, maybe it does a good job, but I know Exemplar will do what you're asking. If you like fiddling under the hood, Exemplar is a better choice. If you want a design to synthesize if you fall over dead and your head lands on the keyboard, Synplicity is a better choice. I don't mean to rank on Synplicity, from my benchmarking it compiled faster and gave slightly better results compared to Exemplar. Still, its more of a "hit one button and get a design" sort of tool. You won't go wrong with either. I didn't like FPGA Express when I benchmarked it, but I know they are better now (I looked at Version 2.something). Rick Filipkiewicz wrote in message <366D9981.1A8E551E@algor.co.uk>... >I need to buy an HDL synth tool that's not going to break the >piggy-bank. It seems that there are 3 that will do the job: FPGA Express >from Synopsys, Leonardo from Exemplar, or Synplify from, Synplicity. > >The conditions are: Verilog input, Target FPGA = Xilinx (probably >Virtex ,certainly big XC4000XLs), must be command line or script driven, >compatible (?) with Model Tech's simulator. > >Anybody have any experience with these tools ? >Article: 13545
I have an XCS30XL-PQ240 driving a 32 bit data bus and a 16 bit address bus. Can I do this without going to slow slew rate? How should I distribute the pins? I am mainly concerned about ground bounce, but I guess minimal internal routing could be a conflicting requirement. Comments? SteveArticle: 13546
To all on this newsgroup, About a month ago I posted a message asking for help on identifying two chips that I believe were programmable logic chips. Well, I just wanted to say thanks to all who responded and to let you know that I identified the chips and even found a data book about them. Unfortunately, the type of chips they are I'll never be able to duplicate them. But, if I continue my work there should be no reason why I couldn't come up with a modern FPGA solution to replacing them. The chips in question were manufactured by a company called Matra-Harris. They were custom manufactured gate arrays made for Atari for a new computer they were developing, the 1450XLD. The engineer would use special software to access Matra-Harris design computers remotely and come up with their custom chip design. Matra-Harris would them manufacture a custom die to the company in question design. Looks like I now have a date with a logic analyzer to figure out the logic being use to generate the chip select signals made by these chips. Again, thanks to all who responded. Without their help, I would still be trying to solve a mystery. -- ****************************************************** Glenn Bruner Email: brunergs@pcisys.net Visit my web page of images of rare Atari items http://www.pcisys.net/~brunergs/Atari/ ******************************************************Article: 13547
Depends on how good your PWB is and what kind of loads you are driving. The board should have at least four layers with dedicated ground and vcc planes. Good decoupling is also a must. The most important factor, however, is the loads on the pins you wish to switch. If the load capacitance is small (one or two devices), the switching current will also be small. If that is the case, you can drive all your data out the same edge. I've done that in many designs where the pins connected only to another FPGA or to a small number of memories or to a bus via fet switches without problems (with the fast slew rate). On the other hand, if you are driving a heavily loaded bus, you may want to stick with the slow slew rate. Steve wrote: > I have an XCS30XL-PQ240 driving a 32 bit data bus > and a 16 bit address bus. Can I do this without going > to slow slew rate? How should I distribute the pins? > > I am mainly concerned about ground bounce, but I > guess minimal internal routing could be a conflicting > requirement. > > Comments? > > Steve -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 13548
******************************************************************************
Call for Papers
The Seventh Japanese FPGA/PLD Conf. & Exhibit
June 30 -- July 1, 1999
MIPRO Exhibition Halls in Sunshine City, Tokyo, JAPAN
******************************************************************************
Beware, date and place changes since last CFP.
IMPORTANT DATES:
Deadline for submission of abstracts: Feb. 5, 1999
Notification of acceptance: Mar.19, 1999
Deadline for camera-ready papers: May 14, 1999
AIM AND BACKGROUND OF CONFERENCE:
The "Japanese FPGA/PLD Design Conference & Exhibit" is a
conference and exhibit, which provides a forum to exchange
ideas and promote research on the fields of device technology, design
technology, EDA support tools, and applications for FPGA/PLD.
At the seventh conference and exhibit, we are planning to introduce more
practically technical information and leading edge technology trends
on "Devices, Designs, EDA tools, and Application for FPGA/PLD";
especially on the FPGA/PLD in the 21st century. To make more intensive
discussion possible on the current studies and the sprouting ideas,
the next conference will expand the number of papers at the
paper presentation session and tutorial sessions. For example subjects
handled on these session is such as FPGA/PLD device which enables
entirely new functions, developing "System on Chip" using IP, new design
methodologies for FPGA/PLD toward the 21st century, and killer applications
for FPGA/PLD.
We invite papers on the following topics and also welcome papers on
related fields, such as system LSI design, development, and
application. Papers on case studies of design or application
from industries are most welcome. But we do not welcome papers
which have the same content, with the paper already published
or planed to be published in the near future. In the conference the
official language will be Japanese and English.
We are looking forward to your papers.
AREAS OF INTEREST:
Original papers on, but not limited to, the following areas are
invited.
a) Device architectures
b) Circuit design technology
c) CAD/DA technology
d) Development support technology with FPGA/PLD-compatible IP
e) Developing System on Chip using IP or VSI
f) Compiler technology for embedded systems
g) Emulation technology and rapid prototyping
h) Hardware/Software codesign
i) Reconfigurable computing
j) Usage of FPGA/PLD with embedded core
k) Evolving hardwares
l) All kinds of application using FPGA/PLD
m) Other topics related to FPGA/PLD
SUBMISSION OF PAPERS:
Please send six (6) copies of extended abstract and the completed
application form to the address below. Your papers will be reviewed by
the program committee for selection. Besides technical contents, your
extended abstract is expected to contain a presentation outline
describing the background, goal, approaches, importance, and
originality. The extended abstract may not exceed four pages of A4
size papers, including the title, figures, and tables. Abstracts
exceeding four pages will not be accepted. Selected papers
will have a chance to present there paper in the conference,
either by lecture style or poster session style. In addition,
all applicants will receive a three-day conference tickets for
free.
APPLICATION FORM:
Fill in the application form with the title of the paper, name of
author(s), author(s) affiliation, abstract(about 100 words), and three
or less keywords, with the contact address of the
corresponding author; name, affiliation, postal code and address,
telephone number, FAX number, and E-mail address. We welcome
applications by E-mail or postal mail. Ask for application
forms(template) to the address below.
AWARD:
Excellent papers will be awarded based on the decision made by the
program committee. The authors of excellent papers will be awarded at
the conference, and will be asked to give presentations at the special
session. Supplementary prizes will be also provided to the awarded
authors respectively.
SUBMISSION OF PAPERS:
Deadline for submission of abstracts: Feb. 5, 1999
Notification of acceptance: Mar. 19, 1999
Deadline for camera-ready papers: May 14, 1999
Send abstract/application forms or inquires to:
Hideharu Amano
Keio University
3-14-1, Hiyoshi, Yokohama 223-8522, Japan
TEL:+81-45-560-1063 FAX:+81-45-560-1064
E-mail:hunga@am.ics.keio.ac.jp
ORGANIZERS/SPONSORS:
Organizers:
Steering Committee of
The Seventh Japanese FPGA/PLD Design Conference & Exhibit
Sponsors:
Embassy of the United States of America (pending)
Semiconductor Industry Association (pending)
Distributors Association of Foreign Semiconductors (pending)
International Semiconductor Cooperation Center (pending)
In Cooperation with:
The Institute of Electronics, Information and
Communication Engineers of Japan (pending)
Information Processing Society of Japan (pending)
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Tetsuo HIRONAKA
Faculty of Computer Sciences Tel : +81-82-830-1566
Hiroshima City University Fax : +81-82-830-1792
Hiroshima, 731-31, JAPAN E-mail: hironaka@ce.hiroshima-cu.ac.jp
Article: 13549S & K Technologies, a small technology firm with a progressive outlook and high growth potential, is seeking qualified individuals for the position of Senior Electrical Engineer. Potential projects include designing high-speed serial communication and DSP electronics for a DoD project, embedded FPGA-based motion controller for a NASA telerobotics project, as well as commercial product development. Successful candidate should have the following qualifications: - BSEE with 5+ years of electronics design experience - FPGA/VHDL experience - Microprocessor/DSP design experience - OrCAD or other design tool experience - C/C++, 95/NT - Embedded programming experience desirable - U.S. citizen or permanent residence required SKT offers competitive compensation package, including bonus and profit sharing. For immediate consideration, send resumes to: Larry C. Li Director of Research 1016 Hercules Drive Houston, TX 77058 e-mail: larryli@ghg.net phone: (281) 483-9793
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