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Messages from 68750

Article: 68750
Subject: Re: DDS-Based PLL
From: "John_H" <johnhandwork@mail.com>
Date: Fri, 16 Apr 2004 15:37:20 GMT
Links: << >>  << T >>  << A >>
"Rene Tschaggelar" <none@none.net> wrote in message
news:407ec586$0$713$5402220f@news.sunrise.ch...
> Kevin Neilson wrote:
>
> > An alternative using a conventional VCO-based PLL with an FPGA would be
to
> > implement most of the PLL as a DDS.
>
> Not really.

??

If you read his full post, you would have noted that the selection of a high
frequency alias from the DDS output was part of the ideas he was asking
about.  Very valid.

Also, not all VCO-based systems result in higher frequency values.

My suggestion of using sin/cos DDS outputs to drive an I/Q modulator doesn't
require a VCO.

Not really.



Article: 68751
Subject: Re: Altera flex 10k library component doubt
From: "Leon Heller" <leon_heller@hotmail.com>
Date: Fri, 16 Apr 2004 16:52:22 +0100
Links: << >>  << T >>  << A >>

"prav" <praveenkn123@yahoo.com> wrote in message
news:863df22b.0404160428.43706c3b@posting.google.com...
> Hi all,
>
> i have got a basic doubt in altera's flex10 k library component
> "8count" which is a 8-bit up/down counter.This library component has a
> output named "COUT" is it the decoded version of  terminal count(255)
> or something else ??
> any body can clarify this!!
>
> thanks in advance

I've just used this counter, but I didn't use COUT. I think it means Carry
Out. You could always check the AHDL code for the part to see exactly what
it does.

Leon



Article: 68752
Subject: Re: Osborne [Was: Apples to Apples? Stratix II <> Virtex-II Pro]
From: "Pete Fraser" <pete@rgb.com>
Date: Fri, 16 Apr 2004 09:10:16 -0700
Links: << >>  << T >>  << A >>

"Tommy Thorn" <TommyAtNumba-Tu.Com--not@yahoo.com> wrote in message
news:M6Jfc.6089$Fo4.73141@typhoon.sonic.net...

>
> Another interesting tidbit: Osborne was quite arrogant and would readily
> turn down interested resellers for "not being professional enough".

I used to see him wandering the streets of Berkeley, staring
at his feet. I never spoke to him, but he seemed a sad and broken guy.



Article: 68753
Subject: Re: Writing PCI constraints in Altera
From: vbetz@altera.com (Vaughn Betz)
Date: 16 Apr 2004 09:30:18 -0700
Links: << >>  << T >>  << A >>
Hi Tushit,

As Subroto said, the best thing to do is to study Altera's PCI core to
get all the constraints right.

Here's a quick summary of the constraints for 33 MHz PCI:

- 7 ns Tsu constraint on all inputs
- 11 ns Tco constraint on the outputs
- 33 MHz constraint on the PCI clock
- 0 ns Th constraint on the inputs

Don't forget the Th (hold-time) constraint, since the PCI spec needs
it.

The Tsu and Tco constraints can instead be converted to clock path
constraints with the INPUT_MAX_DELAY constraint as David said, but it
would be easier to just set them as Tsu and Tco since then you don't
have to work on precisely what INPUT_MAX_DELAY you have to set.

Vaughn

tushitjain@yahoo.com (tushit) wrote in message news:<ec6aab0.0404130920.42fa2dfd@posting.google.com>...
> Hi,
> I am fairly new to FPGAs. I am trying to write the constraints for the
> PCI module on an Altera Stratix device. I am using QuartusII for all
> synthesis and P&R.
> The PCI spec says I need to ensure a setup time of 7ns for all pins.
> The PCI clock itself works at 33Mhz. I want to know the following:
> 1) Is it okay if I just constraint the PCI clk of my design to 50Mhz
> (30ns for the 33Mhz clock and another 10ns to ensures that the setup
> time is met)? I realise this will be an overkill on the internal logic
> but may save me some effort.
> 2) The other way I think to do this is to constraint the PCI clk to
> 33MHz and specify the external delay on all the PCI signals to 7 or
> 8ns. While setting PCI clk to 33Mhz I also ticked the option of
> including external delays in the frequency calculation. Is this the
> correct approach? OR do I need to setup the tco.
> Thanks in advance.
> Regards
> Tushit

Article: 68754
Subject: Document State Machines?
From: oarproducts@yahooREMOVE.com (o)
Date: Fri, 16 Apr 2004 17:37:51 GMT
Links: << >>  << T >>  << A >>
hi , i do contract design and most of my fpga designs have one or more
state machines written in VHDL , my question is how you document this
for the customer as a deliverable ?

1) ok, well written and commented VHDL is self documenting .. sortof
. but only to the company software types , managers do not get a warm
and fuzzy and when there is maintenance at a later time it doesn't
work well for managers/customers/new engineers to work with ..

2) the old stand by is a flow chart,  easy to use in a trouble
shooting meeting with a wide variety of participants looking for the
problem , bad part is they are expensive to make and maintain and my
customers don't like me to quote time doing them , the pc programs
that do them seem to take a lot of entry time and are expensive,  i
still often sketch out design flows in chart form on a big piece of
paper on the wall before VHDL coding and keep it updated during the
development but putting this into deliverable form is a pain ...

i was recently hired to solve a problem with a design I worked on a
couple of years ago which their engineers were having trouble with ,
the deliverable documents had well written VHDL and text descriptions
but at the time I quoted an additional manweek to provide computer
generated system flowdiagrams and that was turned down ..

so when i returned i dug into the cellar and found my old original
pencil drawn working chart , it was a 3' by 7' chart of the entire
system including mini flowdiagrams of each state machine .. i slapped
that on my customers conference room wall and 2 days later the problem
was solved after an intense session with engineering/customer/managers
all using it  .. ok the customer is happy but perplexed how come i
didn't supply such a diagram ... well , at the time they were
unwilling to pay me a week to "professionalize" it ... and i even
tried to get their document department to save a copy of the big chart
and the snooty document department said that they would not save  the
"hand written mess" ... mmmm

i would like to be enlightened , thanks



Article: 68755
Subject: Re: Document State Machines?
From: "Kevin Neilson" <kevin_neilson@removethiscomcast.net>
Date: Fri, 16 Apr 2004 18:15:26 GMT
Links: << >>  << T >>  << A >>
I tried a few of those tools that allow you to draw state machines and then
generate the code, but I never liked the code they generated and I don't
like having "source for the source".  So you can use them just for
documentation, but then you have the problem that the document always
differs from the actual code when you make a change.  I normally just do
what you do, which is to have a "hand-written mess" before I code the
machine.  I guess I'd recommend using the Mentor tool or something similar
to make a picture for the customer to see, but not necessarily for code
generation.  If there were a tool that could load in a state machine and
print it graphically, this would be ideal.  Synplicity's synthesizer does do
this for state machines it extracts, but the graphical version isn't really
pretty enough to show to managers.  -Kevin



Article: 68756
Subject: Re: DDS-Based PLL
From: "Kevin Neilson" <kevin_neilson@removethiscomcast.net>
Date: Fri, 16 Apr 2004 18:25:29 GMT
Links: << >>  << T >>  << A >>
"Hal Murray" <hmurray@suespammers.org> wrote in message
news:107sm91nneuiv61@corp.supernews.com...
> >An ability to position an edge within 300ps does not imply that a
> >3+GHz clock has been used.  It is possible to use multiple phases of a
> >lower frequency clock to achieve the same thing.
>
> Or an adjustable delay.  Consider the MC100E195
>   http://www.onsemi.com/pub/Collateral/MC10E195-D.PDF
> It claims 20 ps resolution.  (Mainly for ATE equipment, I think.)
>
> I've always wanted to build something that could use one of them.
>
> I'd guess Peter is using the equivalent thing packaged in a DCM
>
> --

These statements are both true but assume one can wield great control over
the DCM, which I don't think is possible.  There is no direct access to the
taps on a DCM or the tap mux, and the only way to change the tap is by using
the phase increment function, which allows you to increment or decrement one
tap only, and also very very slowly.  It's meant to be used infrequently.
Mabye Peter has some backdoor access to the DCM we don't know about.

You can use carry chain muxes to get 200ps resolution, but it's hard to get
the routing from the outputs to have deterministic delays.
-Kevin



Article: 68757
Subject: Re: how to pass a date user code from Synplify to Quartus?
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: 16 Apr 2004 20:28:36 +0200
Links: << >>  << T >>  << A >>
"Pierre-Louis" <none.none@hotmail.com> writes:

> Is there any way to do that automatically, by passing this parameter from
> Symplify?? I know the way to automatically pass a time based constant or a

You could make the synthesis script generate a file with the constant,
and then source this file from the the quartus script where you do
jtag programming.

Petter

-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 68758
Subject: Re: DDS-Based PLL
From: "Kevin Neilson" <kevin_neilson@removethiscomcast.net>
Date: Fri, 16 Apr 2004 18:34:50 GMT
Links: << >>  << T >>  << A >>
The applications I was thinking of mostly is sampling clocks for ADCs or
DACs, so having low jitter is important and in that case using the MSB of a
DDS wouldn't suffice.  I had one application in which I had to generate a
DAC clock that wasn't really large but was a really strange multiple of an
input clock (the ratio was close to 80000/78000, irreducable) and PLLs
couldn't handle that ratio and even if they could the comparison frequency
would be really low and the loop filter cutoff would have had to be really
small.

I like the offset idea.  Of course that means you need an accurate
high-frequency source with which to mix; I guess that would be generated
with a PLL.
-Kevin

"John_H" <johnhandwork@mail.com> wrote in message
news:aEhfc.10$6Z6.289@news-west.eli.net...
> Analog Devices has a whole line of parts based on integrating the whole
ball
> of wax.
>
> The technique is used, just not in the boards *we've* seen.
>
> One of the issues is that the bulk of designs don't need a precise,
> arbitrary, low jitter clock source opting instead for lower cost, fixed
(or
> limited) solutions.
>
> If you have a clock that's low enough in frequency to use a really cheap
> DAC, you could get better results by using the MSB output of a faster DDS.
> If you're fast enough to need a decent DAC, it'll cost you.  A simple
> lowpass filter works fine for some apps but may involve a less-simple
filter
> than you expect to block out an alias as close as the 3rd harmonic.
> Oversampling is great but increases the cost of the DAC further.  The
Analog
> Devices chips integrate most of these functions in one device providing
> exceptional spectral purity.
>
> I put together a DDS based synthesizer that adds controlled levels of
> sinusoidal jitter about 6 years ago and have since watched some of the
> offerings that provide higher integration.
>
> The higher frequency extraction with a bandpass can work but the filtering
> is easier with single-sideband modulation of a high frequency carrier with
 a
> DDS controlled offset.  I/Q modulation devices achieve this translation
> (with -35 dBc images) and are used significantly in wireless systems and
> don't have the narrow bandwidth, high rejection requirements of picking
out,
> say, the ninth harmonic.  Good I/Q is cheap stuff nowadays.
>
>
> "Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message
> news:Zahfc.37136$wP1.140239@attbi_s54...
> > An alternative using a conventional VCO-based PLL with an FPGA would be
to
> > implement most of the PLL as a DDS.  The FPGA would have a phase
> accumulator
> > and BRAM-based sine LUT and would output a sine to a cheap 8-bit DAC.
The
> > output of the DAC would be reconstructed with a simple lowpass (with a
> > simplicity based on the oversampling rate) and then squared with a
> > comparator to make a clock of any desired frequency.  The comparator
would
> > do the job of placing the edge of the clock at the correct interpolated
> > point between DAC samples.  This has several advantages.  You can
> synthesize
> > any clock with any crazy multiplication ratio without fractional-N
> > techniques.  You can dither or spread the clock easily and digitally
> control
> > overshoot when transitioning.  You get rid of a bunch of analog
hardware,
> > including a VCO and a loop filter and charge pump, all of which have
> varying
> > characteristics from part to part.  You could even generate really fast
> > clocks by bandpassing one of the DAC's images.  Yet I rarely see this
> > technique used.  Is is just that it's used more than I think, or does it
> > have some disadvantage like introducing a lot of phase noise?
> > -Kevin
> >
> >
>
>



Article: 68759
Subject: Re: DDS-Based PLL
From: "John_H" <johnhandwork@mail.com>
Date: Fri, 16 Apr 2004 19:30:38 GMT
Links: << >>  << T >>  << A >>
"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message
news:eHVfc.145675$gA5.1776343@attbi_s03...
> The applications I was thinking of mostly is sampling clocks for ADCs or
> DACs, so having low jitter is important and in that case using the MSB of
a
> DDS wouldn't suffice.  I had one application in which I had to generate a
> DAC clock that wasn't really large but was a really strange multiple of an
> input clock (the ratio was close to 80000/78000, irreducable) and PLLs
> couldn't handle that ratio and even if they could the comparison frequency
> would be really low and the loop filter cutoff would have had to be really
> small.
>
> I like the offset idea.  Of course that means you need an accurate
> high-frequency source with which to mix; I guess that would be generated
> with a PLL.
> -Kevin


The jitter associated with *most* digital-based clocking techniques is tough
to deal with for ADC and DAC systems without the PLL and VCO.  What *can* be
done to get the irreducably low frequency to not cripple your system is to
not go so low....  Fractional-N synthesizers can give superb spectral
results with non-integer divides.  In some cases, these Fractional-N devices
which "dither" the divider before the phase comparator can produce close-in
harmonics that aren't reasonable to filter.  With arbitrary numerator and
denominator values (producing an odd modulus in the accumulator) these
close-in sidebands can be pushed out to well beyond the PLL's loop filter
cutoff.  With sigma-delta techniques in some of the commercially available
Fractional-N synthesizers, some problem sidebands can be squashed.  Neat
stuff, all of it.

- John_H



Article: 68760
Subject: Re: PCI Express specification.
From: Dwayne Surdu-Miller <miller@SEDsystems.nospam.ca>
Date: Fri, 16 Apr 2004 13:30:41 -0600
Links: << >>  << T >>  << A >>
Actually, you can get the official specification from PIC SIG if you are 
not a member.  The order form is at:

http://www.pcisig.com/specifications/order_form

Dwayne


Article: 68761
Subject: Re: Osborne [Was: Apples to Apples? Stratix II <> Virtex-II Pro]
From: Austin Lesea <austin@xilinx.com>
Date: Fri, 16 Apr 2004 15:11:06 -0700
Links: << >>  << T >>  << A >>
All,

He was a real character.  That was part of the whole mystique:  he was 
actually Australian, but for some reason the Brits loved him (must be 
the accent).  I know because I was supposed to have a day off from 
lecturing, and I was flown from Paris to London to "replace" Adam when 
he did not show from Stockholm for an appointed 3 day course folks had 
paid $750 a day to attend.

I started my talk with "anyone who paid for Adam, I am not he.  I expect 
you to at least sit and listen to me until lunchtime before I will 
entertain giving anyone's money back.  Offer me that one courtesy."

At lunchtime, I had one person ask for their money back, and I was glad 
they did (as I would have thrown the a**hole out if he had not).

As for why I was in Paris, and why he got 'stuck' in Stockholm, I will 
not say here.  But it is one hell of a story if you ever find me and 
remember to ask me!

Adam was a fine gentleman with a sharp mind, and a gift for writing and 
explaining.

A quote from one of my brothers is appropriate here: "if I didn't have 
any idiosyncrasies, I'd have no personality at all!"

The world is lessened for the loss of folks like Adam.

Austin


Article: 68762
Subject: Re: Document State Machines?
From: "Bert" <_wegvoorspam_lmaarsen@xs4all.nl>
Date: Fri, 16 Apr 2004 23:25:07 +0100
Links: << >>  << T >>  << A >>

"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message
news:2pVfc.151171$w54.1057538@attbi_s01...
> I tried a few of those tools that allow you to draw state machines and
then
> generate the code, but I never liked the code they generated and I don't
> like having "source for the source".  So you can use them just for
> documentation, but then you have the problem that the document always
> differs from the actual code when you make a change.  I normally just do
> what you do, which is to have a "hand-written mess" before I code the
> machine.  I guess I'd recommend using the Mentor tool or something similar
> to make a picture for the customer to see, but not necessarily for code
> generation.  If there were a tool that could load in a state machine and
> print it graphically, this would be ideal.  Synplicity's synthesizer does
do
> this for state machines it extracts, but the graphical version isn't
really
> pretty enough to show to managers.  -Kevin
>

For state machines we use Ease, a tool for graphical FPGA design
entry. It includes also a nice manner to draw state macines. The output
is used in our company as the documentation.

I agree that the generated code is never as you wish it should be,
but I am not very unhappy with it. But to be honest only for very
complex state machines I will use this tool, for all other state machines
I write my own VHDL and provide a state machine drawing in our
hardware documentation.

The time I need to draw the machine, set al the conditions and actions
is mostly just a little bit less than writing the case statement by
yourself.

Bert



Article: 68763
Subject: generic mapping
From: "Steve Wenner" <stevewenner@adelphia.net>
Date: Fri, 16 Apr 2004 19:56:49 -0400
Links: << >>  << T >>  << A >>
Hello,
I am trying to create a test file to get a handle on 1. generic mapping and
2. multiple architectures within a file.  Could someone tell me what I am
doing wrong?  I am using the latest Quartus freeware however it doesn't seem
to like how I have called the architecture from the top level file (tester).


thanks much,

-- 
Steve Wenner


begin 666 tester.vhd
M;&EB<F%R>2!)145%.PT*=7-E(&EE964N<W1D7VQO9VEC7S$Q-C0N86QL.PT*
M#0IE;G1I='D@=&5S=&5R(&ES#0H)<&]R="AM+"!R.B!I;B!S=&1?;&]G:6,[
M(&]U='!U=#H@;W5T('-T9%]L;V=I8RD[#0IE;F0@=&5S=&5R.PT*#0IA<F-H
M:71E8W1U<F4@<W1R=6-T=7)E(&]F('1E<W1E<B!I<PT*#0IC;VUP;VYE;G0@
M86YD9V%T92!I<PT*"6=E;F5R:6,@*%1P9#IT:6UE*3L-"@EP;W)T*&$L(&(Z
M:6X@<W1D7VQO9VEC.R!C.B!O=70@<W1D7VQO9VEC*3L-"F5N9"!C;VUP;VYE
M;G0[#0H-"F)E9VEN#0H-"G-T979E.B!A;F1G871E*'=I=&AT:6UE*0T*"6=E
M;F5R:6,@;6%P*%1P9" ]/B Q-&YS*0T*"7!O<G0@;6%P* T*"0EA(#T^("AM
M(&%N9"!R*2P-"@D)8B ]/B!R+ T*"0EC(#T^(&]U='!U="D[#0H-"F5N9#L)
`
end

begin 666 andgate.vhd
M+2US86UP;&4@='=O(&%R8VAI=&5C='5R92!F:6QE#0H-"FQI8G)A<GD@:65E
M93L-"G5S92!I965E+G-T9%]L;V=I8U\Q,38T+F%L;#L-"@T*96YT:71Y(&%N
M9&=A=&4@:7,-"@EG96YE<FEC*%1P9#IT:6UE.CTR;G,I.PT*"7!O<G0H82P@
M8CH):6X@<W1D7VQO9VEC.PEC.B!O=70@<W1D7VQO9VEC*3L-"F5N9"!E;G1I
M='D@86YD9V%T93L-"@D-"F%R8VAI=&5C='5R92!W:71H=&EM92!O9B!A;F1G
M871E(&ES#0IB96=I;@T*"6,@/#T@82!A;F0@8B!A9G1E<B!4<&0[#0IE;F0@
M87)C:&ET96-T=7)E('=I=&AT:6UE.PT*#0H-"F%R8VAI=&5C='5R92!N;W1I
M;64@;V8@86YD9V%T92!I<PT*8F5G:6X-"@EC(#P](&$@86YD(&([#0IE;F0@
487)C:&ET96-T=7)E(&YO=&EM93L`
`
end


Article: 68764
Subject: Re: Problem downloading with parallel converter
From: "Hendra Gunawan" <u1000393@email.sjsu.edu>
Date: Fri, 16 Apr 2004 16:58:33 -0700
Links: << >>  << T >>  << A >>
"Peter Seng" <NOSPAM@seng.de> wrote in message
news:c5iov3$sfa$1@online.de...
> First try to make changes to the parallel port settings - see Quatech
> documentation. If You can not change the mode, try to set base adress to
> 3BCh (this address should not be capable to work in EPP or ECP mode) or
> contact Quatech and ask if the mode can be set to a user defined status.
> Interupts are of no interest - they are not used by parallel cable III.
> SPP and PS2 ports use a range of  3 adresses, EPP uses a range of 8
adresses
> and ECP uses two ranges of  8 adresses.
> Which I/O adresses are accessed (adresses and range)?


I use 0378-037F. According to the quatech manual, the only configuration
mode that use standard port mode is configuration #9. I tried to change to
that mode but it won't let me to set the base address to 03BC because it is
used for another device.
Could you tell me the address range for SPP, PS2, EPP and ECP so I can play
with it?

> ??? do You use the Xilinx cable and a standard parallel cable to make the
> Xilinx cable longer?

No, I don't use Xilinx cable at all. My FPGA board is a simple one.
https://digilent.us/Sales/Product.cfm?Prod=D2E
I just connect the board to my laptop using a standard parallel cable.
https://digilent.us/Sales/Product.cfm?Prod=PLLCBL
Thank You!

Hendra



Article: 68765
Subject: EH-2004 Registration
From: eh-2004@ehw.jpl.nasa.gov (EH-2004)
Date: 16 Apr 2004 17:41:00 -0700
Links: << >>  << T >>  << A >>
Dear Colleague,


The 2004 NASA/DoD Conference on Evolvable Hardware
registration  and Hotel  reservation is already available in the Conference
web-site, at

http://ehw.jpl.nasa.gov/events/nasaeh04


We also remind that, as in 2003, EH-2004 will
be co-located in Seattle with  the Genetic and
Evolutionary Computation Conference
(GECCO-2004,  June 26-30, 2004).


With best regards

Gregory Hornby
Conference co-chair

Article: 68766
Subject: Re: PCI Express specification.
From: "Kelvin" <kelvin8157@hotmail.com>
Date: Sat, 17 Apr 2004 09:20:15 +0800
Links: << >>  << T >>  << A >>
well...i will search it again and again until i can find one...dun think
i can afford that kind of price...

Kelvin





"Dwayne Surdu-Miller" <miller@SEDsystems.nospam.ca> wrote in message
news:1080d31jslrtubb@corp.supernews.com...
> Actually, you can get the official specification from PIC SIG if you are
> not a member.  The order form is at:
>
> http://www.pcisig.com/specifications/order_form
>
> Dwayne
>



Article: 68767
Subject: Huh, anybody wants to play some NES???
From: jaxlau@yahoo.com (Jacques athow)
Date: 16 Apr 2004 21:15:47 -0700
Links: << >>  << T >>  << A >>
our final year project.. thanks to everyone that answered my
questions. We spent more than 1000hours on this project. I wanna see
how much it can go for!

Xilinx rulez!

http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=3810496942

Article: 68768
Subject: Re: Huh, anybody wants to play some NES???
From: "Hendra Gunawan" <u1000393@email.sjsu.edu>
Date: Fri, 16 Apr 2004 23:00:52 -0700
Links: << >>  << T >>  << A >>
"Jacques athow" <jaxlau@yahoo.com> wrote in message
news:acc717b2.0404162015.6a20ae26@posting.google.com...
> our final year project.. thanks to everyone that answered my
> questions. We spent more than 1000hours on this project. I wanna see
> how much it can go for!
>
> Xilinx rulez!
>
> http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=3810496942

Jacques, first of all, congratulations! That's a really amazing project!
I have a question for you.
You use 4 Virtex 2 FPGA chips, and from the picture, it looks like you use
sockets to connect the FPGA to the surrounding components.
Where did you buy the sockets?
How did you wire wrap it? I mean, the distance between pins in Virtex 2 is
very small, right? So, how do you manage to wire wrap it or solder it
without using a machine? Does the distance between pins in the sockets wide
enough for one to wirewrap without using a machine?
You run the board at 40MHz, with all the soldering and wirewrapping, does
the noise matter at all in your project?

Hendra



Article: 68769
Subject: FPGA power supply circuits
From: Ben Popoola <b.popoola@ntlworld.com>
Date: Sat, 17 Apr 2004 10:17:12 +0100
Links: << >>  << T >>  << A >>
Hi,
	SRAM FPGAs have a start-up current spike greater than 1A.
TI have a FPGA power supply document on their web site, that provides
various power supply circuits for FPGAs.

Questions:

(1) What is the minimum input current needed - from an off-the-shelf
power supply - for use with the TI circuits ?



Cheers


Article: 68770
Subject: Protel 2004 for FPGA design?
From: "Leon Heller" <leon_heller@hotmail.com>
Date: Sat, 17 Apr 2004 12:17:40 +0100
Links: << >>  << T >>  << A >>
I've just received an evaluation copy of Altium Protel 2004. Although I'm
very happy with Pulsonix and am one of their beta-testers, I thought I'd see
what Altium's latest offering was like. They seem to be devoting as much, if
not more, effort to FPGA design in this product as to PCB design. Is anyone
actually using their FPGA stuff?

Leon



Article: 68771
Subject: Re: Huh, anybody wants to play some NES???
From: jaxlau@yahoo.com (Jacques athow)
Date: 17 Apr 2004 04:50:52 -0700
Links: << >>  << T >>  << A >>
> Jacques, first of all, congratulations! That's a really amazing project!
> I have a question for you.
> You use 4 Virtex 2 FPGA chips, and from the picture, it looks like you use
> sockets to connect the FPGA to the surrounding components.
> Where did you buy the sockets?
> How did you wire wrap it? I mean, the distance between pins in Virtex 2 is
> very small, right? So, how do you manage to wire wrap it or solder it
> without using a machine? Does the distance between pins in the sockets wide
> enough for one to wirewrap without using a machine?
> You run the board at 40MHz, with all the soldering and wirewrapping, does
> the noise matter at all in your project?
> 
> Hendra

Hi, for your questions:
we actually used 1 virtex2 xc2v1000 fg256 FPGA chip.
We did not use any socket at all. We didnt use any lense, and
everything was done within one week. We had a couple of team members
with good eye sight and with some training, they master the art of
soldering 1 mm pads!
So no socket of any kind

The first serious issue that we had was actually the ground bounces
that exist, because of inexistant ground plane. The way we resolved
this was a good planning at the beginning of the actual board design.
With a little bit of thought, it was decided to lay a sort of grid
around the FPGA chip, using wire and solder. All the chip gnd pins
were then connected, as well as those of the FPGA chip.

Initial test which was mostly static indicated no problem. Afterwards,
when we downloaded our first SOC module, the nintendo audio unit, the
6502 cpu and some game cartridge, it was noted that the sound played
fine, until you approach or touch some part of the circuitry. Then we
realized that any piece of metal would destabilized the whole circuit,
increasing the frequecy or decreasing it (the sound would be played
either faster or slower)...

This was a serious issue with the DCM, but we found out later that one
of the pins, from our sound dac, was left unconnected, and was
supposed to be grounded. Also, some wires, where the actual symptoms
were most noted, were cut to smaller length. Now it works without
problem for days.
The power consumption is about 180mA.
The noise matter in general, but I think in our case, at 40MHZ, and
max internal clock rate of 12.5MHZ, HS issues are not much of a
concern.

Here are the specs for the board

Virtex2 FPGA chip, XC2V1000 -4 FG256
entire soldered with common blue kynar prototyping wire
MODULAR DESIGN APPROACH AT THE BOARD LEVEL, EACH COMPONENT CAN BE
PHYSICALLY DISCONNECTED FROM THE POWER SUPPLIES (GOOD FOR DEBUGGING
PURPOSES)
dual flash memories AM29F101, we did a core for a famous flash/eprom
(starts with a W) programmer. We are using it as the main memory
interface to do our system development.
ADV7125 triple hs video dac is connected to the FPGA chip
AD5332 dual dac are used for the two sound channel, as per the
original NES
5 hc245 buffer chips, for voltage level translator
one 40mhz can oscillator

The HDL code was developed using VHDL

We did two 6502 cpu core
We also develop a four channel sound generator
We also did a graphic unit, using reverse engineer data obtained from
the net
All the cores are tested in FPGA silicon.

That was alot, alot of work. It started last year, may2003 and was
completed this week.

Jac

Article: 68772
Subject: Re: Protel 2004 for FPGA design?
From: Rene Tschaggelar <none@none.net>
Date: Sat, 17 Apr 2004 16:14:12 +0200
Links: << >>  << T >>  << A >>
Leon Heller wrote:
> I've just received an evaluation copy of Altium Protel 2004. Although I'm
> very happy with Pulsonix and am one of their beta-testers, I thought I'd see
> what Altium's latest offering was like. They seem to be devoting as much, if
> not more, effort to FPGA design in this product as to PCB design. Is anyone
> actually using their FPGA stuff?

Yes. Me not yet though.
Apparently you're not yet member of the DXP forums.
Have a look at the forum for DXP, available at the altium
and protel websites.

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

Article: 68773
Subject: Re: PLL and DLL
From: Rene Tschaggelar <none@none.net>
Date: Sat, 17 Apr 2004 16:18:26 +0200
Links: << >>  << T >>  << A >>
Muthu wrote:

> Hi,
> 
> What is the need for PLL / DLL ?
> 
> what kind of system requires this? When it is required?

The newer families of FPGAs run on frequencies where
1) it is hard to get oscillators
2) you wouldn't want these oscillators on your board for EMC reasons
3) the chips are too large to run on a single clock net

PLLs allow to step the frequency up from a usual clock.

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

Article: 68774
Subject: dumb question CPLD or FPGA
From: "Joseph Goldburg" <wizard1@SPAMnetspace.net.au>
Date: Sun, 18 Apr 2004 01:22:45 +1000
Links: << >>  << T >>  << A >>
What's the difference  between say the Xilinx Coolrunner CPLD
and the Xilinx 4000 FPGA series.

I noticed the coolrunner dev kit for $50 USD

Please reply to this new group and wizard1@netspace.net.au

Thanks in advance

Joseph





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