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"DJ" <reconfigurablecomputing@gmail.com> writes: > does anyone have a cracked copy of xilinx edk.... > can you help me getting it..? Yes, for US $595 I'll help you get it.Article: 78426
Dave wrote: > Hi, > > I am implementing a state machine in a FPGA using VHDL. > Several states are determined by 4 external event inputs (falling > edge) which occur asynchronously to the 25MHz FPGA clock (I might need > to increase to 50MHz). The events occur at random intervals of 10us or > more. > > I have a couple questions which someone may be able to guide me on: > > 1) Should I have a synchroniser (2-stage shift reg) at each of the 4 > event inputs before being sampled by the state machine to avoid > meta-stability problems? > > 2) I'm using the following VHDL code to detect a falling edge on the > event inputs. Is there a better way? > > process( clk, ev1, ev2, ev3, ev4, reset) > variable prev_ev1: std_logic; > variable got_ev1: boolean; > > <variables for other events omitted> > > begin > if (reset = '1') then -- reset the event states > prev_ev1 := event; > got_ev1 := false; > elsif (rising_edge(clk)) then > if (event = '0') then -- event signal is low > if (prev_ev1 = '1') then > got_ev1 := true; -- falling edge detected > end if; > prev_ev1 = '0' > else > prev_ev1 = '1'; > end if; > > <repeat edge detection for the other events> > > <process 'got_ev' flags in state machine & reset them> > end if; > end process; > > Any advice welcome! > Thanks > Dave Yes, you should use a resynchronizer, and avoid using the "greedy path". That is, the signal 'event' in your code above should be the output of a two-flop synchronizer; not the output of a single synchronization flop. Jonathan's comments about metastability being of little concern to you are accurate, but the danger is finite. The liklihood of a single synchronizer flop being metastable at the next clock edge is very small, but if it does go metastable it will eat into the setup time. If the path connected to the output takes up most of the period, then there is no margin for any excess clk->out time. If latency isn't an issue and flops are plentiful, then having extra synchronizer flops is a prudent idea. It is true though that a more common mistake is to synchronize a multibit bus without realizing that this will result in invalid values except in the case of Gray-coded logic. -KevinArticle: 78427
Thanks Newman, I made that change also and it seemed to help. At least it runs. Joel "newman5382" <newman5382@yahoo.com> wrote in message news:vKbLd.9279$JO2.713@tornado.tampabay.rr.com... > Joel, > I added the ucf file and added offset in of 4 ns for grins. When I went > into the dreaded gate level simulation debug. I noticed that > write_device_tb/uut/current_state_ffd2_94/rst > write_device_tb/uut/current_state_ffd2_94/srst > did not have the same delay values. I increased the testbench delay rst > value to 125 ns, and it appeared to help. > There may be some active reset minimum in the gate level simulation for > some type of reset on configuration thingy. > > -Newman > > "Weddick" <weddick@comcast.net> wrote in message > news:IaOdnWe-DuutgGDcRVn-ig@comcast.com... >> The only thing that I had put in the UCF file was the clock period. I >> will admit I don't know much about this file and what should be set. I >> attached the UCF file and help in additional settings would be >> appreciated. Actually the UCF file that I created was for the higher >> level project. So maybe the settings never got flowed down? >> >> Joel >> >> >> "newman5382" <newman5382@yahoo.com> wrote in message >> news:rE%Kd.8455$JO2.6607@tornado.tampabay.rr.com... >>> >>> "Weddick" <weddick@comcast.net> wrote in message >>> news:ZZOdnWsnGoUBzGHcRVn-gw@comcast.com... >>>>I am just starting with VHDL and have been doing software for the last >>>>20 >>>>years. My project that I am trying to get working is part of a memory >>>>controller which will allow different processes to request access to the >>>>memory. >>>> >>>> The portion of the code that I posted works great when I do the >>>> Behavioral >>>> Model Simulation. When I do the post-Place & Route VHDL Model >>>> Simulation >>>> the first write cycle does not work. You can see that it processes >>>> through the states but the data out and address lines don't change as >>>> expected. >>>> >>>> I would appreciate any help with this problem. Hopefully it's just >>>> something stupid. That always makes me feel better. >>>> >>>> Joel >>>> >>>> >>> >>> Joel, >>> When I compiled the source to gates, and ran the simulation, I got a >>> lot >>> of timing violations. >>> >>> In the testbench, how do you control the set up and hold of the inputs >>> to >>> the uut with respect to clk? (especially data_valid, rst, ack) Do you >>> constrain tbe implementation with timing constraints from a UCF file? >>> >>> -Newman >>> >>> >> >> >> > >Article: 78428
I guess I don't understand what your getting at. How should they be synchronized? (Example?) Is there a better way that I should be coding this so everything is synchronized? Thanks, Joel "vax, 9000" <vax9000@gmail.com> wrote in message news:ctjfao$prv$1@charm.magnus.acs.ohio-state.edu... > Weddick wrote: > >> The only thing that I had put in the UCF file was the clock period. I >> will >> admit I don't know much about this file and what should be set. I >> attached >> the UCF file and help in additional settings would be appreciated. >> Actually >> the UCF file that I created was for the higher level project. So maybe >> the settings never got flowed down? > > Your problem is that the inputs(rst, data_valid, ack) are not > synchronized. > Also I don't understand why "write" should be 'Z' some times. Also you'd > better synchronize your outputs too. > > vax, 9000Article: 78429
Hi All, Can anyone tell me the solution to solve the setup or Hold time violation when running the simulation? When i was running the simulation of my design, the simulator shows some warnings, which related to the setup time violation in a flip-flop with respect to CLK. Does anyone have the solution for this problem? Thanks.Article: 78430
Hi All, I have a Cyclone application with a long lifetime and a high realibility requirement (i.e. no subsequent CRC's and retries, the IGBT just turns on) I am trying to assess the MTBF of metastable events. I have 166MHz clock and 10kHz async. inputs with a single sync. latch. Latencies are best avoided so I'd rather not double sync. unless I have to. The Altera app. note gives an expression for MTBF based on the metastable time Tmet and two device dependant parameters (C1 and C2) Are these parameter values available for Cyclone ? Thanks, GaryArticle: 78431
Since I do not work for Altera, I cannot comment on their parameter values. But I can give you some general inputs: Your biggest problem is the 166 MHz clock rate, i.e. the short 6 ns clock period. You must do everything humanly possible to keep the interconnect + logic from the synchronizing flip-flop's Q to the next destination"s D as short as possible. If Altera flip-flops are similar to the Xilinx flip-flops that I have measured (and there is every reason to assume they are) then the metastable MTBF will change by a factor of a million (!) for every half nanosecond of extra "breathing room" you have on that path. And it would be really desirable to drive only one D from that Q, i.e. do not fan out the logic at that point. I think you can succeed. Peter Alfke, Xilinx Applications. ============================== Gary Pace wrote: > Hi All, > > I have a Cyclone application with a long lifetime and a high realibility > requirement (i.e. no subsequent CRC's and retries, the IGBT just turns on) > > I am trying to assess the MTBF of metastable events. I have 166MHz clock and > 10kHz async. inputs with a single sync. latch. Latencies are best avoided so > I'd rather not double sync. unless I have to. > > The Altera app. note gives an expression for MTBF based on the metastable > time Tmet and two device dependant parameters (C1 and C2) > > Are these parameter values available for Cyclone ? > > Thanks, > GaryArticle: 78432
Hello, Thanks to Andrea's help, I was able to confirm that I was properly setting-up the master write/read requests signals . I was able to narrow done the problem to the slave to master attachment interactions in the plb_ipif. For instance, when the my user_logic module issues a master read, the master attachment issues a read on the PLB bus and it seems to be executing successfully (all the ACKS go high at the appropriate moment on the PLB bus). After the master read, the slave attachment is supposed to perform a write to the "local" memory in my user_logic module. The Bus2IP signals (like Bus2IP_WrReq) from the slave attachment, which are supposed to toggle during a slave attachment write, do not toggle. Likewise, for a master write, the slave attachment should perform a local memory read, which also fails (no activity on the slave Bus2IP_x signals), so the master write is never completed since the slave read is not performed. I looked at the internal plb_ipif signals in simulation (ModelSim), which show that sa2ma_x and ma2sa_x have activity, but the activity eventually leads to errors. In summary, the Master to PLB bus interactions seem actually okay, but there is some failure within the slave <-> master attachments interactions (sa2ma_error signals is asserted during these failures), the whole transaction does not complete properly. Has anyone encountered such issues? I haven't changed the inputs/outputs of the plb_ipif instantiation that the "Create/Import IP" wizard generated. Andrea said that she just instantiated the plb_ipif manually (i.e. not with the Wizard). Has anyone else had to adopt this approach to get a master plb module working? Thanks, NN On Wed, 26 Jan 2005, Nju Njoroge wrote: > Hello Andrea, > > Thank for the response. I wrote a simple test pcore to get a feel for how > the plb_ipif module should respond. Below is snippet of the main code. The > summary of the code is that it issues a single beat write to an address, > then issues a read to the same location. There is a little counter that > waits after the reset signals have gone high before it starts the > write/read requests. Note that the BE, Data, Addr, buses etc. are held > constant well before the requests are made. Would you happen to have a > simple example of PLB master you wrote that works? I would like to see the > timing to get an idea why the M_Request and associated plb_ipif signals > are not being triggered. Also, what version of plb_ipif are you using? We > are using plb_ipif_v2_01_a (the one that has a master attachment). > > Thanks, > > Nju > > reg [6:0] counter; > wire counter_done; > > > // Logic for simple 7-bit coutnter > always @(posedge Bus2IP_Clk) > begin > if(Bus2IP_Reset) counter[6:0] <= 7'd0; > else if (counter < 7'd127) counter <= counter + 1'b1; > else counter <= counter; > end > > assign counter_done = (counter == 7'd127); > > assign IP2Bus_Data = 64'hfeeddeadbeefbead; > assign IP2Bus_Retry = 1'b0; > assign IP2Bus_Error = 1'b0; > assign IP2Bus_ToutSup = 1'b0; > assign IP2Bus_RdAck = Bus2IP_RdReq; > assign IP2Bus_WrAck = Bus2IP_WrReq; > > > assign IP2Bus_Addr = 32'h00000008; > assign IP2Bus_MstBE = 8'hf0; > assign IP2Bus_MstBurst = 1'b0; > assign IP2Bus_MstBusLock = 1'b0; > assign IP2Bus_MstNum = 5'h0; > assign IP2IP_Addr = IP2Bus_Addr; > > // Logic for requests > > // State machine for simple write, followed by read > reg [1:0] state, nxt_state; > > //State encoding > parameter COUNTING = 2'b00; > parameter WRITING = 2'b01; > parameter READING = 2'b10; > parameter DONE = 2'b11; > > always @(posedge Bus2IP_Clk) > begin > if(Bus2IP_Reset) state <= COUNTING; > else state <= nxt_state; > end > > always @(/*AUTOSENSE*/Bus2IP_MstError or Bus2IP_MstLastAck > or Bus2IP_MstTimeOut or counter_done or state) > begin > case(state[1:0]) > COUNTING: > nxt_state <= (counter_done == 1'b0) ? COUNTING: WRITING; > > WRITING: > nxt_state <= (Bus2IP_MstLastAck | Bus2IP_MstTimeOut | > Bus2IP_MstError) ? READING: WRITING; > READING: > nxt_state <= (Bus2IP_MstLastAck | Bus2IP_MstTimeOut | > Bus2IP_MstError) ? DONE: READING; > > DONE: > nxt_state <= DONE; > default: nxt_state <= COUNTING; > endcase // case(state[1:0]) > end // always @ (... > > assign IP2Bus_MstRdReq = (state == READING); > assign IP2Bus_MstWrReq = (state == WRITING); > > On Wed, 26 Jan 2005, Andrea Sabatini wrote: > > > Nju, > > > > I've been designing master PLB master modules using the PLB IPIF for quite a > > while now and, like in your case, the only think I could rely on were the > > two diagrams you referreded to in your message and the simulation results. I > > have to say that I did not follow the design flow suggested by Xilinx > > because I just instatiated the PLB IPIF inside my code and I did not use the > > Peripheral wizard. > > > > I think that the timing reported in those two diagrams is not correct > > becasue the signls Bus2IP_Cs and Bus2IP_CE are always asserted at the same > > point in time but the signals Bus2IP_RdCe, Bus2IP_WrCe, Bus2IP_RdReq and > > Bus2IP_WrReq, althought are always asserted at the same time, are alwas at > > least one clock cycles delayed respect to the previous two. > > > > To be honest, I do not think that that module is bug-free but so far it seem > > to behave correctly in our application. > > > > If you can be more specific about your problem maybe I can help you a little > > more. > > > > Regarding the documentation, I do not know if something more detaild exist. > > > > Regards, > > > > Andrea Sabatini > > > > > > > > > >Article: 78433
The simplest solution is to run your simulation at slower clock speed. But if you must run at the clock speed when there is a timing violation, you can change your coding style to be more synthesis friendly, or change your design that will accomplish the same goal without timing violation. HendraArticle: 78434
On 31 Jan 2005 18:40:40 -0800, spacexxspace@yahoo.com wrote: >Hi All, > >Can anyone tell me the solution to solve the setup or Hold time >violation when running the simulation? > >When i was running the simulation of my design, the simulator shows >some warnings, which related to the setup time violation in a flip-flop >with respect to CLK. Does anyone have the solution for this problem? Are these warnings related to external signals ? If yes, you can fix the setup/hold violations by managing the generation of signals in your test-bench. If they are internal DFF.Q to DFF.D violations on the same clock, for setups you just have to try harder to meet timing during synthesis/P&R and add pipelines, simplify logic etc. In this mode, it would be difficult to have hold violations in an FPGA as the clock tree is already generated and all flops have non-negative clk->Q delays.Article: 78435
HI, I'm looking for examples of a codesign. The process on a PC aided by the functions on a FPGA preferably using a serial(RS 232) interface. Can anyone help me with some documentation and examples? Regards, erjsArticle: 78436
vax, 9000 wrote: > The MAX II can tolerate 3.3V input, I believe. I read some TTL data sheets > but they seem all provide typical VOH(3.1V) and minimal VOH(2.4V) only. > The max VOH is usually not provided. Could I drive the CPLD i/o pins > directly, with the LSTTL outputs? OK, since nobody answered this question, I did a small experiment. I tested VOH of three TTL chips, F(airchild)74LS244, EL74LS14, DS8835. Vcc is 5.07V. Without load, the outputs are around 6.2V(strange?), 5.0V and 5.0V. With a 10K pull-down resistor, the outputs are around 3.5V, 3.5V, 3.5V. I used a digital multimeter(means high input resistance). So the answer is no, unless a serial resistor is used, and the input diode (in EPM1270, EPM2210) is enabled. vax, 9000 > > I will try to use some LVTTL to interface the CPLD, if LSTTL are not > qualified. Thank you. > > vax, 9000Article: 78437
Thank you for your responses, I have not done much scripting before but I feel that it can ease my work load. Doulos have a Tcl/Tk course that I might take. Best Regards, R.NArticle: 78438
vax, 9000 wrote: > vax, 9000 wrote: > > >>The MAX II can tolerate 3.3V input, I believe. I read some TTL data sheets >>but they seem all provide typical VOH(3.1V) and minimal VOH(2.4V) only. >>The max VOH is usually not provided. Could I drive the CPLD i/o pins >>directly, with the LSTTL outputs? > > OK, since nobody answered this question, I did a small experiment. I tested > VOH of three TTL chips, F(airchild)74LS244, EL74LS14, DS8835. Vcc is 5.07V. > Without load, the outputs are around 6.2V(strange?), 5.0V and 5.0V. With a > 10K pull-down resistor, the outputs are around 3.5V, 3.5V, 3.5V. I used a > digital multimeter(means high input resistance). > > So the answer is no, unless a serial resistor is used, and the input diode > (in EPM1270, EPM2210) is enabled. Where did you find the 3.3V MAX value ? The data I have gives 4V (DC)-4.5V (10% duty cycle) ? On that basis, you would just need to enable the input diode, and from your numbers, draw < 300uA clamping current. You WILL need to stick to bipolar output structures, and avoid CMOS which may be dangerous in the long term. -jgArticle: 78439
Hi, Wojciech Zabolotny wrote: > Yes I know. The price of RT54SX was unacceptable for us :-(. There will be > above 200 boards with that chip, and above 1000 boards with Xilinx'es... This number could be cheaper by an ASIC, if your time schedule allows the extra time. >> If you need a specific element, why not instanciating it by hand? >> > Well, I just couldn't discover how to instantiate the FF by hand in the > Actel platform... In designer, you could choose to place by hand. I guess that you have to modify the edif netlist before reading in, to get cells, that could be set by hand on a c-cell place. Remember that a FF could be build from complete combinatorial gates. bye Thomas -- Emailantworten bitte an thomas[at]obige_domain. Usenet_10 ist für Viren und Spam reserviertArticle: 78440
Jim Granville wrote: > vax, 9000 wrote: >> vax, 9000 wrote: >> >> >>>The MAX II can tolerate 3.3V input, I believe. I read some TTL data >>>sheets but they seem all provide typical VOH(3.1V) and minimal VOH(2.4V) >>>only. The max VOH is usually not provided. Could I drive the CPLD i/o >>>pins directly, with the LSTTL outputs? >> >> OK, since nobody answered this question, I did a small experiment. I >> tested VOH of three TTL chips, F(airchild)74LS244, EL74LS14, DS8835. Vcc >> is 5.07V. Without load, the outputs are around 6.2V(strange?), 5.0V and >> 5.0V. With a 10K pull-down resistor, the outputs are around 3.5V, 3.5V, >> 3.5V. I used a digital multimeter(means high input resistance). >> >> So the answer is no, unless a serial resistor is used, and the input >> diode (in EPM1270, EPM2210) is enabled. > > Where did you find the 3.3V MAX value ? > The data I have gives 4V (DC)-4.5V (10% duty cycle) ? > On that basis, you would just need to enable the input diode, and from > your numbers, draw < 300uA clamping current. I think you are right. I didn't read the datasheet carefully. Now I find that the clamping diodes only exist within i/o bank 3, and there is power-up sequence restriction too. Another problem is that I failed to find the allowed clamping diode current. vax, 9000 > > You WILL need to stick to bipolar output structures, and avoid CMOS > which may be dangerous in the long term. > -jgArticle: 78441
> Hi All, > > Can anyone tell me the solution to solve the setup or Hold time > violation when running the simulation? > > When i was running the simulation of my design, the simulator shows > some warnings, which related to the setup time violation in a flip-flop > with respect to CLK. Does anyone have the solution for this problem? > Thanks. Make sure your testbench is not toggling signals immediately beside your clock edges. Put suitable delays in between edges and toggles that mimic the actual behaviour of your hardware. If it is not for real hardware try using a 1/4 of a clock period or something... Cheers, KenArticle: 78442
In one of the last posts I read the following: >It is true though that a more common mistake is to synchronize a >multibit bus without realizing that this will result in invalid values >except in the case of Gray-coded logic. >-Kevin Does that mean that using a multi-stage flip flop chain to synchronize the asynchronous input bus will lead to invalid values ? Please shed some light on that. Kind regards AndréArticle: 78443
>1) Should I have a synchroniser (2-stage shift reg) at each of the 4 >event inputs before being sampled by the state machine to avoid >meta-stability problems? Do you want your circuit to work all of the time or is most of the time good enough? There are tricks to building reliable circuits without the classic pair of FFs to synchronize an async input. But they are asking for troubles. The main problem is that the typical tool package doesn't support checking to make sure you get it right and don't break something with an innocent change sometime later on. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 78444
On 31 Jan 2005, Gabor wrote: > Don't know about Altera, but Atmel recently got into the Rad Hard > business: > http://www.atmel.com/ad/radhardfpga/default.asp?source=enews > Unfortunately these are SRAM based. One of the Actel's SXA advantages is their nonvolatility... Regards, WojtekArticle: 78445
On Tue, 1 Feb 2005, Thomas Stanka wrote: > Wojciech Zabolotny wrote: > > Yes I know. The price of RT54SX was unacceptable for us :-(. There will be > > above 200 boards with that chip, and above 1000 boards with Xilinx'es... > > This number could be cheaper by an ASIC, if your time schedule allows the > extra time. > Unfortunately, the additional requirement is that the firmware in Xilinx'es should be upgradeable, so they can not be replaced with ASICs... The Actels are needed to "wake up" other parts of the system by reading their configuration from the local FLASH (with ECC protected redundant configuration data), so they have to be nonvolatile. Maybe the FLASH based Actels could be sufficient for this purpose, but I'm afraid to use FLASH configured parts in irradiated environments. (The FLASH memories are acceptable, because there will be a way to refresh their contents). Additionally the Actels should store some user data, and send them to Xilinx'es after reconfiguration. That's what are these reduntant registers for... -- Thanks & regards, Wojtek ZabolotnyArticle: 78446
ALuPin wrote: > In one of the last posts I read the following: > >>It is true though that a more common mistake is to synchronize a >>multibit bus without realizing that this will result in invalid values >>except in the case of Gray-coded logic. > > Does that mean that using a multi-stage flip flop chain to synchronize > the asynchronous input bus will lead to invalid values ? Since the indivdual bits of the multi bit bus may change at their own time, sampling at odd intervals may result in sampled bus pattern that are just temporary in nature. Thus the sampled pattern may be wrong. Only the gray code is save to sample at odd intervals as only one-bit changes are allowed. Apart from that, the multi bit bus could also contain its own clock, showing when the data is valid. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 78447
Hi all, I was given an EDIF netlist for evaluation of IP core. I could synthesize it and see and everything. But i am unable to check functional simulation of the core as to how it works. Is there any way to do it with Modelsim and Xilinx tools thanks in advanceArticle: 78448
and a after place and route simulationnal could'nt be good?? you could generate a post place and route with xilix fondation in implement project>place and route >generate place and route simulation model it should generate you a model in vhdl that you can use in modelsim alexis <vasus_ss@yahoo.co.in> a écrit dans le message de news: 1107256079.013034.160220@f14g2000cwb.googlegroups.com... > Hi all, > > I was given an EDIF netlist for evaluation of IP core. I could > synthesize it and see and everything. But i am unable to check > functional simulation of the core as to how it works. Is there any way > to do it with Modelsim and Xilinx tools > > thanks in advance >Article: 78449
Peter - Do you have any documentation on this? Thanks! Ben "Peter Alfke" <alfke@sbcglobal.net> wrote in message news:1107227844.242806.124150@c13g2000cwb.googlegroups.com... > Since I do not work for Altera, I cannot comment on their parameter > values. But I can give you some general inputs: > Your biggest problem is the 166 MHz clock rate, i.e. the short 6 ns > clock period. You must do everything humanly possible to keep the > interconnect + logic from the synchronizing flip-flop's Q to the next > destination"s D as short as possible. If Altera flip-flops are similar > to the Xilinx flip-flops that I have measured (and there is every > reason to assume they are) then the metastable MTBF will change by a > factor of a million (!) for every half nanosecond of extra "breathing > room" you have on that path. > And it would be really desirable to drive only one D from that Q, i.e. > do not fan out the logic at that point. > I think you can succeed. > Peter Alfke, Xilinx Applications. > ============================== > Gary Pace wrote: > > Hi All, > > > > I have a Cyclone application with a long lifetime and a high > realibility > > requirement (i.e. no subsequent CRC's and retries, the IGBT just > turns on) > > > > I am trying to assess the MTBF of metastable events. I have 166MHz > clock and > > 10kHz async. inputs with a single sync. latch. Latencies are best > avoided so > > I'd rather not double sync. unless I have to. > > > > The Altera app. note gives an expression for MTBF based on the > metastable > > time Tmet and two device dependant parameters (C1 and C2) > > > > Are these parameter values available for Cyclone ? > > > > Thanks, > > Gary >
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