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I also had problems with impact 10.1 (on Virtex-5 though) I recommend that you use impact 9.2. but I am afraid you have to download the whole thing? Cheers,Article: 134476
On Aug 11, 5:17=A0am, MarkAren <markare...@yahoo.com> wrote: > On Aug 11, 8:52=A0pm, Jim Granville <no.s...@designtools.maps.co.nz> > wrote: > > > > > > > MarkAren wrote: > > > Hi All, > > > > I have a project that requires a small PLD and have honed in on the > > > Altera series. > > > > Can someone explain the difference between the EPM7064x and the > > > EPM3064x series please. > > > > Each shares: same number of CLBs, Icc and Fmax, JTAG. > > > > The 7k seems newer, but also about twice the price of the 3k > > > (Digikey). > > > This was a strange exersise in marketing. IIRC > > > The 3000 series was a lower cost target, but just very slightly cripple= d > > from the 7000 series. (ie not quite pin compatible. WHY do that?!) > > > I think the 3000 series offers less IO on given device. > > > I see the 7000 series has lost link-preference on the Altera website. > > > These days, Altera's CPLDs are somewhat trailing edge, with Lattice > > 4000ZE being the newest technology (most recently released), followed b= y > > Atmel's ATF15xxBE, and then Xilinx XC2Cxx series. > > > Speaking of Altera and CPLD's - whatever became of the touted > > Altera MAX III CPLDs ? > > > Google finds a 2004 Altera road map that says : > > MAX III CPLDs > > - Intent: Solve Additional Board Management Issues > > - Adjust Density, Power & Cost According to Market Requirements > > > Seems the plug was pulled on this ? > > > -jg > > Hi Jim, > > Thanks. Glad I am not going crazy. > > I am looking at a possible NIOS II project on one of their much larger > parts. Main interest there is steepness and altitude of learning > curve... Does look quite interesting though. > > I see you are also in NZ. > > -mark- Hide quoted text - > > - Show quoted text - There may be a difference in silcon fab processing, which may account for some of the cost difference in the two series of parts. Trying to recall from a conversation I had with an Altera FAE a few years back, Altera was trying to get away from a lot of the 7000 series process technologies because they were large and old and that this was going to in turn drive the cost of them up. This was especially true for the 7000S (5V) parts. I have used both series of parts and the Cylcone FPGAs and had excellent results with all of them. I even had a PCB foo_bar where I accidentally put a set of pins to 7Vdc via a pull up resistor, which thanfully limited the current. Of course this massively exceeded the device limits, even for being 5V tollerant. Surprisingly, the devices on all the prototypes continued to function reliably for several months before I respun the board to correct the problem. As far as a NIOS2 project, if you decide to go that route, best of luck. I tried unsuccessfully to implement one. I ran into trouble getting the flash memory, even the AMD varient that they suggested to work correctly with their (Athalon?) bus architecture. I also experienced super lengthy compile times, though I was using a modest PC. One other thing to conisder is that they use Eclipse for the basis of the development environement, which was supposed to be a "killer" app that never really impressed me.Article: 134477
On 12 =D7=90=D7=95=D7=92=D7=95=D7=A1=D7=98, 13:19, Antti <Antti.Luk...@goog= lemail.com> wrote: > On 12 aug, 10:27, Pinhas <bk...@hotmail.com> wrote: > > > Hi > > I need help in completeing an SDIO open source code. > > >http://bknpk.no-ip.biz/SDIO/doc_1.htmlhttp://bknpk.no-ip.biz/ > > what help do you want, need or expect? > > the SDIO specs are all under NDA and there are also no known > opensource SDIO software drivers where to "derive" missing > information. > > Antti close open issues as in http://bknpk.no-ip.biz/SDIO/open_issues.html Test it on board/FPGA.Article: 134478
My Spartan 3 FPGA kit came with a cable that's supposed to plug into a DB25 connector. However, the laptop computer I'm using for the kit does not have any such jack on it. What adapter can I use? My laptop has USB ports and a DB9 but no DB25. Jason Hsu http://www.jasonhsu.com/Article: 134479
On Aug 12, 12:01=A0pm, Jason Hsu <jason_...@my-deja.com> wrote: > My Spartan 3 FPGA kit came with a cable that's supposed to plug into a > DB25 connector. =A0However, the laptop computer I'm using for the kit > does not have any such jack on it. > > What adapter can I use? =A0My laptop has USB ports and a DB9 but no > DB25. > > Jason Hsuhttp://www.jasonhsu.com/ Something like this: <http://sewelldirect.com/DB9toDB25.asp> 30 seconds to find it with a search engine!Article: 134480
On 2008-08-12, Jason Hsu <jason_hsu@my-deja.com> wrote: > My Spartan 3 FPGA kit came with a cable that's supposed to plug into a > DB25 connector. However, the laptop computer I'm using for the kit > does not have any such jack on it. > > What adapter can I use? My laptop has USB ports and a DB9 but no > DB25. What you need is a printer port. A better solution is to buy a Xilinx platform cable USB and give the parallel cable to someone who can use it. (someone else pointed you at a db9-db25 adapter, probably for serial, which is not useful to you) -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 134481
OK, I ordered the JTAG/USB cable from Digilent.Article: 134482
On Aug 8, 11:37=A0pm, Jamie Morken <jmor...@shaw.ca> wrote: > Hi, > > Does anyone know of an appnote showing the recommended breakout routing > for the cyclone3 484BGA package? =A0I am currently working on a PCB with > this IC and am wondering about the most efficient way to break it out. > > I am using tiny vias between the 1mm pitch BGA pads, mainly wondering > the best places to put the 3.3V supply and PLL supply decoupling caps, > and the best way to deal with the 3.3V and GND pins on the third and > fourth rows in respectively. > > cheers, > Jamie When working with Altera devices, one helpful place is <www.altera.com> This might be what you're looking for: <http://www.altera.com/support/ kdb/solutions/rd08251999_6829.html> General guidelines: 1) Get the power pins to the power plane as directly as possible. 2) Minimize the (effective) distance between the bypass cap and the bypassed pin. Xilinx also published routing guidelines; it's useful data for any FPGA in a BGA.Article: 134483
On Aug 12, 1:25=A0pm, Ben Jackson <b...@ben.com> wrote: > > (someone else pointed you at a db9-db25 adapter, probably for serial, > which is not useful to you) > Oops. I do have programming pods with db25 serial, but I should have realized that with anything as new as a spartan3 the db25 would be parallel, not serial.Article: 134484
"bart" <bart.borosky@latticesemi.com> wrote in message news:3ce5a071-bb41-40db-947b-3b4e243d1ef1@y21g2000hsf.googlegroups.com... > Lattice is holding a webcast tomorrow, Wednesday, August 13th, > presenting our PCI Express IP offerings, various hardware evaluation > platforms, and the associated demos and reference designs for > evaluating PCI Express. The webcast is titled: "Evaluating and > Enhancing PCI Express Performance." The presenters will be Sid Mohanty > and Jamie Freed, from our strategic marketing and applications > engineering groups, respectively. > > If you're interested, the event takes place live at 11am Pacific, > 18:00 GMT. In addition, you will be able to view this webcast archive > on-demand, at your convenience, starting a few hours after the live > event takes place. Is it really going to happen this time? I signed up for it last time it it was announced, but it was postponed. Half the system didn't realize this, and much confusion ensued.Article: 134485
On Aug 11, 5:07=A0pm, "KJ" <kkjenni...@sbcglobal.net> wrote: > "Ben Jackson" <b...@ben.com> wrote in message > > news:slrnga1e1b.1ep2.ben@saturn.home.ben.com... > > > I'm taking gamma-corrected RGB and displaying it on a linear device. = =A0If > > you consider R, G, B in [0,1) then R' =3D R ** 2.2 and so on. =A0For my= first > > version I just instantiated an 8-bit 'square' megafunction in Quartus, > > which turns out to be 30 LUTs (possibly less at map time because I'm > > ignoring the lower 8 bits of the output). =A0Obviously the power of 2 i= sn't > > quite a power of 2.2. > > Odd why it should take any LUTs at all...or are you targetting something > that doesn't have hardware multipliers? > > > After testing a RAM-based lookup table to do 2.2, > > I decided to build the equivalent case statement and see how it worked > > out. =A0119 LUTs. > > Doesn't sound like a lookup table got implemented using internal device > memory...or are you targetting something that doesn't have internal memor= y? > > Let's see, no hardware multipliers, no internal memory...my god man, what > are you using, self-assembling carbon nanotube based logic? > > > The table has many repeated value at the low end and skips some values = at > > the high end. =A0The transition points between runs of values (at the l= ow > > end) and the exact values (at the high end) could be shifted "slightly" > > with little quality penalty but possibly space savings. =A0Is there a > > methodical way to minimize the logic by allowing these slight errors? = =A0I > > can't just 'x' some values because I care about monotonicity. > > > (and yes, I'm aware that my internal color path should probably be wide= r > > than my output 8 bits, at which point this may become moot, but I'm sti= ll > > curious) > > See the link below for how I did an sRGB->RGB conversion function. =A0Cle= aner > and easier to validate than a case statement. > > http://groups.google.com/group/comp.lang.vhdl/browse_frm/thread/b2e4b... > > Once you've got the constants computed, don't forget to put it into a > synchronous process otherwise it will get implemented in LUTs rather than > internal memory. =A0I'm guessing that's what happened with your case stat= ement > lookup table. > > i.e. Gazouta <=3D Lookup(Gazinta) when rising_edge(Clock); > > Kevin Jennings When you use a RAM for code conversion, a dual-ported RAM can be twice as useful, if you can use both ports independently to do the same conversion algorithm. Just my $0.02 worth... Peter AlfkeArticle: 134486
Jason Hsu wrote: > OK, I ordered the JTAG/USB cable from Digilent. Note that Digilent's JTAG/USB cable does not work with the Xilinx Impact program. You'll have to use Digilent's programming software or find other software that supports that cable. That also means that the Digilent cable doesn't support Xilinx Chipscope, or the EDK debugger.Article: 134487
On Aug 11, 7:47=C2=A0am, Pinhas <bk...@hotmail.com> wrote: > On 11 =D7=90=D7=95=D7=92=D7=95=D7=A1=D7=98, 03:23,vorange<orange...@yahoo= .com> wrote: > > > > > > > On Aug 11, 1:20=C2=A0am,vorange<orange...@yahoo.com> wrote: > > > > Newbie here. =C2=A0I'm trying to learn fpga (xilinx with verilog). = =C2=A0So get > > > ready for weeks of silly questions coming your way as i try to figure > > > this thing out. > > > > Question : > > > > I remember that Xilinx Webpack had examples of Verilog code neatly > > > arranged in a list. =C2=A0Code to do a shift and so on - stuff you co= uld > > > just cut and paste into your code and just change the name of the > > > variables. > > > > I download Xilinx Webpack now and I cannot find it. =C2=A0Where is it= ? > > > Wait! =C2=A0I think I found it. > > > Click on the "lightbulb icon" :-) > > > Its called Language Templates. =C2=A0 Choose from the expanding menus. > > > Alright, we're off to a good start. > > There are many examples for using xilinx tools and verilog at:http://bknp= k.no-ip.bizhttp://bknpk.no-ip.biz/LEON/AHB_APB_leon/AHB_APB_verilog.html > > As well as free usb and sdio code.http://bknpk.no-ip.biz/usb_invitation_f= or_final_pj.htmlhttp://bknpk.no-ip.biz/SDIO/doc_1.html- Hide quoted text - > > - Show quoted text - I visited the links and quite frankly I can barely understand that website. The website itself is poorly organized. Whatever it is, its not for a beginner like me. I do like the doggy pics though.Article: 134488
On Aug 11, 2:17 am, MarkAren <markare...@yahoo.com> wrote: > > Thanks. Glad I am not going crazy. > > I am looking at a possible NIOS II project on one of their much larger > parts. Main interest there is steepness and altitude of learning > curve... Does look quite interesting though. > > -mark I found the NIOS-II to be easier to learn than MicroBlaze. I will recommend that you learn either with a supported board; my bias against MicroBlaze may be be because my 1st attempt was on an unsupported board. The eclipse interface is usable, but because it's so highly integrated with their system builder, you have to really hunt to find bits that need to be changed for custom boards. At least I did. Regarding CPLD's, I like the MAX-II. Cheap dev kits are available, and 1270 LE's is a *lot*. They can be clocked pretty fast, too.Article: 134489
Hello, I am an engineer (relatively new one) )designing solutions using FPGA's ... I came across Microblaze soft core processor from Xilinx and purchased EDK v9.2i .... Though there is much detail of its architecture and "features" at Xilinx site but there are not many examples and application notes for Microblaze ... I wanted to know more about its application, use and "real" benefits in commercial market. Let me know if anyone here knows how and exactly where this soft core processor is used (not only market but solutions/projects) and is it any good. Hope there are Microblaze "users" around ! Ghazal JavedArticle: 134490
On Aug 13, 7:56=A0am, Ghazal <gzl.ja...@gmail.com> wrote: > Hello, > =A0 =A0I am an engineer (relatively new one) )designing solutions using > FPGA's ... I came across Microblaze soft core processor from Xilinx > and purchased EDK v9.2i .... Though there is much detail of its > architecture and "features" at Xilinx site but there are not many > examples and application notes for Microblaze ... I wanted to know > more about its application, use and "real" benefits in commercial > market. > =A0 =A0Let me know if anyone here knows how and exactly where this soft > core processor is used (not only market but solutions/projects) and is > it any good. > =A0 =A0Hope there are Microblaze "users" around ! > Ghazal Javed Microblaze can save you a lot of design trouble If you need user interface or you have time non-critical processes to implement. Well, the cheapest way is to buy a Spartan3E Starter Kit and try some of the reference designs: http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm Cheers, Ales GuruArticle: 134491
Ghazal wrote: > Hello, > I am an engineer (relatively new one) )designing solutions using > FPGA's ... I came across Microblaze soft core processor from Xilinx > and purchased EDK v9.2i .... Though there is much detail of its > architecture and "features" at Xilinx site but there are not many > examples and application notes for Microblaze ... I wanted to know > more about its application, use and "real" benefits in commercial > market. > Let me know if anyone here knows how and exactly where this soft > core processor is used (not only market but solutions/projects) and is > it any good. > Hope there are Microblaze "users" around ! > Ghazal Javed I've worked with several other embedded FPGA softprocessors. Microblaze is exceptionally good because of the split development cycle for software and fpga cores. Software can be patched into the core which makes the whole development cycle very efficient. Although there are not very much reference designs and the documentation is lacking in many ways, especially when starting (I assume they want to push you to attend an expensive course...) it's not difficult to get simple applications working in a short time. I had some problems to get the installation working under linux, but also this works fine now. You can buy the spartan 3A dsp 1800 board for development (there were some problems with other boards). For help you can always ask here. TacoArticle: 134492
I've found it easiest to create a constant is_used mask that mimics the structure of the register array (so many words by so many bits, etc.). Simply AND the written and read data bits with that mask, and the synthesis tool will optimize away the register bits that are not used (replacing them with constant zeroes). In the old days, I'd use a for-generate/if-generate loop to infer the tri-state buffers for reading each bit based on the mask. In creating the register and bit assignments, I create integer constants for register address and location of individual bits. For ranges of bits (bit fields), I create a vector constant with the desired range, such that it can be accessed as: register(address)(field'range). Then creating the masks is a self documenting initialization statement: constant is_used : reg_array_type := (register_name => (unused_bit_name, unused_field_name'range => '0', others => '1'),...); Alternatively, you can list the used bits and default the others to 0, depending on which list is shorter. I also use a writable mask (register level, not bit level, since we generally decree that all cpu-writable registers return their written data when read) to handle read-only vs read=write registers in the same array. AndyArticle: 134493
Hello again, thanks for the nice tips I got last time! But... I am currently desperately trying to get the ll_temac working with EDK 10.1 on the ML403 board. What I did: Create a design using the base system builder. Used emaclite. Compiled. Works out of the box with u-boot and linux. Then I created a new design using the bsb file from the former. I just changed from emaclite to ll_temac. Tried with and without dma. Both leads to the result that my board does nothing and I cannot even connect to the ppc by means of xmd. Simply nothing happens. I don't know what's wrong. Perhaps there's an EDK bug? Or do I have to do something special? Any help is appreciated! Thanks, Philipp -- You have to reboot your computer after powerfail? Haha! http://h316.hachti.deArticle: 134494
On 13 Aug, 06:16, LittleAlex <alex.lo...@email.com> wrote: > On Aug 11, 2:17 am, MarkAren <markare...@yahoo.com> wrote: > > > > > Thanks. Glad I am not going crazy. > > > I am looking at a possible NIOS II project on one of their much larger > > parts. Main interest there is steepness and altitude of learning > > curve... Does look quite interesting though. > > > -mark > > I found the NIOS-II to be easier to learn than MicroBlaze. I will > recommend that you learn either with a supported board; my bias > against MicroBlaze may be be because my 1st attempt was on an > unsupported board. > > The eclipse interface is usable, but because it's so highly integrated > with their system builder, you have to really hunt to find bits that > need to be changed for custom boards. At least I did. > > Regarding CPLD's, I like the MAX-II. Cheap dev kits are available, > and 1270 LE's is a *lot*. They can be clocked pretty fast, too. Fiddled about with NIOS II, quite big it was. Decided to make my own processor design, 1270 LEs is a lot, you can fit a 25% processor on there and have lots of room left for I/O. The lack of on board memory is the worst bit, but then not all things need more than the flash provided. Home brew processor design has advantages of knowing your own tools when you make them, when you make them! I reckon the next version of my processor will work as advertized. Then I'll make a simple tool chain in Java2ME. I'm thinking programs on old recycled SIM cards in the 1.6K of SMS storage :-). cheers jackoArticle: 134495
On Aug 13, 7:27=A0am, taco <b...@joepie.org> wrote: > Ghazal wrote: > > Hello, > > =A0 =A0I am an engineer (relatively new one) )designing solutions using > > FPGA's ... I came across Microblaze soft core processor from Xilinx > > and purchased EDK v9.2i .... Though there is much detail of its > > architecture and "features" at Xilinx site but there are not many > > examples and application notes for Microblaze ... I wanted to know > > more about its application, use and "real" benefits in commercial > > market. > > =A0 =A0Let me know if anyone here knows how and exactly where this soft > > core processor is used (not only market but solutions/projects) and is > > it any good. > > =A0 =A0Hope there are Microblaze "users" around ! > > Ghazal Javed > > I've worked with several other embedded FPGA softprocessors. Microblaze i= s > exceptionally good because of the split development cycle for software an= d > fpga cores. Software can be patched into the core which makes the whole > development cycle very efficient. Although there are not very much > reference designs and the documentation is lacking in many ways, especial= ly > when starting (I assume they want to push you to attend an expensive > course...) it's not difficult to get simple applications working in a sho= rt > time. I had some problems to get the installation working under linux, bu= t > also this works fine now. > You can buy the spartan 3A dsp 1800 board for development (there were som= e > problems with other boards). For help you can always ask here. > Taco Besides the Xilinx site, you can find additional examples for many of the Xilinx Spartan boards on the Avnet Design Resource Center (www.em.avnet.com/drc). The 1800A board mentioned by Taco has several MicroBlaze designs (www.em.avnet.com/spartan3a-dsp). BryanArticle: 134496
Hi, I don't know why whenever I try to connect via XMD to a preloaded Ultracontroller-II design, I get the following error: ERROR: PowerPC405 Version UNKNOWN. The PowerPC405 Config String is Not Valid : 0xffffffff. I'm working with an ml403 v4fx board. I then switch back to SYS ACE and XMD works again, i.e. overwrite my FPGA. Another issue that I'm not sure about is the following: I'm trying to route a clock through one of the gpio's but can't scope anything. Is it to do with the DEBUGHALT method used by UC? This Ultracontroller thing has given me some fair grief already. Would be grateful for any insight/tip. Cheers, -MannyArticle: 134497
I am looking for a development board with USB Interface for hardware- in-loop. I don't think I want to mess with USB. I just want to use some easy to use board which will allow me to transfer data (at high speed) to-fro the board. I saw board from www.easyfpga.com and www.opalkelly.com But I wasn't sure.. Anyone has soem first hand experience with these boards? How good are they for new-bie? Any recommendations?Article: 134498
Hi Nirav, you said your focus is on high speed data transfer. How about the EFM-01 Board from www.cesys.de/index_en.html The easyfpga-board has a maximum transfer rate of 8 Mbit (FTDI to FPGA) because it's just an usb to RS232 converter. (Sufficient?) Cesys and opalkelly both use the Cypress FX2 chip which provides a parallel bus interface to the FPGA with nearly full USB2 transfer rate. Now you have to compare how the vendors support the FX2 interface and the software development on the host side. And of course what size of FPGA you need (500Kgates vs 4000KGates+SDRAM), which depends on the application you have in mind. Have a nice synthesis Eilert Nirav schrieb: > I am looking for a development board with USB Interface for hardware- > in-loop. > I don't think I want to mess with USB. > I just want to use some easy to use board which will allow me to > transfer data (at high speed) to-fro the board. > > I saw board from www.easyfpga.com > and www.opalkelly.com > > But I wasn't sure.. > Anyone has soem first hand experience with these boards? > How good are they for new-bie? > > Any recommendations? >Article: 134499
LittleAlex wrote: > On Aug 8, 11:37 pm, Jamie Morken <jmor...@shaw.ca> wrote: >> Hi, >> >> Does anyone know of an appnote showing the recommended breakout routing >> for the cyclone3 484BGA package? I am currently working on a PCB with >> this IC and am wondering about the most efficient way to break it out. >> >> I am using tiny vias between the 1mm pitch BGA pads, mainly wondering >> the best places to put the 3.3V supply and PLL supply decoupling caps, >> and the best way to deal with the 3.3V and GND pins on the third and >> fourth rows in respectively. >> >> cheers, >> Jamie > > When working with Altera devices, one helpful place is > <www.altera.com> > > This might be what you're looking for: <http://www.altera.com/support/ > kdb/solutions/rd08251999_6829.html> > > General guidelines: > 1) Get the power pins to the power plane as directly as possible. > 2) Minimize the (effective) distance between the bypass cap and the > bypassed pin. > > Xilinx also published routing guidelines; it's useful data for any > FPGA in a BGA. Hi, Thanks, I downloaded 484-pin.zip (layout gerbers) from http://www.altera.com/support/software/download/gerber/dnl-gerber.html These gerbers don't seem to show the routing of the central block of pins on this FBGA package, not sure if the gerbers are incomplete or if its just my gerber viewer, anyone have Altium / ACCEL to take a look at those files included in the zip file? Accel PCB layout file from ACCEL software pcb Layout file from the ACCEL layout tool cheers, Jamie
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