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Messages from 133575

Article: 133575
Subject: Re: Spartan3: INIT_B doesn't go LOW after PROG_B goes LOW in 2% of
From: wzab <wzab01@gmail.com>
Date: Fri, 4 Jul 2008 01:57:23 -0700 (PDT)
Links: << >>  << T >>  << A >>
I have found the following post: http://forums.xilinx.com/xlnx/board/message?board.id=Virtex&thread.id=1188
So as I can see it was more common problem.

In the part of my system I have switched to monitoring of the DONE
line instead of the INIT line to detect, that the device have been
deconfigured. Unfortunately in some chips the previous policy is
almost hardcoded (they are the FLASH based CPLDs, which must be
removed from the system to be reprogrammed).

Article: 133576
Subject: Re: Have you ever experimented some problem with External Memory?
From: Pablo <pbantunez@gmail.com>
Date: Fri, 4 Jul 2008 03:34:54 -0700 (PDT)
Links: << >>  << T >>  << A >>
Thanks so much for your replies.

I have just passed multiple memories tests. every thing works fine.
But i have detected something abnormal when I used multiple threads.
So it seems to be a problem of re-entrant threads.

Again, my best regards

pablo

Article: 133577
Subject: Re: OPB_CENTRAL_DMA
From: Pablo <pbantunez@gmail.com>
Date: Fri, 4 Jul 2008 03:40:38 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 4, 10:34 am, Guru <ales.gor...@email.si> wrote:
> On Jul 3, 2:32 pm, Pablo <pbantu...@gmail.com> wrote:
>
> > Has anybody used central_dma to copy data between peripherals and
> > processors, or between two buffers in bram mermory. I have added it to
> > the design and configure but, I receive a DMA BUS TIMEOUT.
>
> > Best Regards
>
> Obviously one of the addresses you are trying to access does not
> exist. Check the address map.

This was my first opinion, so I create two buffers in internal memory
as follows:

#include "xparameters.h"
#include "xdmacentral.h"
#include "xutil.h"

//====================================================
#define uint	unsigned int
void dma_init(uint config);
void dma_transfer (int *src, int *dst, uint length);

int main (void) {
	int i;
	int array[100];
	int array1[100];
	for (i = 0; i < 100 ; i++) {
		array[i]=1;
		array1[i]=0;
	}
	dma_init(0xC0000004);
	dma_transfer(&array[0],&array1[0],60);
	return 0;
}



// Function to control DMA

void dma_init(uint config) {
	int *dma = (int *)0x41e00000;
	*dma = 0xA; // Reset
	dma++;
	*dma = config; // Config
}
void dma_transfer (int *src, int *dst, uint length) {
	int *dma = (int *)0x41e00008;
	*dma = (int)src; // Src Address
	dma++;
	*dma = (int)dst;
	dma++;
	*dma = length;




> Otherwise the CENTRAL_DMA has low performance since the data needs to
> travel twice: source_peripheral -> DMA and DMA ->
> destination_peripheral
> Not to mention that is not capable of long bursts.
>

Is it possible to avoid this timeout?

> Cheers,
>
> Guru

Guru I have seen a post in which you said that dma registers are
located at:
baseaddr + 0x400.

but in the documentation it said that registers positions are:
baseaddr + 0x4.

am I ok?

again, my best regards

pablo


Article: 133578
Subject: Single ended interface at 70Mhz for FPGAs
From: Goli <togoli@gmail.com>
Date: Fri, 4 Jul 2008 04:10:43 -0700 (PDT)
Links: << >>  << T >>  << A >>
hi,

I am looking for connecting my proprietary 8 bit bus interface across
two Xilinx FPGAs across the back plane, (10 inch trace). I dont want
to use differential as that would take lot of pins, Is there any
single ended interface that I can  use. I dont think LVTTL and LVCMOS
would work at such high speeds, whereas HSTL kind of interfaces can
not drive that long a trace.

So is there any other IO standard that I can use for this?


Article: 133579
Subject: Serial Pheripheral Interface for XILINX FPGA
From: Zorjak <Zorjak@gmail.com>
Date: Fri, 4 Jul 2008 04:13:11 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,

I have one question if anyone can give me some clues. I need to
realize SPI (Serial Pheriferal Interface for my project). Does anybody
knows is there any free version of this core that can be foud on the
net. TO be honest, I tought that I will find this easy on the net but
it turns out that it was not.. I need that my interface be fully
programed.

Please if someone can give me any clue where can I find this. If you
don't know, some good literature would also help if I must to do it by
myself from the beginning.

Thank you very much
Zoran

Article: 133580
Subject: Re: Serial Pheripheral Interface for XILINX FPGA
From: Alfreeeeed <Alfredo.Taddei@gmail.com>
Date: Fri, 4 Jul 2008 04:24:52 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 4, 8:13=A0am, Zorjak <Zor...@gmail.com> wrote:
> Hi,
First thing that comes to my mind is.......start using Microblaze. You
can configure a SPI peripheral. Drawback is License of EDK of course
and You will have to review your C/C++ knowledge.

If not of your like the former option......check
Opencores.....www.opencores.org . I think I saw sthg there for a SPI
( I found an UART controller).

Cheers

Alfredo

>
> I have one question if anyone can give me some clues. I need to
> realize SPI (Serial Pheriferal Interface for my project). Does anybody
> knows is there any free version of this core that can be foud on the
> net. TO be honest, I tought that I will find this easy on the net but
> it turns out that it was not.. I need that my interface be fully
> programed.
>
> Please if someone can give me any clue where can I find this. If you
> don't know, some good literature would also help if I must to do it by
> myself from the beginning.
>
> Thank you very much
> Zoran


Article: 133581
Subject: Re: Serial Pheripheral Interface for XILINX FPGA
From: Zorjak <Zorjak@gmail.com>
Date: Fri, 4 Jul 2008 07:00:16 -0700 (PDT)
Links: << >>  << T >>  << A >>
Thank you for your fast help Alfred I surely visit opencores. The
thing is that I need VHDL solution of the SPI, so microblaze isn't
waht I am looking for.

Thank you again for your help.
Zoran


On Jul 4, 1:24=A0pm, Alfreeeeed <Alfredo.Tad...@gmail.com> wrote:
> On Jul 4, 8:13=A0am, Zorjak <Zor...@gmail.com> wrote:> Hi,
>
> First thing that comes to my mind is.......start using Microblaze. You
> can configure a SPI peripheral. Drawback is License of EDK of course
> and You will have to review your C/C++ knowledge.
>
> If not of your like the former option......check
> Opencores.....www.opencores.org. I think I saw sthg there for a SPI
> ( I found an UART controller).
>
> Cheers
>
> Alfredo
>
>
>
>
>
> > I have one question if anyone can give me some clues. I need to
> > realize SPI (Serial Pheriferal Interface for my project). Does anybody
> > knows is there any free version of this core that can be foud on the
> > net. TO be honest, I tought that I will find this easy on the net but
> > it turns out that it was not.. I need that my interface be fully
> > programed.
>
> > Please if someone can give me any clue where can I find this. If you
> > don't know, some good literature would also help if I must to do it by
> > myself from the beginning.
>
> > Thank you very much
> > Zoran


Article: 133582
Subject: Re: FiFo Help Needed
From: "MM" <mbmsv@yahoo.com>
Date: Fri, 4 Jul 2008 10:45:13 -0400
Links: << >>  << T >>  << A >>
> or rather... how can I simulate the FIFO?

If you can afford it upgrade your license. If you can't afford it try 
partial simulations or see if you can find a less resrtictive free 
simulator, or get an evaluation license, etc..


/Mikhail 



Article: 133583
Subject: Re: FiFo Help Needed
From: Mike Treseler <mtreseler@gmail.com>
Date: Fri, 04 Jul 2008 08:38:06 -0700
Links: << >>  << T >>  << A >>
Zhane wrote:

> # ** Warning: Design size of 11167 statements or 0 non-Xilinx leaf
> instances exceeds ModelSim XE-Starter recommended capacity.

Why does it take 11,167 statements to describe a fifo?
See http://mysite.verizon.net/miketreseler/sync_fifo.vhd

Article: 133584
Subject: Re: Serial Pheripheral Interface for XILINX FPGA
From: "Icky Thwacket" <it@it.it>
Date: Fri, 4 Jul 2008 16:45:14 +0100
Links: << >>  << T >>  << A >>

"Zorjak" <Zorjak@gmail.com> wrote in message 
news:2a3e6b51-ccf4-4b1c-83cb-3cd1935a5120@m44g2000hsc.googlegroups.com...
> Hi,
>
> I have one question if anyone can give me some clues. I need to
> realize SPI (Serial Pheriferal Interface for my project). Does anybody
> knows is there any free version of this core that can be foud on the
> net. TO be honest, I tought that I will find this easy on the net but
> it turns out that it was not.. I need that my interface be fully
> programed.
>
> Please if someone can give me any clue where can I find this. If you
> don't know, some good literature would also help if I must to do it by
> myself from the beginning.
>
> Thank you very much
> Zoran

Christ! It takes about an hour tops to put together an SPI interface. If you 
cannot even do that you should not even be playing with FPGA's!

Read the SPI interface spec for the peripheral(s) you want to interface and 
go design.

Icky 



Article: 133585
Subject: Re: Single ended interface at 70Mhz for FPGAs
From: nico@puntnl.niks (Nico Coesel)
Date: Fri, 04 Jul 2008 15:48:57 GMT
Links: << >>  << T >>  << A >>
Goli <togoli@gmail.com> wrote:

>hi,
>
>I am looking for connecting my proprietary 8 bit bus interface across
>two Xilinx FPGAs across the back plane, (10 inch trace). I dont want
>to use differential as that would take lot of pins, Is there any
>single ended interface that I can  use. I dont think LVTTL and LVCMOS
>would work at such high speeds, whereas HSTL kind of interfaces can
>not drive that long a trace.
>
>So is there any other IO standard that I can use for this?

I'd go for external LVDS transceivers. They are very very cheap, made
for this purpose and will save you a lot of headaches.

-- 
Programmeren in Almere?
E-mail naar nico@nctdevpuntnl (punt=.)

Article: 133586
Subject: Re: Processor Debug interface
From: jetmarc@hotmail.com
Date: Fri, 4 Jul 2008 09:34:27 -0700 (PDT)
Links: << >>  << T >>  << A >>
vits ha escrito:
> I wanted to know about the different debug interfaces used(or
> standards present like JTAG etc...) in a wireless SOC having a RISC
> processor. ARM uses some thing called trace debugging, I didn't get
> the concept clearly. Can anyone enlighten me on the same.

I once did something that could be called "trace debugging".
Basically I created a lot of debug signals in the design.  Those were
connected to a debug module.  In this module, I selected a subset of
them (the others were automatically removed by the toolchain).  The
module contained a FIFO memory wide enough to hold N samples of the
subset.  It also looked for a trigger.  When triggered, it started to
sample the signals into the FIFO.  Depending on the configuration it
either sampled on every clock, or when any of the sampled signals
changed.

Once the FIFO was full, I could read it from its other side.  I made a
little software to format it into something readable.

With this little helper I found various bugs that seemed to only
appear under very rare and difficult-to-simulate conditions.

Maybe the ARM thing is something similar.

Marc

Article: 133587
Subject: Re: Single ended interface at 70Mhz for FPGAs
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 4 Jul 2008 18:10:12 +0100
Links: << >>  << T >>  << A >>

"Goli" <togoli@gmail.com> wrote in message 
news:3d9aeb69-2537-48cd-9bf9-e30c57dff9c3@l28g2000prd.googlegroups.com...
> hi,
>
> I am looking for connecting my proprietary 8 bit bus interface across
> two Xilinx FPGAs across the back plane, (10 inch trace). I dont want
> to use differential as that would take lot of pins, Is there any
> single ended interface that I can  use. I dont think LVTTL and LVCMOS
> would work at such high speeds, whereas HSTL kind of interfaces can
> not drive that long a trace.
>
> So is there any other IO standard that I can use for this?
>
LVCMOS will be fine @ 70MHz. Your backplane should have a ground plane. Use 
appropriate terminations at the FPGAs. Look into the DCI stuff. Simulate it 
w/hyperlynx or similar.
http://www.xilinx.com/publications/xcellonline/xcell_50/xc_pdf/xc_spartan3-50.pdf
HTH., Syms. 



Article: 133588
Subject: HELP! How do I install Xilinx ISE WebPack?
From: Jason Hsu <jason_hsu@my-deja.com>
Date: Fri, 4 Jul 2008 10:17:04 -0700 (PDT)
Links: << >>  << T >>  << A >>
I'm using Damn Small Linux version 3.4.8.

I downloaded the file 10.1_Webinstall.zip to my hard drive.  When I
open this file, I get taken to /ramdisk/tmp/.emelfm-unpack .  I open a
shell and go to this directory and type "setup".  The installer
opens.  So far so good.

The problem: I CAN'T READ ANYTHING!  I know I'm supposed to get text,
but each letter is just a square.  How do I configure things so I get
actual text instead of meaningless gibberish?

Article: 133589
Subject: Re: Single ended interface at 70Mhz for FPGAs
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Sat, 05 Jul 2008 07:47:50 +1200
Links: << >>  << T >>  << A >>
Goli wrote:
> hi,
> 
> I am looking for connecting my proprietary 8 bit bus interface across
> two Xilinx FPGAs across the back plane, (10 inch trace). I dont want
> to use differential as that would take lot of pins, Is there any
> single ended interface that I can  use. I dont think LVTTL and LVCMOS
> would work at such high speeds, whereas HSTL kind of interfaces can
> not drive that long a trace.
> 
> So is there any other IO standard that I can use for this?

Does this have to pass any EMC tests ?
Will you need any headroom, or will the Bus NEVER
be faster than 70Mhz ?
There are also 4 bit busses : The intel LPC and QuadSPI
use fewer pins.

-jg


Article: 133590
Subject: Re: Single ended interface at 70Mhz for FPGAs
From: "MM" <mbmsv@yahoo.com>
Date: Fri, 4 Jul 2008 16:48:30 -0400
Links: << >>  << T >>  << A >>
Which FPGA(s) are you using? Even if you don't have MGT's available you 
could run your bus at twice or possibly even 4 times the speed while using 
LVDS. This way you could even save some pins. You could even employ DDR for 
more savings :)

/Mikhail

"Goli" <togoli@gmail.com> wrote in message 
news:3d9aeb69-2537-48cd-9bf9-e30c57dff9c3@l28g2000prd.googlegroups.com...
> hi,
>
> I am looking for connecting my proprietary 8 bit bus interface across
> two Xilinx FPGAs across the back plane, (10 inch trace). I dont want
> to use differential as that would take lot of pins, Is there any
> single ended interface that I can  use. I dont think LVTTL and LVCMOS
> would work at such high speeds, whereas HSTL kind of interfaces can
> not drive that long a trace.
>
> So is there any other IO standard that I can use for this?
> 



Article: 133591
Subject: Re: Xilinx XPS and Multiple Microblaze
From: Pablo H <pablo.huerta@gmail.com>
Date: Fri, 4 Jul 2008 16:40:16 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 3 jul, 18:40, Pablo <pbantu...@gmail.com> wrote:
> Hi,
>
> I know that it is possible to put multiple microblaze in a
> virtexIIPro. I am trying to design one architecture with two
> microblaze and two bram. When I try to generate Addresses, xps returns
> error because it couldn't work with multiple processors. So I decide
> to map address manually, but xps still returns errors and linker
> script doesn't recognize the second bram. If linker script doesn't
> recognize this bram, how could I download the executable.elf to this
> bram.
>
> Could someone inform me about the best way to build this design?
>
> Best Regards
>
> Pablo


Article: 133592
Subject: Re: Xilinx XPS and Multiple Microblaze
From: Pablo H <pablo.huerta@gmail.com>
Date: Fri, 4 Jul 2008 16:50:18 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi Pablo,

Can you tell me more about the architecture? How are the 2 brams
connected? One memory to each MicroBlaze or both processors have acces
to both memories?
If you can describe the architecture and the error linker script
returns it will be easier to help.

If you want, you can write me to pablo.huerta@gmail.com and we can
talk about it.

Regards,

Pablo H

On 3 jul, 18:40, Pablo <pbantu...@gmail.com> wrote:
> Hi,
>
> I know that it is possible to put multiple microblaze in a
> virtexIIPro. I am trying to design one architecture with two
> microblaze and two bram. When I try to generate Addresses, xps returns
> error because it couldn't work with multiple processors. So I decide
> to map address manually, but xps still returns errors and linker
> script doesn't recognize the second bram. If linker script doesn't
> recognize this bram, how could I download the executable.elf to this
> bram.
>
> Could someone inform me about the best way to build this design?
>
> Best Regards
>
> Pablo


Article: 133593
Subject: Re: HELP! How do I install Xilinx ISE WebPack?
From: root <root@nowhere.com>
Date: Fri, 04 Jul 2008 17:23:03 -0700
Links: << >>  << T >>  << A >>
Jason Hsu wrote:
> I'm using Damn Small Linux version 3.4.8.
> 
> I downloaded the file 10.1_Webinstall.zip to my hard drive.  When I
> open this file, I get taken to /ramdisk/tmp/.emelfm-unpack .  I open a
> shell and go to this directory and type "setup".  The installer
> opens.  So far so good.
> 
> The problem: I CAN'T READ ANYTHING!  I know I'm supposed to get text,
> but each letter is just a square.  How do I configure things so I get
> actual text instead of meaningless gibberish?

Have you tried this link?

http://www.xilinx.com/support/answers/30616.htm

Article: 133594
Subject: Xilinx 10.1 service-pack error: ./setup: line 41: 1472 Segmentation
From: root <root@nowhere.com>
Date: Fri, 04 Jul 2008 17:27:04 -0700
Links: << >>  << T >>  << A >>
On my Centos 5.2 (x86 32-bit) Linux box, I've noticed a problem with the 
10.1 service-packs.  If I unzip to a directory called "/tmp/x/", then 
try to run ./setup, the installer gives me this error-message.

[root@centos52 x]# ./setup
./setup: line 41:  1472 Segmentation fault 
$setuploc/bin/lin/xilinxupdate

But, If I use a longer temp directory name, like '/tmp/blahblahblah/', 
then it works FINE.  This happens with the ISE_IP update and the 
EDK_10_1_2 update...

is this one of those Linux/Centos quirks, or an install-package bug?

Article: 133595
Subject: Xilinx ISE speed files compatibility
From: "MM" <mbmsv@yahoo.com>
Date: Fri, 4 Jul 2008 20:50:10 -0400
Links: << >>  << T >>  << A >>
Does anyone know if I can copy a speed file from ISE10.1 to ISE8.2? They are 
of very much different size, which seems to say they are not compatible, but 
I thought I would ask anyways... I suspect that V4FX40 file in 8.2 is too 
optimistic... Can this be true?

Thanks,
/Mikhail 



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Subject: synthesis warning
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Hi,
during synthesis I get many warnings. One of them is :

WARNING:Xst:2404 -  FFs/Latches <rreg.addr<17:0>> (without init value) have 
a constant value of 0 in block <main>.

rreg.addr is connected to the input port of a subcell.
Is the error in main, or could it also be in the subcell ?

Here is some code (Because of copyright issues is cannot post all of it):

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;


entity main is
        port(
                clk,reset : in std_logic;
                --btn: in std_logic_vector(2 downto 0);
                --rx : in std_logic;
                --tx : out std_logic;
                --led: out std_logic_vector(7 downto 0);
                --sseg : out std_logic_vector(7 downto 0);
                --an : out std_logic_vector(3 downto 0);
                sw : in std_logic_vector(2 downto 0);
                
                -- to/from chip
                ad : out std_logic_vector(17 downto 0);
                we_n, oe_n : out std_logic;
                -- SRAM chip a
                dio_a : inout std_logic_vector(15 downto 0);
                ce_a_n,ub_a_n,lb_a_n : out std_logic;
                -- SRAM chip b
                dio_b : inout std_logic_vector(15 downto 0);
                ce_b_n,ub_b_n,lb_b_n : out std_logic;

                hsync,vsync : out std_logic;
                rgb : out std_logic_vector(2 downto 0)
        );
end main;

architecture Behavioral of main is
        signal pixel_tick : std_logic;
        signal wr_tick : std_logic;
        signal wr_addr : std_logic_vector(17 downto 0);
        signal wr_data : std_logic_vector(31 downto 0);
        signal wr_fifo_full : std_logic;
        signal video_on : std_logic;
        signal pixel_x,pixel_y : std_logic_vector(9 downto 0);
        
        type state_t is (s0,s1);
        type regs_t is record
                        state : state_t;
                        addr : std_logic_vector(17 downto 0);
                        n : unsigned(2 downto 0);
                end record;
        signal rreg,rnext : regs_t;
begin
        vga_pixel_unit : entity vga_pixel_gen port map(
                        clk=>clk,reset=>reset,pixel_tick=>pixel_tick,rgb=>rgb,wr_tick=>wr_tick,
                        wr_addr=>wr_addr,wr_data=>wr_data,wr_fifo_full=>wr_fifo_full,ad=>ad,
                        we_n=>we_n,
oe_n=>oe_n,dio_a=>dio_a,ce_a_n=>ce_a_n,ub_a_n=>ub_a_n,lb_a_n=>lb_a_n,
                        dio_b=>dio_b,ce_b_n=>ce_b_n,ub_b_n=>ub_b_n,lb_b_n=>lb_b_n,
                        video_on=>video_on
                );

        vga_sync_unit : entity vga_sync port map(
                        clk=>clk,reset=>reset,hsync=>hsync,vsync=>vsync,video_on=>video_on,
p_tick=>pixel_tick,
                        pixel_x=>pixel_x,pixel_y=>pixel_y
                );
                
        process(clk,reset)
        begin
                if reset='1' then
                        rreg.addr <= (others=>'0');
                        rreg.state <= s0;
                elsif rising_edge(clk) then
                        rreg <= rnext;
                end if;
        end process;
        
        process(rreg,wr_fifo_full,sw)
        begin
                rnext <= rreg;
                wr_addr <= (others=>'0');
                wr_data <= (others=>'0');
                wr_tick <= '0';
                
                case rreg.state is
                        when s0 =>
                                if wr_fifo_full='0' then
                                        wr_addr <= rreg.addr;
                                        wr_data <= sw&'0'&sw&'0'&sw&'0'&sw&'0'&sw&'0'&sw&'0'&sw&'0'&sw&'0';
                                        wr_tick <= '1';
                                        rnext.addr <= std_logic_vector(unsigned(rreg.addr) +
to_unsigned(18,1));
                                        if unsigned(rnext.addr) = 10 then
                                                rnext.addr <= (others =>'0');
                                        end if;
                                        rnext.n <= (others=>'1');
                                        rnext.state <= s1;
                                end if;
                        when s1 =>
                                if rreg.n = 0 then
                                        rnext.state <= s0;
                                else
                                        rnext.n <= rreg.n - 1;
                                end if;
                end case;
        end process;
end Behavioral;


Best REgards
Thorsten


From webmaster@home.org Fri Jul 04 19:27:11 2008
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Message-Id: <486edbf9$0$25949$6e1ede2f@read.cnntp.org>
From: Thorsten Kiefer <webmaster@home.org>
Subject: Re: synthesis warning
Newsgroups: comp.arch.fpga
Date: Sat, 05 Jul 2008 04:27:11 +0200
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Here is more code, if it helps.....


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity vga_pixel_gen is
        port(
                clk,reset : in std_logic;
                pixel_tick : in std_logic;
                video_on : in std_logic;
                
                rgb : out std_logic_vector(2 downto 0);
                wr_tick : in std_logic;
                wr_addr : in std_logic_vector(17 downto 0);
                wr_data : in std_logic_vector(31 downto 0);
                wr_fifo_full : out std_logic;
                -- to/from chip
                ad : out std_logic_vector(17 downto 0);
                we_n, oe_n : out std_logic;
                -- SRAM chip a
                dio_a : inout std_logic_vector(15 downto 0);
                ce_a_n,ub_a_n,lb_a_n : out std_logic;
                -- SRAM chip b
                dio_b : inout std_logic_vector(15 downto 0);
                ce_b_n,ub_b_n,lb_b_n : out std_logic

        );
end vga_pixel_gen;

architecture Behavioral of vga_pixel_gen is
        signal mem,mem_rw,mem_ready : std_logic;
        signal mem_addr : std_logic_vector(17 downto 0);
        signal mem_data_f2s,mem_data_s2f : std_logic_vector(31 downto 0);
        signal s2f_rd,s2f_wr,s2f_full,s2f_empty : std_logic;
        signal s2f_wdata,s2f_rdata : std_logic_vector(31 downto 0);
        signal f2sd_rd,f2sd_empty : std_logic;
        signal f2sd_rdata : std_logic_vector(31 downto 0);
        signal f2sa_rd,f2sa_empty,f2sa_full : std_logic;
        signal f2sa_rdata : std_logic_vector(17 downto 0);
        
        type state_t is (s10,s20,s30,s40);
        type regs_t is record
                        state : state_t;
                        addr : std_logic_vector(17 downto 0);
                end record;
        signal rreg,rnext : regs_t;

        type state2_t is (s210,s220,s230,s240,s250,s260,s270,s280,s290);
        type regs2_t is record
                        state : state2_t;
                        data : std_logic_vector(31 downto 0);
                        rgb : std_logic_vector(2 downto 0);
                end record;
        signal r2reg,r2next : regs2_t;
begin
        s2f_fifo : entity fifo
                generic map(B => 32,W => 2)
                port map(
                        clk=>clk,reset=>reset,rd=>s2f_rd,wr=>s2f_wr,w_data=>s2f_wdata,
                        full=>s2f_full,empty=>s2f_empty,r_data=>s2f_rdata
                );
        f2s_data_fifo : entity fifo
                generic map(B => 32,W => 2)
                port map(
                        clk=>clk,reset=>reset,rd=>f2sd_rd,wr=>wr_tick,w_data=>wr_data,
                        full=>wr_fifo_full,empty=>f2sd_empty,r_data=>f2sd_rdata
                );
        f2s_addr_fifo : entity fifo
                generic map(B => 18,W => 2)
                port map(
                        clk=>clk,reset=>reset,rd=>f2sa_rd,wr=>wr_tick,w_data=>wr_addr,
                        full=>f2sa_full,empty=>f2sa_empty,r_data=>f2sa_rdata
                );
        sram_unit : entity sram_ctrl
                port
map(clk=>clk,reset=>reset,ad=>ad,we_n=>we_n,oe_n=>oe_n,dio_a=>dio_a,ce_a_n=>ce_a_n,
                
ub_a_n=>ub_a_n,lb_a_n=>lb_a_n,dio_b=>dio_b,ce_b_n=>ce_b_n,ub_b_n=>ub_b_n,lb_b_n=>lb_b_n,
                
mem=>mem,rw=>mem_rw,addr=>mem_addr,data_f2s=>mem_data_f2s,data_s2f=>mem_data_s2f,ready=>mem_ready);

        process(clk,reset)
        begin
                if reset = '1' then
                        rreg.state <= s10;
                        rreg.addr <= (others=>'0');
                        r2reg.state <= s210;
                elsif rising_edge(clk) then
                        rreg <= rnext;
                        r2reg <= r2next;
                end if;
        end process;
        

process(rreg,f2sa_rdata,f2sd_rdata,s2f_full,f2sd_empty,mem_ready,mem_data_s2f)
        begin
                rnext <= rreg;
                mem <= '0';
                mem_rw <= '0';
                mem_addr <= (others=>'0');
                mem_data_f2s <= (others=>'0');
                f2sd_rd <= '0';
                f2sa_rd <= '0';
                s2f_wdata <= (others=>'0');
                s2f_wr <= '0';
                
                case rreg.state is
                        when s10 =>
                                if s2f_full='0' then
                                        if mem_ready='1' then
                                                mem_addr <= rreg.addr;
                                                mem_rw <= '1';
                                                mem <= '1';
                                                rnext.state <= s20;
                                        else
                                                rnext.state <= s10;
                                        end if;
                                else
                                        rnext.state <= s30;
                                end if;
                        when s20 =>
                                if mem_ready='1' then
                                        --s2f_wdata <= "10001000100010001000100010001000";
                                        s2f_wdata <= mem_data_s2f;
                                        s2f_wr <= '1';
                                        rnext.addr <= std_logic_vector(unsigned(rreg.addr) +
to_unsigned(18,1));
                                        if unsigned(rnext.addr) = 38400 then
                                                rnext.addr <= (others =>'0');
                                        end if;
                                        rnext.state <= s30;
                                end if;
                        when s30 =>
                                rnext.state <= s10;
                                if f2sd_empty='0' then
                                        f2sd_rd <= '1';
                                        f2sa_rd <= '1';
                                        rnext.state <= s40;
                                end if;
                        when s40 =>
                                if mem_ready='1' then
                                        mem_addr <= f2sa_rdata;
                                        mem_data_f2s <= f2sd_rdata;
                                        mem_rw <= '0';
                                        mem <= '1';
                                        rnext.state <= s10;
                                end if;
                end case;
        end process;
        
        process(r2reg,pixel_tick,video_on,s2f_rdata)
        begin
                r2next <= r2reg;
                s2f_rd<='0';

                case r2reg.state is
                        when s210 =>
                                s2f_rd<='1';
                                r2next.state <= s220;
                        when s220 =>
                                if pixel_tick='1' and video_on='1' then
                                        r2next.data <= s2f_rdata;
                                        r2next.rgb <= r2next.data(31 downto 29);
                                        r2next.state <= s230;
                                end if;
                        when s230 =>
                                if pixel_tick='1' and video_on='1' then
                                        r2next.rgb <= r2reg.data(27 downto 25);
                                        r2next.state <= s240;
                                end if;
                        when s240 =>
                                if pixel_tick='1' and video_on='1' then
                                        r2next.rgb <= r2reg.data(23 downto 21);
                                        r2next.state <= s250;
                                end if;
                        when s250 =>
                                if pixel_tick='1' and video_on='1' then
                                        r2next.rgb <= r2reg.data(19 downto 17);
                                        r2next.state <= s260;
                                end if;
                        when s260 =>
                                if pixel_tick='1' and video_on='1' then
                                        r2next.rgb <= r2reg.data(15 downto 13);
                                        r2next.state <= s270;
                                end if;
                        when s270 =>
                                if pixel_tick='1' and video_on='1' then
                                        r2next.rgb <= r2reg.data(11 downto 9);
                                        r2next.state <= s280;
                                end if;
                        when s280 =>
                                if pixel_tick='1' and video_on='1' then
                                        r2next.rgb <= r2reg.data(7 downto 5);
                                        r2next.state <= s290;
                                end if;
                        when s290 =>
                                if pixel_tick='1' and video_on='1' then
                                        r2next.rgb <= r2reg.data(3 downto 1);
                                        r2next.state <= s210;
                                end if;
                end case;
        end process;
        
        rgb <= r2reg.rgb when video_on='1' else "000";
end Behavioral;



From webmaster@home.org Sat Jul 05 00:24:32 2008
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Message-Id: <486f21a9$0$25952$6e1ede2f@read.cnntp.org>
From: Thorsten Kiefer <webmaster@home.org>
Subject: Re: synthesis warning
Newsgroups: comp.arch.fpga
Date: Sat, 05 Jul 2008 09:24:32 +0200
References: <486ed8e3$0$25950$6e1ede2f@read.cnntp.org>
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Hi,
I solved be removing the type conversions...

REgards
Thorsten


Article: 133596
Subject: Re: FiFo Help Needed
From: Zhane <me75@hotmail.com>
Date: Sat, 5 Jul 2008 00:43:14 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 4, 11:38=A0pm, Mike Treseler <mtrese...@gmail.com> wrote:
> Zhane wrote:
> > # ** Warning: Design size of 11167 statements or 0 non-Xilinx leaf
> > instances exceeds ModelSim XE-Starter recommended capacity.
>
> Why does it take 11,167 statements to describe a fifo?
> Seehttp://mysite.verizon.net/miketreseler/sync_fifo.vhd

no idea
I used the Core generator to generate
and used the structural one to simulate
and end up getting that error

Article: 133597
Subject: ISE Simulator
From: meralonurlu@gmail.com
Date: Sat, 5 Jul 2008 02:36:49 -0700 (PDT)
Links: << >>  << T >>  << A >>
Xilinx ISE 9.2 and 10.1  (Webpack)

signal cntr: integer range 0 to 3;
...
if(clk'event and clk='1') then cntr<=cntr+1; end if;
inferres 2 FFs as I see from the RL schematics.
But when I try to simulate, the simulator does not recognize any upper
limit. That is, it counts limitlessly.
I am a beginner. What is the problem?
Thanks.

Article: 133598
Subject: basic chipscope pro query
From: irfan.mohammed@gmail.com
Date: Sat, 5 Jul 2008 02:40:09 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hello,

I am new to chipscope pro.i read lot of documents but unable to get
exact information.i worked with counter example which works fine

now i implement a design of ram using VHDL,where i first write some
data on specific address and then read from that location.i have
synthesized and then i created cdc format file.

here is my entity declaration

entity ram1 is
port(
clk:in std_logic;
wr_addr:in std_logic_vector(2 downto 0);
rd_addr:in std_logic_vector(2 downto0);
we:in std_logic;
oe:in std_logic;
din:in std_logic_vector(7 downto 0);
dout:out std_logic_vector(7 downto 0));

end ram1


i can give inputs in xilinx simulator and perform functional
verification.now my question is by using chipscope inserter and
analyzer how can i verify my design especially where can i give my
inputs such as wr_addr,rd_addr,we,oe,din.

any suggessions will be greatly appreciated.

please help its very urgent

Thanks in Advance
Irfan




Article: 133599
Subject: QPSK SymbolRate generator ...
From: "Kappa" <78kappa78(at)virgilio(dot)it>
Date: Sat, 5 Jul 2008 13:43:34 +0200
Links: << >>  << T >>  << A >>
I have built a QPSK modulator, but I have some doubts about the generation 
of SymbolRate variable.

The SymbolRate range should from 1 to 45 Msymb/s. I intend to use an 
external AD9850 DDS, which generates the clock from 1 MHz to 45 MHz for 
clockout the Symbol.

The Symbols (I and Q) is interpolated by x2 or x4.

How can multiply internally this clock (1 to 45 MHz) by x2 or x4 ? I 
remember that the clock is variable.

It's possible ?

Thansk.

Kappa





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