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On May 27, 1:42 am, marts...@gmail.com wrote: > On May 27, 12:25 am, Thomas Stanka <usenet_nospam_va...@stanka-web.de> > wrote: > > > > > On 27 Mai, 05:18, marts...@gmail.com wrote: > > > > signal x: std_logic; > > > > you don't assign any value to "x" > > [..] > > > how does the x power up? high/low?? is that part/technology dependent? > > > > the reason I am asking this is because, I have a part that used to > > > work all the time but now I got a different part (same mfg), > > > programmed with the same programming file and it seems like x is > > > powering up differently. > > > Try a Reset on Power up. > > For most FPGAs there is a global value for Powerup content that is > > valid before you use a reset. > > First of all, inspect the synthesis result. Only latches and FF are > > set during power up. All other signals depend on the contentg of > > Inputs, FF and latches. > > > bye Thomas > > Thomas, > > Thanks for your input. But what I was trying to figure out is > that...If I am not using the reset, or not assign any values to > signal, what happens in that case? I do know how to fix it but I was > just curious to find out, why was this working for sometime but now > doesn't work with a different part (same mfg)? > Thanks, > Martin You *have* to assign a value to X or it won't simulate (properly) and it can't be constructed. X will always have a value 'U' and therefor so will Y. What is driving X? That determines the value of X at power up. RickArticle: 132426
"bish" <bisheshkh@gmail.com> wrote in message news:5df586c0-0126-48cc-9ff1-ee382f505221@u6g2000prc.googlegroups.com... > We have just bought a new Spartan 3a 1800a dsp board of Xilinx. We > needed i/o pins to control motors and use various sensors and camera. > The board contains EXP expansion slots, ( somewhere I found it is > called QTE connector?). > > We are confused as how to easily connect our sensors like optical > encoder, camera and output for our motor drivers using these EXP > slots? > Somewhere we found that we need to use QSE connector but we are not > clear about it. We need a low cost solution !!!!! Can we find the > connectors to match with EXP slot at one end and have simple wires at > the other end?? The S3ADSP starter kit board comes with Samtec QTE connectors. The corresponding connectors are series their QSE. The user guide documents the specific type. Samtec was nice enough to send a couple of the required connectors as samples. These are SMT components; you'll have to build a board to bring out the required signals. They also sell QSE terminated cables, although I doubt these are cheap. They are shielded differential pairs. You might look at daughterboards sold for the S3ADSP3400 kits. I don't have experience with the 3400 board. Its accessories might or might not fit the QTE connectors on the 1800 board.Article: 132427
On May 27, 8:18 am, marts...@gmail.com wrote: > Here is my question/issue: > > say you have: > > y : out std_logic; > signal x: std_logic; > > you don't assign any value to "x" but you have a condition in your > code.. > > i.e > > if (x= '1') then > y <= '1'; > else > y <= '0'; > end if; Power up period can be divided in to two parts, 1. Power up and before configuration starts -> This is dependent from FPGA to FPGA, most FPGAs tristate all the pins, hence the value will depend on how it is connected externally on board. Sometimes this also can depend on what voltage sequence that you are following to power up the FPGA. 2. During configuration -> Xilinx FPGA has a pin (I think HWSWAP) which determines at powerup how the pin should behave either pulled up or pulled low. Hope this helps. -- Goli > > how does the x power up? high/low?? is that part/technology dependent? > > the reason I am asking this is because, I have a part that used to > work all the time but now I got a different part (same mfg), > programmed with the same programming file and it seems like x is > powering up differently. > > Thanks, > MartinArticle: 132428
On 27 Mai, 05:18, marts...@gmail.com wrote: > if (x= '1') then > y <= '1'; > else > y <= '0'; > end if; First, this will be optimized by synthesis to y <= x; Then it will be noticed that x is not driven and a don't care will be assigned to y. y <= '-': Logic driven by y will be at least partially removed. If y is an output the synthesis tool is likely to have some convention what value is assigned. I would choose 'z'. Kolja SulimmaArticle: 132429
Hi , i tried yesterday to configure my fpga with an encrypted bitstream . Using Impact 10.1 i didn't unerstand the way to do it , i mean how can i enter the key & bit files ? i couldn't find the option . what i did is to load the key file first inside fpga then the bit file , i v had the warning : Impact can not find the instruction ISC_Prog ... thank you .Article: 132430
On May 26, 11:09 pm, sijo2...@googlemail.com wrote: > On May 26, 4:57 pm, Florian <Flo...@yahoo.com> wrote: > > > Hi > > > I have a very basic question. Xilinx permits me to initialize Block RAM > > with an external data file. The thing I am just wondering is, how do I > > download this file on the FPGA? Do I need to have a UART to download > > this file? Because I cant find an option with CHipscope, there I can > > just configure the FPGA with a new bit stream. > > > Cheers for helpful comments, > > Floh > > I'm not aware of any tools that would let you change the contents of > RAM in a configured FPGA without requiring you to design your own > interface and logic to write received data into the Block RAM. I've > often thought this would be a useful feature (It would be especially > nice to be able to dump the contents of a block RAM with Chipscope). > > What is possible is to change the data in the configuration bit stream > so that when you configure the FPGA the RAM is initialised with the > data you require, without having to iterate through synthesis and PAR. > It's been a while since I did anything like this but I seem to > remember there is a tool included in the Picoblaze package from Xilinx > called Data2Mem that did exactly this to include the code for the > processor in the bit stream. Take a look at the flow this tool > required and you should be able to adapt it to your needs. > > Simon Hi, I think that Chipscope allows text file to be applied at input of certian module through VIO core. A slightest of logic across VIO can allow initalization of BRAMs at run time. I never tried this, just an idea /MHArticle: 132431
On 27 mai, 09:28, dajjou <swissiyous...@hotmail.fr> wrote: > Hi , > > i tried yesterday to configure my fpga with an encrypted bitstream . > Using Impact 10.1 i didn't unerstand the way to do it , i mean how > can i enter the key & bit files ? i couldn't find the option . > what i did is to load the key file first inside fpga then the bit > file , i v had the warning : Impact can not find the instruction > ISC_Prog ... > > thank you . Im using : - Xilinx Platform cable USB II - OS : Linux - HW : Virtex 5 LX 30 - ISE 10.1Article: 132432
On May 26, 7:39=A0pm, morphiend <morphi...@gmail.com> wrote: > > Well, you did part of the resolution: run Xplorer script on it. > > After you've run the script, it should provide you with the > combination of settings it used to build your image. Record those and > use them for future iterations. Now you won't need to run the script, > and you're build-time should be much less. Thanks :) Where can I edit the hardware flow setting? Where are the script files? Some of the files seem to contain the options, but are rewritten for every run. So the changes I make are not persistent. EDK doesnt seem to have a GUI for editing the map and par switches, like ISE. I think I should use a custom script for the hardware flow. If I can modify the script used for default flow then it will be better. Raghu.Article: 132433
On May 26, 7:37=A0pm, Zorjak <Zor...@gmail.com> wrote: > Hi, > > Can someone help me please. I am trying familiarize myself with xilinx > ISE an d core generator. I was trying to realize simple "fifo core" > using core generator. I have done all the procedure and the core have > been created. So I instance created component in my design and it > looks like this > > --------------------------------------------------------------------------= -=AD------- > -- Company: > -- Engineer: > -- > -- Create Date: =A0 =A015:08:49 05/22/2008 > -- Design Name: > -- Module Name: =A0 =A0fifotest - Behavioral > -- Project Name: > -- Target Devices: > -- Tool versions: > -- Description: > -- > -- Dependencies: > -- > -- Revision: > -- Revision 0.01 - File Created > -- Additional Comments: > -- > --------------------------------------------------------------------------= -=AD------- > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > --Library XilinxCoreLib; > -- synthesis translate_on > library work; > > ---- Uncomment the following library declaration if instantiating > ---- any Xilinx primitives in this code. > --library UNISIM; > --use UNISIM.VComponents.all; > > entity fifotest is > port ( > =A0 =A0 =A0 =A0 clk: IN std_logic; > =A0 =A0 =A0 =A0 din: IN std_logic_VECTOR(17 downto 0); > =A0 =A0 =A0 =A0 rd_en: IN std_logic; > =A0 =A0 =A0 =A0 rst: IN std_logic; > =A0 =A0 =A0 =A0 wr_en: IN std_logic; > =A0 =A0 =A0 =A0 dout: OUT std_logic_VECTOR(17 downto 0); > =A0 =A0 =A0 =A0 empty: OUT std_logic; > =A0 =A0 =A0 =A0 full: OUT std_logic); > end fifotest; > > architecture Behavioral of fifotest is > > component fifo_v4_3 > =A0 =A0 =A0 =A0 port ( > =A0 =A0 =A0 =A0 clk: IN std_logic; > =A0 =A0 =A0 =A0 din: IN std_logic_VECTOR(17 downto 0); > =A0 =A0 =A0 =A0 rd_en: IN std_logic; > =A0 =A0 =A0 =A0 rst: IN std_logic; > =A0 =A0 =A0 =A0 wr_en: IN std_logic; > =A0 =A0 =A0 =A0 dout: OUT std_logic_VECTOR(17 downto 0); > =A0 =A0 =A0 =A0 empty: OUT std_logic; > =A0 =A0 =A0 =A0 full: OUT std_logic); > end component; > > begin > > ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG > your_instance_name : fifo_v4_3 > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 port map ( > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 clk =3D> clk, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 din =3D> din, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 rd_en =3D> rd_en, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 rst =3D> rst, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 wr_en =3D> wr_en, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 dout =3D> dout, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 empty =3D> empty, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 full =3D> full); > > ------------INSTANTIATION Template ------------ > > end Behavioral; > > but when I wanted to implement my module I have got this error > > ERROR:NgdBuild:604 - logical block 'your_instance_name' with type > 'fifo_v4_3' > > I was reading on the xilinx help but there is written that I should do > this > > This error occurs when a netlist is not found. > > In EDK user-defined PCOREs, if the VHDL for the PCORE is using both > HDL and NGC or EDIF netlists, the STYLE attribute for the MPD file for > that core must be set correctly. When using both HDL and NGC or EDIF > netlists, ensure that the STYLE =3D MIX is set in the peripheral MPD > file. > > The MPD file can be found in the following directory: > > <project_directory>\pcore\<core_name>\data > > But I can' find this MPD file in my core directory. Actually, > directory where my core is realized consist only directory temp. I am > totally confused. > > Has anyone had similar type of problem. I repeat that from the core > generator I don't receive any kind of message that there are some > errors in my designed core. > > Any kind of help is welcome > Thanks to everyone > Zoran Coregen creates a .ngc file too.Have you copied the .ngc file also from your coregen directory to your ISE project? ISE needs the ngc file for the implementation. Raghu.Article: 132434
Good morning. I am currently seeking any publication of my work with FPGA devices, especially for obtaining Ph.D Student. Specifically I've introduced a middleware of communications for FPGA multicomputers. I would appreciate if someone indicate me any magazines, congress or any action that might assert. Best RegardsArticle: 132435
On 27 Maj, 01:09, "Symon" <symon_bre...@hotmail.com> wrote: > "kislo" <kisl...@student.sdu.dk> wrote in message > > news:046b8420-5e4a-4ee8-8ca2-1903b2253991@34g2000hsf.googlegroups.com... > > > The IO drive level constrain specifies the drive level of a output > > signal .. if i am using LVCMOS33 with a drive level of 8mA how can i > > determine the the output impedance if using f.x a 50ohm characteristic > > impedance of my trace? > > From the IBIS files. Use them with your SI simulator. > HTH., Syms. i dont have any SI simulator available :) so how to extract the impedance from the IBIS model ? there is alot of voltage and current values, but what values should i use ?Article: 132436
Hai, Is there any formula or general rule to set output width of FIR filter given its input ,coefficients width and number of taps.?? I red in some data sheet of FIR filter deisgn as: output width = input width+coefficient width+logN(base 2) In some other data sheet of FIR filter deisgn as: output width = 2*input width+logN(base 2) which of the above is correct??pls give some link for refernce doc explaining the general rule to set o/p width.. regards, fazArticle: 132437
On Tue, 27 May 2008 04:44:11 -0700 (PDT), fazulu deen <fazulu.vlsi@gmail.com> wrote: >Is there any formula or general rule to set output width of FIR >filter >given its input ,coefficients width and number of taps.?? Go do the sums... >I red in some data sheet of FIR filter deisgn as: >output width = input width+coefficient width+logN(base 2) That looks right. Each product (input*coeff) gives a width of (input bits) + (coeff bits). Assuming all your coefficients have that same width, your maximum output value cannot exceed N*(max_input*max_coeff), so giving a bit growth of ceiling(log2(N)) over the output width of each multiplier. Early stages in the pipeline obviously can use narrower words. In the systolic form (input fed to all multipliers simultaneously) and assuming coefficient widths are the same for all taps, the sum's bit growth at each tap is: tap# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17... bits 0 1 2 2 3 3 3 3 4 4 4 4 4 4 4 4 5... >In some other data sheet of FIR filter deisgn as: >output width = 2*input width+logN(base 2) Looks like someone's assuming the coefficients and input are the same width, doesn't it? >pls give some link for refernce doc >explaining the general rule to set o/p width.. FIR filters are really rather easy to reason about. At each step you can easily pre-calculate the largest possible numeric value that can be seen. You may be able to use knowledge of the input stream to set even tighter bounds on bit width, but the benefit is rarely worth the hassle. IIR filters, of course, are much harder. Try comp.dsp where there is some very heavy-duty filter expertise. (There's plenty of filter expertise here too, mind you!) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 132438
hi all, I am trying to use HWICAP to configure certain LUTs , I guess that starting with the examples from XILINX will be a good start, the problem that after many trials and of course nothing working, I noticed that the DONE bit which in the status reg in the HWICAP is low all the time so nothing is working, but before calling the function XHwIcap_Initialize the Done bit is high , I don't know if what I noticed is really a problem as I guess or not, I am using EDK 9.1 and XUP board for XC2VP30 under Linux, I don't may be the problem in Linux or some thing else. thanks fatmaArticle: 132439
"kislo" <kislo02@student.sdu.dk> wrote in message news:4bd6ea99-ffd4-45be-8208-7c52b2433bd2@y21g2000hsf.googlegroups.com... > On 27 Maj, 01:09, "Symon" <symon_bre...@hotmail.com> wrote: >> "kislo" <kisl...@student.sdu.dk> wrote in message >> >> news:046b8420-5e4a-4ee8-8ca2-1903b2253991@34g2000hsf.googlegroups.com... >> >> > The IO drive level constrain specifies the drive level of a output >> > signal .. if i am using LVCMOS33 with a drive level of 8mA how can i >> > determine the the output impedance if using f.x a 50ohm characteristic >> > impedance of my trace? >> >> From the IBIS files. Use them with your SI simulator. >> HTH., Syms. > > i dont have any SI simulator available :) so how to extract the > impedance from the IBIS model ? there is alot of voltage and current > values, but what values should i use ? STW. http://groups.google.com/groups/search?q=impedance+ibis+group%3Acomp.arch.fpga&qt_s=Search HTH., Syms.Article: 132440
On May 27, 6:09 am, raghunanda...@gmail.com wrote: > On May 26, 7:39 pm, morphiend <morphi...@gmail.com> wrote: > > > > > Well, you did part of the resolution: run Xplorer script on it. > > > After you've run the script, it should provide you with the > > combination of settings it used to build your image. Record those and > > use them for future iterations. Now you won't need to run the script, > > and you're build-time should be much less. > > Thanks :) Where can I edit the hardware flow setting? Where are the > script files? Some of the files seem to contain the options, but are > rewritten for every run. So the changes I make are not persistent. EDK > doesnt seem to have a GUI for editing the map and par switches, like > ISE. I think I should use a custom script for the hardware flow. If I > can modify the script used for default flow then it will be better. > > Raghu. EDK stores it's settings for the flow (or atleast used to in the 9.x, I haven't tried 10.x yet) in the /etc directory. For me it's a file called "fast_runtime.opt". In that file are all the command line switches, separated by a new line, for each tool that is run in the EDK flow. I don't use the EDK gui much, so I don't know if its specifically possible or not to configure it from there. On the flipside, ISE does support native EDK project building. You just create a new ISE project and import the EDK xmp file as a source file. That way you would have the entire ISE flow if you so wished. -- MikeArticle: 132441
On May 27, 4:08 am, dajjou <swissiyous...@hotmail.fr> wrote: > On 27 mai, 09:28, dajjou <swissiyous...@hotmail.fr> wrote: > > > Hi , > > > i tried yesterday to configure my fpga with an encrypted bitstream . > > Using Impact 10.1 i didn't unerstand the way to do it , i mean how > > can i enter the key & bit files ? i couldn't find the option . > > what i did is to load the key file first inside fpga then the bit > > file , i v had the warning : Impact can not find the instruction > > ISC_Prog ... > > > thank you . > > Im using : > - Xilinx Platform cable USB II > - OS : Linux > - HW : Virtex 5 LX 30 > - ISE 10.1 This was a problem in ISE 9.2.x. It was in the answer records on how to fix it. Here's the link: http://www.xilinx.com/support/answers/30115.htm. It stated that it was supposed to be fixed in 10.1. I ran into the same problem under 9.2.4. I followed the instructions and manually updated my BSDL files and then my part programmed "fine".Article: 132442
On May 27, 12:14 pm, raghunanda...@gmail.com wrote: > On May 26, 7:37 pm, Zorjak <Zor...@gmail.com> wrote: > > > > > Hi, > > > Can someone help me please. I am trying familiarize myself with xilinx > > ISE an d core generator. I was trying to realize simple "fifo core" > > using core generator. I have done all the procedure and the core have > > been created. So I instance created component in my design and it > > looks like this > > > ------------------------------------------------------------------------= ---=AD------- > > -- Company: > > -- Engineer: > > -- > > -- Create Date: 15:08:49 05/22/2008 > > -- Design Name: > > -- Module Name: fifotest - Behavioral > > -- Project Name: > > -- Target Devices: > > -- Tool versions: > > -- Description: > > -- > > -- Dependencies: > > -- > > -- Revision: > > -- Revision 0.01 - File Created > > -- Additional Comments: > > -- > > ------------------------------------------------------------------------= ---=AD------- > > library IEEE; > > use IEEE.STD_LOGIC_1164.ALL; > > use IEEE.STD_LOGIC_ARITH.ALL; > > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > --Library XilinxCoreLib; > > -- synthesis translate_on > > library work; > > > ---- Uncomment the following library declaration if instantiating > > ---- any Xilinx primitives in this code. > > --library UNISIM; > > --use UNISIM.VComponents.all; > > > entity fifotest is > > port ( > > clk: IN std_logic; > > din: IN std_logic_VECTOR(17 downto 0); > > rd_en: IN std_logic; > > rst: IN std_logic; > > wr_en: IN std_logic; > > dout: OUT std_logic_VECTOR(17 downto 0); > > empty: OUT std_logic; > > full: OUT std_logic); > > end fifotest; > > > architecture Behavioral of fifotest is > > > component fifo_v4_3 > > port ( > > clk: IN std_logic; > > din: IN std_logic_VECTOR(17 downto 0); > > rd_en: IN std_logic; > > rst: IN std_logic; > > wr_en: IN std_logic; > > dout: OUT std_logic_VECTOR(17 downto 0); > > empty: OUT std_logic; > > full: OUT std_logic); > > end component; > > > begin > > > ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG > > your_instance_name : fifo_v4_3 > > port map ( > > clk =3D> clk, > > din =3D> din, > > rd_en =3D> rd_en, > > rst =3D> rst, > > wr_en =3D> wr_en, > > dout =3D> dout, > > empty =3D> empty, > > full =3D> full); > > > ------------INSTANTIATION Template ------------ > > > end Behavioral; > > > but when I wanted to implement my module I have got this error > > > ERROR:NgdBuild:604 - logical block 'your_instance_name' with type > > 'fifo_v4_3' > > > I was reading on the xilinx help but there is written that I should do > > this > > > This error occurs when a netlist is not found. > > > In EDK user-defined PCOREs, if the VHDL for the PCORE is using both > > HDL and NGC or EDIF netlists, the STYLE attribute for the MPD file for > > that core must be set correctly. When using both HDL and NGC or EDIF > > netlists, ensure that the STYLE =3D MIX is set in the peripheral MPD > > file. > > > The MPD file can be found in the following directory: > > > <project_directory>\pcore\<core_name>\data > > > But I can' find this MPD file in my core directory. Actually, > > directory where my core is realized consist only directory temp. I am > > totally confused. > > > Has anyone had similar type of problem. I repeat that from the core > > generator I don't receive any kind of message that there are some > > errors in my designed core. > > > Any kind of help is welcome > > Thanks to everyone > > Zoran > > Coregen creates a .ngc file too.Have you copied the .ngc file also > from your coregen directory to your ISE project? ISE needs the ngc > file for the implementation. > > Raghu. HI Raghu Thanks for your try to help. My core folder is located in the my ise project directory. All I I included my vhd core file in to my ise project. After you told me this I have copied all files from core directory to my ise directory and i tried to start compilation again. My result is the same. I am getting the same error. I don't know what to do. ZoranArticle: 132443
Narendra Sisodiya wrote: > This is my final project , I want to work hard , rather then making > some work around to problem, I do not have proper guidance, hope i > will get here,. Choose a simpler project or drop the class. -- Mike TreselerArticle: 132444
On 30 Apr, 09:00, Antony <ascgr...@gmail.com> wrote: > Hi all, > I'm glad to see that the XUPV2P board is now supported by EDK 10.1. > However, setting the MPCM memory controller to work seems complex and > up to now I hadn't success (256 MB DDR DIMM memory module correctly > working before with the standard PLB and OPB controllers). I set up > parameters like the previous controllers and the clocking has been > realized following Xilinx guide, but I cannot make it work... Any one > had success with that? Hello, made it work ;) now it is ok, just a little tuning of the parameters. Bye!Article: 132445
Hi Gabriel,
Thank you for your reply. Yeah, all my logiclock region were set to
autosize and floating. I have changed the setting as you suggested and
the message was gone.
Now, I set the logic regions to preserve both "placement and routing".
And my compilation time reduced to about 1 hour and 7 munites,
comparing to the compilation time of 1 hour and 20 minutes before I
use incremental compilation. Does this sound right to you? I was
expecting more time deduction.
I have 34 logiclock regions in the design, but I didn't assign the top
level to a logiclock region. Could this be the problem?
The messages below seem to suggest that the placement and routing was
preserved.
Info: The Fitter has identified 35 logical partitions of which 34 have
a previous placement to use
Info: Previous placement does not exist for 5155 of 5155 atoms in
partition Top
Info: Previous placement and routing used for 5041 of 5041 atoms in
partition xxxx:xxxx_1
Info: Previous placement and routing used for 5036 of 5036 atoms in
partition xxxx:xxxx_2
...................
But still, the log shows that the fitter spent 10 minutes on physical
synthesis optimization for speed, so the placement took about 13
minutes. Then the router took about 36 minutes.
The top level only has some glue logic, most of the design are in the
34 logic partitions. If the placement and routing of those partitions
are indeed preserved, it shouldn't take this long to route the top
level.
Any comments?
Hua
Article: 132446Morphiend , Thank you ! But unfortunately this solution doesn't fix my problem definitly , in fact i v got a new warning : " Match_cycle = 0. done. '2': Reading status register contents... CRC error : 0 Decryptor security set : 1 DCM locked : 1 DCI matched : 1 End of startup signal from Startup block : 0 status of GTS_CFG_B : 0 status of GWE : 0 status of GHIGH : 0 value of MODE pin M0 : 0 value of MODE pin M1 : 0 Value of MODE pin M2 : 0 Internal signal indicates when housecleaning is completed: 1 Value driver in from INIT pad : 0 Internal signal indicates that chip is configured : 0 Value of DONE pin : 0 Indicates when ID value written does not match chip ID: 0 Decryptor error Signal : 1 System Monitor Over-Temperature Alarm : 0 startup_state[18] CFG startup state machine : 0 startup_state[19] CFG startup state machine : 0 startup_state[20] CFG startup state machine : 0 E-fuse program voltage available : 0 SPI Flash Type[22] Select : 1 SPI Flash Type[23] Select : 1 SPI Flash Type[24] Select : 1 CFG bus width auto detection result : 0 CFG bus width auto detection result : 0 Reserved : 0 BPI address wrap around error : 0 IPROG pulsed : 0 read back crc error : 0 Indicates that efuse logic is busy : 0 INFO:iMPACT:2218 - Error shows in the status register, release done bit is NOT 1. INFO:iMPACT:2219 - Status register values: INFO:iMPACT - 0111 0000 0001 0000 1000 0011 1000 0000 INFO:iMPACT:579 - '2': Completed downloading bit file to device. Match_cycle = 0. INFO:iMPACT - '2': Checking done pin....done. '2': Programming terminated. DONE did not go high. PROGRESS_END - End Operation. Elapsed time = 27 sec. " Thanks for the answer though. DajjouArticle: 132447
krw wrote: > Toolset: ISE/ModelSim_PE/VHDL > > I've been asked to modify one of my designs for another application > so decided it was time to parameterize it as much of it as possible. > I ran into a roadblock changing configuration of CoreGen devices, so > was simply going to force the eventual user to go through the GUI > for any modifications. Then I RTFM. ;-) > > In the Comparator V9.0 Product Specification there an example of > direct instantiation (Page 7), which looks like it'll save me a lot > of headaches. I can simply use the generics I already have to > manipulate the core. My problem is that ISE doesn't find the > comparator in the library. I've had the problem (with ModelSim) > where the libraries change and I'm pointing to an old copy but I > don't know where to tell ISE where the libraries are. I've always > used the GUI to generate cores before, but I really like the idea of > direct instantiation. I can make my designs far more flexible > without a whole lot of work. Anyone with a cluestick? > > Any reason to not just infer the comparator? VHDL generics make this sort of thing a breeze. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 132448
Florian wrote: > Hi > > I have a very basic question. Xilinx permits me to initialize Block RAM > with an external data file. The thing I am just wondering is, how do I > download this file on the FPGA? Do I need to have a UART to download > this file? Because I cant find an option with CHipscope, there I can > just configure the FPGA with a new bit stream. > > Cheers for helpful comments, > Floh Hello Florian, I have had exactly the same trouble as you did and I never found a solution either. UART is too slow for this purpose at 10kB/second. I think ideally I would like to use ethernet interface for data communication. I've looked into the opencores IP cores and some of the MAC cores can be useful. The problem with using ethernet interface is then I also need to design a custom RAM interface to interact with the ethernet interface. This quickly grows beyond my time and capability as a fpga hobbist. My board (spartan 3A) has all the features to set up something like this to happen. If you want to go this direction for data communication, I can work together with you. FeiArticle: 132449
On May 27, 7:36 pm, Mike Treseler <mike_trese...@comcast.net> wrote: > Narendra Sisodiya wrote: > > This is my final project , I want to work hard , rather then making > > some work around to problem, I do not have proper guidance, hope i > > will get here,. > > Choose a simpler project or drop the class. > > -- Mike Treseler Thanks Mike for your concern, But now I am too late, today is my presentation for masters. (got a good lesson)
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