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>Bottom line -- you really need to compile *your* design to both Stratix and >Virtex (or whatever families you are interested in) before you will really >know what the story is density. Averages don't matter much to you if yours >is that design that gets hosed in one architecture or the other! Is just recompiling good enough to be interesting? (Yes, better than nothing and I'll take whatever I can get.) Suppose I start with some "clean" vendor neutral code. How much do I gain in speed or space by hacking the code to take advantage of special features of an architecture? If I have code that has been tweaked for one vendor, does that get in the way (as compared to not help) if I just compile it for another architecture? How often is real code thoroughly tied to a particular chip? Say by adjusting the pipeline to fit well. Or using a multiplier as a shifter because it would otherwise be idle. Or do all interesting FPGAs these days have multipliers and dual port RAMs and ... that are reasonably equivalent? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 60676
Yeah!!!! I success!!! I have set the baud rate to 1200, no parity bit ,7 data bits and 1 stop bit Use the standard serial is not work Need to connect the pin on our own. Mouse's RTS and GND need to connect to a 5V and GND respectively, they can be connected to 2 pins just besides the debug UART the mouse txd and rxd connect to the stratix board txd and rxd respectively. "Jesse Kempa" <kempaj@yahoo.com> ??? news:95776079.0309180911.4f8937ae@posting.google.com ???... > "clsan" <clsan@cuhk.edu.hkk> wrote in message news:<bkbs56$sbn$1@justice.itsc.cuhk.edu.hk>... > > thx... > > I found that I can use the hyper terminal to communicate with the nios > > through the debug port, but I wonder whether the debug port has power pin to > > give the mouse.Do I need to do anything to activate the power pin or not? > > > > Thank you very much > > > > San > > > > Hi San, > > You might check the dev. board schematic (installed into the Nios kit > "documents/nios_stratix_1s10" folder) page 32, which goes over the > RS232 connections between FPGA & DB9 connectors. We use the same > circuit for both serial ports on the board. The distinction of > communication vs. debug serial port is just for software purposes > (where does STDOUT go...). For hardware development & interfacing > purposes, both ports are functionally equivalent. > > You might also look at whether the 'extra' UART pins are needed for > your mouse (I personally don't have any experience with serial mice!). > In the most basic UART you can create with SOPC Builder, there are TXD > & RXD pins only (because we are just interfacing to a PC terminal). > The remaining UART pins (RTS, CTS, etc.) are optional, and can be > turned on by editing the UART details for the UART(s) in your SOPC > Builder system... > > Jesse Kempa > Altera Corp. > jkempa at altera dot comArticle: 60677
Try (bash), export LD_ASSUME_KERNEL=2.4.1 It runs fine on my RH9, Hans. www.ht-lab.com "Garry Allen" <garrya@ihug.com.au> wrote in message news:3abc4240.0309181808.3e1b9cbc@posting.google.com... > I am very thankful that Xilinx is now supporting Linux directly in > ISE6.1. However, out of the box it only directly supports Redhat 7.3 > and Redhat 8. Has anyone managed to install it under Redhat 9 and what > if anything did you need to do to get it to call the glibc libraries > successfully? > > At the moment when I run ./setup, it fails with an error msssage > stating that it cannot find the glibc libraries. I am unsure if I can > run multiple versions of the gcc compiler > Comments > Thanks > Garry AllenArticle: 60678
"CF" <carl@notsoform.com> wrote in message news:<oMuab.1897$YO5.1362646@news3.news.adelphia.net>... > Parallel JTAG cable on a USB-only W2K laptop? :( you are right about eveything. sorry for you. iMpact uses kernel mode driver to talk to parallel port so even if you install kernel mode driver to emulate LPT at real io address this would not be recognized by iMpact, as it also uses kernel access and bypasses io virtualization. what you can do: 1) there is a japanese project (visual studio project) for downloading xilinx FPGAs using FT232 or FT245 chips, basically you just connect FGPA to FT232 (1:1 pin map) and use the supplied downloader to download bitstreams. 2) you take free sources of Alter JAM player, and change the port access to work with the IO as described above [1]. then you have JAM player that works with USB JTAG cable. unfortunatly the JAM files produced by iMpact do have sometimes trouble with unpatched JAM player, but this can eventually be solved. http://www.hdl.co.jp/ndoc/D2XX/BitBangMode.html above link has the info about using FT232BM/245BM I was going to offer you a free usb module but it has FT232AM on it and cat be used. sorry. optionally, if you need low low cost there is a free design http://www.cesko.host.sk/IgorPlugUSB/IgorPlug-USB%20(AVR)_eng.htm the above can be built from components of total cost aroung 5 USD and it works, could also be used for downloader (but would be REAL REAL SLOW!!) anttiArticle: 60679
Hi! I am using a Spartan 2 XC2S150 Xilinx FPGA. I have a few questions on the Parallel Cable 4 used for the configuration: 1)The PC4 has a pin "Vref". If i am using Spartan 2 XC2S150 with Vcco=3.3V and VCCINT=2.5, what should i connect to Vref? 3.3 or 2.5? 2)The new Xilinx Platform PROMS can be In System Programmed via JTAG. They show a configuration diagram in which the TMS,TCK,TDI pins from the JTAG connector are connected to the PROMS TMS,TCK and TDI pins. The TDO pin of PROM is connecte dto FPGAs TDI pin, and finally FPGAs TDO pin connected to JTAG connector's TDO pin. The TMS and TCK pins from the connector are also connected to FPGAs TMS and TCK pins. In addition to this, the FPGA and PROM are shown connecte din Master Serial mode. Please See page 8 fig: 5 of : http://direct.xilinx.com/bvdocs/publications/ds123.pdf The question is that why is the diagram involving "FPGA" into JTAG signals(FPGAs TMS,TCK,TDI and TDO pins used), despite the fact that FPGA can be configured by Master Serial mode after PROM is configued through JTAG. ? Can this setup also configure FPGA directly through JTAG? or its just for Boundary scan of the FPGA? Please help. Thanks RiderArticle: 60680
Is it possible to use the plugs library without an uart? I keep getting: cpu_sdk/lib/libnios32.a(plugs_print.c.o): In function `d_print_tcp_packet': plugs_print.c.o(.text+0x384): undefined reference to `nr_uart_txchar' ... I would expect no calls to any uart routines whenever I build a system with no serial ports. I've NOT included the plugs debugging routines. However, I have included the oci_core. (NIOS 3.1/Quartus II 3.0SP1 under Linux) Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 60681
Hi! I'm a student and doing a project to construct an Oversampling Delta-Sigma DAC. I planned to build the system using Cadence, Verilog HDL and FPGA which are totally new to me, I don't know whether the FPGA can be programmed to build functions like oversampling and interpolation, or should I make that part by other electronic components and connect to the FPGA containing the delta-sigma modulator only? Hope someone can answer my question. Thanks in advance! Best Regards, EvaArticle: 60682
Dear all: I get a Digilab2 which comes from Digilent. I read the user manual from web site (www.digilent.cc). It mentation that "power supply must be connected before the parallel cable or the board may hang in a non-communicating state". But I always got iMAPCT complains that "Communication with the cable can¡¦t estabilish". I use parallel port to configure it. Have anyone used this FPGA board before ?Article: 60683
ccchen (ccchen@alumni.ee.ncu.edu.tw) wrote: : Dear all: I get a Digilab2 which comes from Digilent. I read : the user manual from web site (www.digilent.cc). : It mentation that "power supply : must be connected before the parallel cable or the board may : hang in a non-communicating state". : But I always got iMAPCT complains that "Communication with the : cable can¡¦t estabilish". I use parallel port to : configure it. Have anyone used this FPGA board before ? Have you checked 'sw1' on the board? This is the 'Program enable switch' next to the parallel port connector. This must be set to the 'JTAG' position, which on my D2E board is the direction away from the edge of the board. If that fails, it's the obvious questions first... Is the power LED glowing? Are you definitly using a parallel cable (not some serial etc.) and the like --- ta cdsArticle: 60684
shabana_rizvi@yahoo.com (rider) wrote in message news:<ca3a68c8.0309190250.7c39fb72@posting.google.com>... > Hi! > > I am using a Spartan 2 XC2S150 Xilinx FPGA. I have a few questions on > the Parallel Cable 4 used for the configuration: > > 1)The PC4 has a pin "Vref". If i am using Spartan 2 XC2S150 with > Vcco=3.3V and VCCINT=2.5, what should i connect to Vref? 3.3 or 2.5? 3.3V (2.5 would possible also work, but not correct) > 2)The new Xilinx Platform PROMS can be In System Programmed via JTAG. > They show a configuration diagram in which the TMS,TCK,TDI pins from > the JTAG connector are connected to the PROMS TMS,TCK and TDI pins. > The TDO pin of PROM is connecte dto FPGAs TDI pin, and finally FPGAs > TDO pin connected to JTAG connector's TDO pin. The TMS and TCK pins > from the connector are also connected to FPGAs TMS and TCK pins. In > addition to this, the FPGA and PROM are shown connecte din Master > Serial mode. Please See page 8 fig: 5 of : > > http://direct.xilinx.com/bvdocs/publications/ds123.pdf > > The question is that why is the diagram involving "FPGA" into JTAG > signals(FPGAs TMS,TCK,TDI and TDO pins used), despite the fact that > FPGA can be configured by Master Serial mode after PROM is configued > through JTAG. ? Can this setup also configure FPGA directly through > JTAG? or its just for Boundary scan of the FPGA? you are right, if you dont want to download the FPGA over JTAG and dont want todo boundary scan (boundary scan is not supported by Cable IV anyway) you can leave the FPGA JTAG pins unconnected. anttiArticle: 60685
Antti Lukats wrote: > shabana_rizvi@yahoo.com (rider) wrote in message news:<ca3a68c8.0309190250.7c39fb72@posting.google.com>... > > Hi! > > > > I am using a Spartan 2 XC2S150 Xilinx FPGA. I have a few questions on > > the Parallel Cable 4 used for the configuration: > > > > 1)The PC4 has a pin "Vref". If i am using Spartan 2 XC2S150 with > > Vcco=3.3V and VCCINT=2.5, what should i connect to Vref? 3.3 or 2.5? > > 3.3V (2.5 would possible also work, but not correct) > > > 2)The new Xilinx Platform PROMS can be In System Programmed via JTAG. > > They show a configuration diagram in which the TMS,TCK,TDI pins from > > the JTAG connector are connected to the PROMS TMS,TCK and TDI pins. > > The TDO pin of PROM is connecte dto FPGAs TDI pin, and finally FPGAs > > TDO pin connected to JTAG connector's TDO pin. The TMS and TCK pins > > from the connector are also connected to FPGAs TMS and TCK pins. In > > addition to this, the FPGA and PROM are shown connecte din Master > > Serial mode. Please See page 8 fig: 5 of : > > > > http://direct.xilinx.com/bvdocs/publications/ds123.pdf > > > > The question is that why is the diagram involving "FPGA" into JTAG > > signals(FPGAs TMS,TCK,TDI and TDO pins used), despite the fact that > > FPGA can be configured by Master Serial mode after PROM is configued > > through JTAG. ? Can this setup also configure FPGA directly through > > JTAG? or its just for Boundary scan of the FPGA? > > you are right, if you dont want to download the FPGA over JTAG > and dont want todo boundary scan (boundary scan is not supported > by Cable IV anyway) Antti, why are you saying that the boundary scan is not supported with PAR cable IV ?? - or it's a wild guess... Aurash > you can leave the FPGA JTAG pins unconnected. > > antti -- __ / /\/\ Aurelian Lazarut \ \ / System Verification Engineer / / \ Xilinx Ireland \_\/\/ phone: 353 01 4032639 fax: 353 01 4640324Article: 60686
rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F686187.8F7C65A5@yahoo.com>... > rob d wrote: > > > > Here is a solution that I can't yet find a hole in. > > > > Put a comparator on the output of the flip flop(ff1) and call its > > output "meta" > > comparator indicates meta when ff1 output is just above a logic 1 min > > down to just below a logic 0 max. > > > > now create the next flip flop > > > > when meta then ff2 = not ff2 (if ff1 is metastable its input was > > changing) > > else ff2 = ff1. > > > > ff2 will never be meta stable as long as timing for meta is met. > > > > We can now use ff1 in a state machine by creating a combinatorial > > signal that reflects what ff1 is doing or trying to do. > > > > when meta then ff1_meta_hard = ff2 else ff1_meta_hard = ff1. > > > > even if you don't shoot me down I don't expect thousands of > > comparators in Vertex 4! :-) > > I don't understand why this is so hard to understand. Nothing personal, > it is just that a lot of people keep trying to make the comparator > solution work. The problem is that the output of the comparator has the > same problem as the output of FF1. It can be inderterminate (between > logic 0 and logic 1) for an indeterminate amount of time. "meta" can be > in transition at the time that FF2 is clocked with will clearly lead to > FF2 going metastable. > I accept that with op amps with non infinite gain then just at the edges of the comparator detection the comparator timing might be slow or unknown(what you have called metastable-I don't know why), this does not matter. Lets just suppose that ff1 was only just metastable and was nearly high. In this scenario with meta unknown then, the mux on ff2 may be switching wildly or trying to average (I don't know modern semi theory) the two inputs to ff2. However ff1 is just about 1 and so is "not ff2" and ff2 will see a solid 1. There may be a hole in my "design" but unless there is something about op amp comparators I have forgotten (I did the theory about 15 yrs ago) then this isn't it. The problem with a forum like this is that someone steps out of the box and other people think that the "out of boxer" has no experience at all. As my last sentence sort of implied I'm not looking for a solution, the maths for metastability is well understood and I'm not looking to pay the obvious penalties for not using the classic solution. > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 60687
Peter Alfke <peter@xilinx.com> wrote in message news:<3F6A547B.D4673C29@xilinx.com>... > Virtex-II has 18 x 18 combinatorial multipliers with a through-delay of > <10 ns . > I think you can use this in a successive approximation loop with max 14 > or 16 cycles. That would mean you can afford 30 ns per cycle. 33 MHz > seems like a "piece-of-cake" to me. > Peter Alfke > Hi Terry, Peter's got the right idea...if latency is an issue, elaborating on my other post: N/D, with N and D both 16 bits... From the description of the physics, it is probably the case that the denominator will be limited in range, as the sensor will have neither infinite or zero resistance. With that in mind, two block rams in parallel may get you within 8 bits for a first approximation to the result, using a table lookup on the top 11 bits of D. After that, using one iteration of Newton-Raphson (see the other reference I gave) gets you 16 bits for 1/D, using one of the multipliers associated with one of the block rams. The other multiplier brings N back into the picture. Thus, a single cycle of delay through the block ram, plus combinatorial delay through the adds/mult for the Newton-Raphson iteration, plus combinatorial through the numerator multiplication. I'm confused by the statement: "No pipeline delay, but a few clock cycles are OK"? How do you distinguish a few clock cycles from a pipeline delay? Regards, John > "Theron Hicks (Terry)" wrote: > > > > Sorry Ray, > > I meant to give a little more detail than I ended up with. The number of > > clock cycles per divide is not critical. I cannot accept any pipeline delay, but > > I am willing to wait a few clock cycles before I get a final result. I basically > > need to get a divide-by result as quickly as possible. The inputs are 2 16 bit > > numbers and I need a minimum of 14 bits in the result. I would really like to get > > to 16 bits if possible. The resultant resistance (the quotient) is subtracted > > from the desired resistance. This difference serves as the input to a very fast > > PID controller. This controller serves to control the temperature of a hot-wire > > sensor in a research grade hot-wire anemometer. Based on that, the time delay > > between requesting a quotient and the time when that quotient is valid needs to be > > minimum. The 16 bit A/D currently has a latency of 460ns. The remainder of the > > PID control loop should take about 30ns. I want the division to be substantially > > faster than the sum of those two times if possible. As a maximum, it must be > > faster that 500ns. If it were much faster (~100ns) then I could look at faster > > A/D converters for an even higher system throughput when desired. I hope this > > clarifies things. > > > > Thanks, > > Theron > > > > Ray Andraka wrote: > > > > > You need to decide what your requirements are: > > > size, precision, accuracy, number of clocks per sample and clock rate. > > > You aren't going to get all of them at once, however if you can compromise on > > > accuracy, a normalize -> look up -> denormalize might be the best approach. > > > > > > Theron Hicks wrote: > > > > > > > Hello, > > > > I have a project in mind where I would like to caclculate the resistance > > > > of a sensor. Because of the remainder of the circuit configuration, this > > > > must be done using a voltage divider. If I implement this in a spartan3, > > > > what is the fastest I can do a 16bit divide (unsigned) Obviously I can do a > > > > shift and subtract, but I would prefer something a little faster. Any > > > > suggestions? (I know I could go to a fast DSP but again, I would prefer to > > > > stick with what I am most comfortable with (FPGAs). My intent is to use the > > > > smallest spartan3 if posible. > > > > Thanks, > > > > Theron Hicks > > > > > > -- > > > --Ray Andraka, P.E. > > > President, the Andraka Consulting Group, Inc. > > > 401/884-7930 Fax 401/884-7950 > > > email ray@andraka.com > > > http://www.andraka.com > > > > > > "They that give up essential liberty to obtain a little > > > temporary safety deserve neither liberty nor safety." > > > -Benjamin Franklin, 1759Article: 60688
I will try again... Two resistors in series. Top resistor is fixed value (40 ohms). Bottom resistor is a very small (5 micron dia) tungsten wire. (Resistance is RT. RT is held at 1.7 time the ambient temperature resistance (RA) of the tungsten by I^2*R.) We are trying to maintain a constant and elevated temperature in the tungsten wire. This is accomplished by maintaining a constant resistance in the tungsten wire. The temperature of the tungsten varies because of airflow past the tungsten and I^2*R heating of the tungsten. This heating is provided by a D/A who's output is connected to the 40 ohm resistor. Call this V1. The voltage drop across the tungsten is measured via the A/D. Call this V2. The desired ressitance of the tungsten is RD. RT can be calculated using V2/V1=RT/(RT+40). The error term RT-(1.7*RA) is the input to a PID controller. The output of the PID is (effectively) V1. V1 can be used to calculate the velocity of the airflow past the tungsten wire. The current (analog wheatstone bridge based) system has a cutoff frequency of about 35KHz. My simulation of the system using Matlab indicates that a digital control loop based system can respond at in excess of 100KHz even allowing for the time necessary to calculate RD using a division and allowing for a 460ns A/D converter. If I can get up to 250KHz, the market is wide open. Small quantities but high prices. Curently the analog system goes for $5 to $10k US per cahnnel. Even at 100KHz frequency response, I can sell them very easily at $2000 (US) per channel. Does that make a little more sense? The system is similar to the Pulse Width Modulated Constant Temperature Anemometer discribed in the first link below. The PWM circuitry is replaced with a digital PID using an A/D and a D/A converter. Alternatively, look at US patent 5,654,507. These links may (or may not) help clarify the issue. http://www.iop.org/EJ/abstract/0957-0233/14/3/302/ http://www.iop.org/EJ/abstract/0957-0233/9/5/006 Thanks, Theron Hicks "Hal Murray" <hmurray@suespammers.org> wrote in message news:vml5vnjsq83m28@corp.supernews.com... > >Even more, if I understand the application, it will be reading a slowly > >varying resistance. Using the previous result as the new approximation, and > >assuming reasonable rates of change, it should be able to generate a new > >result each cycle, after the first 16 cycles. > > It may be even simpler than that. > > You might be able to avoid the divide and come up with some > kludge heuristics, say table lookup on the difference between > the current reading and the previous reading and add/sub that > the the running answer. > > Something like that can easily get you lots of bits of output > and/or gives you a place to put in a PLL filter. (I'm guessing > this is some sort of PLL.) > > > I still don't understand the big picture. It takes two numbers to > do a divide, but the description only mentioned one A/D. Where does > the other number come from? Which one is on top? > > [obvious comments about multiply by inverse if you can] > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam. >Article: 60689
are you sure that Spartan 3 can not configure itself? antti@case2000.com (Antti Lukats) wrote in message news:<80a3aea5.0309182129.63dad53a@posting.google.com>... > naveen_jain86@hotmail.com (video1) wrote in message news:<b29aaa65.0309181138.1ffed2ad@posting.google.com>... > > I am working on a consumer product development. We have decided to use > > the Spartan 3 FPGA. But to keep the cost down, we want to use a very > > small PROM on the board. How could I program the Spartan 3 FPGA with a > > tiny PROM? > > > > I was thinking of creating a compressed bitstream for the small > > processor interface logic that will take hardly 5 to 10% of the > > slices(that should lead to good compression ratios so as to fit in a > > tiny PROM) and then use this logic to self configure the new bitstream > > file from the processor interface and the FPGA having an external > > interface to talk to itself using selectMAP port (since Spartan 3 > > does not have any ICAP module). > > read the postings - S3 logic (your tiny cpu) is not active during > reconfiguration, at least what I understood what xilinx had to say :( > > anttiArticle: 60690
I know it compresses the bitsream based on the unused slices in the design. But how exactly it work? Does the Xilinx Spartan 3 FPGA automatically understand this compressed bitstream (may be though some bitfile header settings)? If it really does, then why we dont have it as default? whether it saves 5% or 10% if there is no price to pay (like some decompression logic that u save if you dont used compressed option) why not all the people use it? ~NaveenArticle: 60691
> At least on the Cyclone board, this is not true -- only the most basic > pins are wired up on the DEBUG port (highly unfortunate IMO.) > > -hpa Ooops, my apologies! I checked the Stratix edition schematic only. Thank you. - JesseArticle: 60692
Hi Steven, I am using Spartan 3 in a product development. I had one question. It is said that Spartan3 supports partial reconfiguration though it does not have ICAP module. My questions are 1. Does Spartan 3 support active partial reconfiguration? I want to put a tiny CPU interface in the FPGA first, and then use this CPU inside the FPGA to reconfigure itself using the selectMap interface. 2. This question is useful only if Spartan 3 allows itself to configure itself. I will use master/slave serial mode to configure the FPGA with the CPU interface so the mode pins will have the corresponding settings. But but to reconfigure the FPGA from inside the FPGA I need to talk to selectMap interface..what happens to mode pins....or when I can use selectMap for active reconfiguration anytime independent of the mode and init pins. Thank you ~Naveen "Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> wrote in message news:<XFb9b.2983$n22.624510994@twister1.starband.net>... > ICAP, or the Internal Configuration Access Port, is not supported in > Spartan-3 FPGAs. Glimpses of the ICAP interface appear in various tools, > either because it was too difficult to remove this function from the > software, or the software mistakenly assumed that Spartan-3 had ICAP. > > Dynamic reconfiguration is still supported in Spartan-3 via the external > SelectMAP interface or JTAG, just not through the ICAP interface. The > decision to remove it was due to silicon resource requirements and testing > cost. Although dynamic reconfiguration is a powerful concept, few > consumer-oriented applications use it. > > The following is some background on partial reconfiguration in Spartan-3 and > the ICAP primitive. > > Does Spartan-3 Support Partial Reconfiguration? > > Virtex/E, Virtex-II, and Virtex-II Pro devices - generically called Virtex > throughout this article - support a feature called partial reconfiguration. > Using this feature, an application can modify a portion of the bitstream > programming inside an FPGA to change the FPGA's functionality. Spartan-3 > FPGAs support some of these same capabilities, but with limitations compared > to Virtex. > > Via today's design software, partial bitstream changes must be performed on > an entire IOB, CLB, or Block RAM column basis in both Virtex and Spartan-3 > FPGAs. For example, to change a single bit within a single LUT, the > application must update all the CLBs in the affected column. Any unmodified > CLBs within the column are overwritten with the same configuration data. > > Perhaps the most important difference between Virtex and Spartan-3 FPGAs is > how the FPGA logic behaves during the reconfiguration process. In the Virtex > devices, any unmodified bits in the affected column continue to operate > normally. Consequently, if bits within a column are unchanged, then the > surrounding logic continues to function normally. In Spartan-3 FPGAs, > however, even unmodified bits in a column are temporarily reset during the > reconfiguration process, which greatly complicates using partial > reconfiguration. Partial reconfiguration works in Spartan-3 FPGAs, just with > extra complications. > > A column consists of multiple configuration frames. Physically, the Virtex > hardware supports configuration changes at the frame level, but software > currently just supports changes at the column level. The Spartan-3 hardware > supports bitstream changes at the column level only. > > The application can partially reconfigure the FPGA via a variety of means, > including the parallel SelectMap configuration interface and the FPGA's JTAG > port. Virtex-II and Virtex-II Pro families also support another means called > the ICAP (Internal Configuration Access Port). The ICAP interface is similar > to the parallel SelectMAP interface, but is available from within the FPGA. > Although the Spartan-3 architecture is based on the Virtex-II and Virtex-II > Pro architectures, the Spartan-3 family does not support the ICAP interface. > > Table 1 summarizes how partial reconfiguration compares between families. > > Table 1. Partial Reconfiguration Support in Virtex-II vs. Spartan-3. > > > Software supports... > Virtex: Column-based reconfiguration > Spartan-3: Column-based reconfiguration > > Hardware supports... > Virtex: Frame-based reconfiguration > Spartan-3: Column-based reconfiguration > > Unmodified logic remains active during reconfiguration? > Virtex: Yes > Spartan-3: No > > Reconfigure via SelectMAP? > Virtex: Yes > Spartan-3: Yes > > Reconfigure via JTAG? > Virtex: Yes > Spartan-3: Yes > > Reconfigure via ICAP? > Virtex: Virtex-II and Virtex-II Pro only > Spartan-3: No > > > > > For more information on partial reconfiguration, visit the following web > links: > > Partial Reconfigurability Frequently Asked Questions > http://www.xilinx.com/ise/advanced/partial_reconf_faq.htm > > XAPP151: Virtex Series Configuration Architecture User Guide > http://support.xilinx.com/xapp/xapp151.pdf > > XAPP290: Two Flows for Partial Reconfiguration: Module Based or Small Bit > Manipulations > > http://www.xilinx.com/xapp/xapp290.pdf > > --------------------------------- > Steven K. Knapp > Applications Manager, Xilinx Inc. > Spartan-3/II/IIE FPGAs > http://www.xilinx.com/spartan3 > --------------------------------- > Spartan-3: Make it Your ASIC > > "Antti Lukats" <antti@case2000.com> wrote in message > news:80a3aea5.0309131115.164ea0ee@posting.google.com... > > Xilinx what is correct in ISE 5.1 schematics editor the ICAP primitive > > doesnt show, but if looking at XDL output then ICAP primitive does > > exist ?! > > > > I was very disappointed to see that Spartan 3 doesnt have ICAP > > (i.e. self reconfig) but it seems it is there? > > > > anttiArticle: 60693
Peter Alfke <peter@xilinx.com> wrote in message news:<3F6A547B.D4673C29@xilinx.com>...
> Virtex-II has 18 x 18 combinatorial multipliers with a through-delay of
> <10 ns .
> I think you can use this in a successive approximation loop with max 14
> or 16 cycles. That would mean you can afford 30 ns per cycle. 33 MHz
> seems like a "piece-of-cake" to me.
> Peter Alfke
>
(See my parallel post...I have to use Google for news posts, so I can't
put this after the other one...)
Ooops...my mistake, N-R requires _two_ multiplies per iteration. So,
balancing multipliers and block rams, use three block rams in parallel
to do 1st approximation using 12 MSBs of denominator, D. Depending on
range of the denominator, this should give a result accurate to at least
9 bits. One iteration of N-R gives 18 bits.
OK, for those who don't want to go to the literature,
N-R iteration for 1/D is:
X[i+1] = X[i] * (2 - D * X[i])
A little expensive (three block rams organized as 12addr x 4bits, and
their associated multipliers), but fast...one cycle, plus combintorial
delays.
Regards,
John
> "Theron Hicks (Terry)" wrote:
> >
> > Sorry Ray,
> > I meant to give a little more detail than I ended up with. The number of
> > clock cycles per divide is not critical. I cannot accept any pipeline delay, but
> > I am willing to wait a few clock cycles before I get a final result. I basically
> > need to get a divide-by result as quickly as possible. The inputs are 2 16 bit
> > numbers and I need a minimum of 14 bits in the result. I would really like to get
> > to 16 bits if possible. The resultant resistance (the quotient) is subtracted
> > from the desired resistance. This difference serves as the input to a very fast
> > PID controller. This controller serves to control the temperature of a hot-wire
> > sensor in a research grade hot-wire anemometer. Based on that, the time delay
> > between requesting a quotient and the time when that quotient is valid needs to be
> > minimum. The 16 bit A/D currently has a latency of 460ns. The remainder of the
> > PID control loop should take about 30ns. I want the division to be substantially
> > faster than the sum of those two times if possible. As a maximum, it must be
> > faster that 500ns. If it were much faster (~100ns) then I could look at faster
> > A/D converters for an even higher system throughput when desired. I hope this
> > clarifies things.
> >
> > Thanks,
> > Theron
> >
> > Ray Andraka wrote:
> >
> > > You need to decide what your requirements are:
> > > size, precision, accuracy, number of clocks per sample and clock rate.
> > > You aren't going to get all of them at once, however if you can compromise on
> > > accuracy, a normalize -> look up -> denormalize might be the best approach.
> > >
> > > Theron Hicks wrote:
> > >
> > > > Hello,
> > > > I have a project in mind where I would like to caclculate the resistance
> > > > of a sensor. Because of the remainder of the circuit configuration, this
> > > > must be done using a voltage divider. If I implement this in a spartan3,
> > > > what is the fastest I can do a 16bit divide (unsigned) Obviously I can do a
> > > > shift and subtract, but I would prefer something a little faster. Any
> > > > suggestions? (I know I could go to a fast DSP but again, I would prefer to
> > > > stick with what I am most comfortable with (FPGAs). My intent is to use the
> > > > smallest spartan3 if posible.
> > > > Thanks,
> > > > Theron Hicks
> > >
> > > --
> > > --Ray Andraka, P.E.
> > > President, the Andraka Consulting Group, Inc.
> > > 401/884-7930 Fax 401/884-7950
> > > email ray@andraka.com
> > > http://www.andraka.com
> > >
> > > "They that give up essential liberty to obtain a little
> > > temporary safety deserve neither liberty nor safety."
> > > -Benjamin Franklin, 1759
Article: 60694"rider" <shabana_rizvi@yahoo.com> ha scritto nel messaggio news:ca3a68c8.0309190250.7c39fb72@posting.google.com... > The question is that why is the diagram involving "FPGA" > into JTAG > signals(FPGAs TMS,TCK,TDI and TDO pins used), despite the > fact that > FPGA can be configured by Master Serial mode after PROM is > configued > through JTAG. ? Can this setup also configure FPGA > directly through > JTAG? or its just for Boundary scan of the FPGA? Yes, you can also configure the FPGA directly via JTAG (it can be useful for debug: programming a FLASH PROM takes at least 20-30 seconds), but obviously when you power off, the configuration is lost. If you compile a bitfile with CCLK as starting clock and try to load it via JTAG, iMPACT outputs a warning and (if you want) it also changes on the fly the startup clock to JTAG. This is useful if you want to use the same bitfile either for PROM and FPGA (no need to recompile). You can also connect only the FLASH PROM to JTAG, leaving unconnected the FPGA; actually, in a Xilinx application note for an earlier configuration PROM they suggested to connect the configuration PROMs and the FPGAs to two different JTAG chains (I don't remember the exact reason, it had to do with some reliability considerations). -- LorenzoArticle: 60695
If anybody designs "vendor neutral" and relies on the compiler to get the best implementation in, say, Xilinx and Altera, the result will most likely the worst of all worlds. FPGA architecture evolution is still young. Certain aspects are almost standardized (4LUTs, carry, dual-ported RAMs, flexible-level I/O), but each vendor tries to outdo the other with clever and (hopefully) useful additions that the competitor does not (yet) have. Xilinx is very proud of its LUTRAMs, SRL16s and DCMs with fine phase stepping. I assume that Altera has their own very different goodies. There is no way that the "generic compiler" will make good use of all this. So it still takes a smart and imaginative designer to navigate between all these exciting capabilities that differentiate the vendors. FPGA are not (yet) a standardized commodity, the way automobiles have become after 100 years of evolution. Thank God ! Peter Alfke Hal Murray wrote: > > >Bottom line -- you really need to compile *your* design to both Stratix and > >Virtex (or whatever families you are interested in) before you will really > >know what the story is density. Averages don't matter much to you if yours > >is that design that gets hosed in one architecture or the other! > > Is just recompiling good enough to be interesting? (Yes, better > than nothing and I'll take whatever I can get.) > > Suppose I start with some "clean" vendor neutral code. How much do > I gain in speed or space by hacking the code to take advantage of > special features of an architecture? > > If I have code that has been tweaked for one vendor, does that get > in the way (as compared to not help) if I just compile it for > another architecture? > > How often is real code thoroughly tied to a particular chip? > Say by adjusting the pipeline to fit well. Or using a multiplier > as a shifter because it would otherwise be idle. > Or do all interesting FPGAs these days have multipliers and > dual port RAMs and ... that are reasonably equivalent? > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam.Article: 60696
Eva, if you can define a purely digital function, then it can be implemented in an FPGA. The constraints are speed, cost, and power consumption. But any digital design can fundamentally be implemented in an FPGA ( and even changed on-the-fly). Peter Alfke, Xilinx Applications Eva Lau wrote: > > Hi! > I'm a student and doing a project to construct an Oversampling > Delta-Sigma DAC. I planned to build the system using Cadence, Verilog > HDL and FPGA which are totally new to me, I don't know whether the FPGA > can be programmed to build functions like oversampling and > interpolation, or should I make that part by other electronic components > and connect to the FPGA containing the delta-sigma modulator only? > Hope someone can answer my question. Thanks in advance! > > Best Regards, > EvaArticle: 60697
Thanks, Theron. There seem to be many different ( very different) ways to solve the digital portion of your design, all offering better than the required performance. Good luck. As they say: Just do it! The various digital schemes may be a wash in the larger realm of things... Peter Alfke ======================== Theron Hicks wrote: > > I will try again... > > Two resistors in series. Top resistor is fixed value (40 ohms). Bottom > resistor is a very small (5 micron dia) tungsten wire. (Resistance is RT. > RT is held at 1.7 time the ambient temperature resistance (RA) of the > tungsten by I^2*R.) We are trying to maintain a constant and elevated > temperature in the tungsten wire. This is accomplished by maintaining a > constant resistance in the tungsten wire. The temperature of the tungsten > varies because of airflow past the tungsten and I^2*R heating of the > tungsten. This heating is provided by a D/A who's output is connected to > the 40 ohm resistor. Call this V1. The voltage drop across the tungsten is > measured via the A/D. Call this V2. The desired ressitance of the tungsten > is RD. RT can be calculated using V2/V1=RT/(RT+40). The error term > RT-(1.7*RA) is the input to a PID controller. The output of the PID is > (effectively) V1. V1 can be used to calculate the velocity of the airflow > past the tungsten wire. The current (analog wheatstone bridge based) system > has a cutoff frequency of about 35KHz. My simulation of the system using > Matlab indicates that a digital control loop based system can respond at in > excess of 100KHz even allowing for the time necessary to calculate RD using > a division and allowing for a 460ns A/D converter. If I can get up to > 250KHz, the market is wide open. Small quantities but high prices. > Curently the analog system goes for $5 to $10k US per cahnnel. Even at > 100KHz frequency response, I can sell them very easily at $2000 (US) per > channel. Does that make a little more sense? The system is similar to the > Pulse Width Modulated Constant Temperature Anemometer discribed in the first > link below. The PWM circuitry is replaced with a digital PID using an A/D > and a D/A converter. Alternatively, look at US patent 5,654,507. > > These links may (or may not) help clarify the issue. > > http://www.iop.org/EJ/abstract/0957-0233/14/3/302/ > http://www.iop.org/EJ/abstract/0957-0233/9/5/006 > > Thanks, > Theron Hicks > > "Hal Murray" <hmurray@suespammers.org> wrote in message > news:vml5vnjsq83m28@corp.supernews.com... > > >Even more, if I understand the application, it will be reading a slowly > > >varying resistance. Using the previous result as the new approximation, > and > > >assuming reasonable rates of change, it should be able to generate a new > > >result each cycle, after the first 16 cycles. > > > > It may be even simpler than that. > > > > You might be able to avoid the divide and come up with some > > kludge heuristics, say table lookup on the difference between > > the current reading and the previous reading and add/sub that > > the the running answer. > > > > Something like that can easily get you lots of bits of output > > and/or gives you a place to put in a PLL filter. (I'm guessing > > this is some sort of PLL.) > > > > > > I still don't understand the big picture. It takes two numbers to > > do a divide, but the description only mentioned one A/D. Where does > > the other number come from? Which one is on top? > > > > [obvious comments about multiply by inverse if you can] > > > > -- > > The suespammers.org mail server is located in California. So are all my > > other mailboxes. Please do not send unsolicited bulk e-mail or > unsolicited > > commercial e-mail to my suespammers.org address or any of my other > addresses. > > These are my opinions, not necessarily my employer's. I hate spam. > >Article: 60698
16 cycles of compare/subtract can go pretty darned fast! You can do it compact in a single stage with a shift register for the result (16 bit suptractor, 16 bit registered mux). 16 clock cycles at 6ns per clock cycle is very achievable. If you want to throw resources at it, you could do a simple combinatorial divide. I got 81ns in the tiny Spartan-3 with a first rough-cut, no attempts to make it fast. "Theron Hicks (Terry)" <hicksthe@egr.msu.edu> wrote in message news:3F6A4BF2.6D4F21A@egr.msu.edu... > Sorry Ray, > I meant to give a little more detail than I ended up with. The number of > clock cycles per divide is not critical. I cannot accept any pipeline delay, but > I am willing to wait a few clock cycles before I get a final result. I basically > need to get a divide-by result as quickly as possible. The inputs are 2 16 bit > numbers and I need a minimum of 14 bits in the result. I would really like to get > to 16 bits if possible. The resultant resistance (the quotient) is subtracted > from the desired resistance. This difference serves as the input to a very fast > PID controller. This controller serves to control the temperature of a hot-wire > sensor in a research grade hot-wire anemometer. Based on that, the time delay > between requesting a quotient and the time when that quotient is valid needs to be > minimum. The 16 bit A/D currently has a latency of 460ns. The remainder of the > PID control loop should take about 30ns. I want the division to be substantially > faster than the sum of those two times if possible. As a maximum, it must be > faster that 500ns. If it were much faster (~100ns) then I could look at faster > A/D converters for an even higher system throughput when desired. I hope this > clarifies things. > > Thanks, > Theron > > Ray Andraka wrote: > > > You need to decide what your requirements are: > > size, precision, accuracy, number of clocks per sample and clock rate. > > You aren't going to get all of them at once, however if you can compromise on > > accuracy, a normalize -> look up -> denormalize might be the best approach. > > > > Theron Hicks wrote: > > > > > Hello, > > > I have a project in mind where I would like to caclculate the resistance > > > of a sensor. Because of the remainder of the circuit configuration, this > > > must be done using a voltage divider. If I implement this in a spartan3, > > > what is the fastest I can do a 16bit divide (unsigned) Obviously I can do a > > > shift and subtract, but I would prefer something a little faster. Any > > > suggestions? (I know I could go to a fast DSP but again, I would prefer to > > > stick with what I am most comfortable with (FPGAs). My intent is to use the > > > smallest spartan3 if posible. > > > Thanks, > > > Theron Hicks > > > > -- > > --Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com > > > > "They that give up essential liberty to obtain a little > > temporary safety deserve neither liberty nor safety." > > -Benjamin Franklin, 1759 >Article: 60699
Hal Murray wrote:
> Is just recompiling good enough to be interesting? (Yes, better
> than nothing and I'll take whatever I can get.)
I always test synth code on both brands.
> Suppose I start with some "clean" vendor neutral code. How much do
> I gain in speed or space by hacking the code to take advantage of
> special features of an architecture?
You can make significant improvements in speed and space.
The downside is a longer design time, a commitment
to a single family from a single vendor and
complications to simulation and design reuse.
> If I have code that has been tweaked for one vendor, does that get
> in the way (as compared to not help) if I just compile it for
> another architecture?
In that case, you must learn the alternate architecture
and recode all of the vendor specific instances and attributes.
> How often is real code thoroughly tied to a particular chip?
It's quite easy to do. Both brands A and X lead you down
that path with wizards, core generators and app notes.
> Say by adjusting the pipeline to fit well. Or using a multiplier
> as a shifter because it would otherwise be idle.
That is a design decision.
If you design with inference only, you lose some options.
> Or do all interesting FPGAs these days have multipliers and
> dual port RAMs and ... that are reasonably equivalent?
The common inferrable set includes carry chains, ram, rom and
and pseudo-dual port ram like this:
if rising_edge(clk) then
if we = '1' then
mem(to_integer(push_tail_ptr)) <= data_i; -- raw address
end if;
data_q <= mem(to_integer(pop_head_ptr)); -- mem data after pop low
end if;
-- Mike Treseler
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