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GOF, Gates On the Fly, GUI tool to do netlist trace and modification(ECO). New Release of GOF V2.097 with features 1. Integrate a parser for Synopsys Primetime Timing Report file. 2. Detect bottlenecks from timing report file. 3. Import related violated paths into Partial Schematic. 4. Visually isolating bottleneck on the schematic. 5. Users can control to draw schematic of violated paths by defining Start-Point, Through-Point and End-Point. 6. Wild card support to match Start/Through/End points. 7. Interactive with build-in ECO engine to fix the violated paths. Check Timing ECO example http://www.nandigits.com/timing_eco.htm Nandy www.nandigits.com Netlist Debug/ECO in GUI mode.Article: 97176
"Hendra" <u1000393@email.sjsu.edu> schrieb im Newsbeitrag news:1140234485.021360.224290@z14g2000cwz.googlegroups.com... > What is the price for ISE Simulator? There is no mention of it in > Xilinx Online Store. How does it compare to ModelSim Xilinx Edition > III? > > Hendra > its not available as standalone product ASFAIK AnttiArticle: 97177
Thank yo very much john for the replay.... I agree with your findings. I wrote a program which converts individual bits to hex values.... Also there is no GUI to genrate vcd file in the model sim.Article: 97178
Thanks for your replies. Happened to find a I2C slave code alone. And since the SCL turned out to be a input alone I could easily put the schmitt trigger and it worked very well.Article: 97179
http://www.rawether.net/ this cost very much like 200/400$ depending on the type.Article: 97180
I found a solution i think it will work. I will test it int the next
week.
I will use an opsource program http://www.winpcap.org/
This program manage all the stuff like open the networkadapter and
stuff like that.
here is some code i found:
#include <stdlib.h>
#include <stdio.h>
#include <pcap.h>
int main(int argc, char **argv)
{
pcap_t *fp;
char errbuf[PCAP_ERRBUF_SIZE];
u_char packet[100];
int i;
/* Check the validity of the command line */
if (argc != 2)
{
printf("usage: %s interface", argv[0]);
return 1;
}
/* Open the adapter */
if ((fp = pcap_open_live(argv[1], // name of the device
65536, // portion of the packet to capture. It doesn't matter
in this case
1, // promiscuous mode (nonzero means promiscuous)
1000, // read timeout
errbuf // error buffer
)) == NULL)
{
fprintf(stderr,"\nUnable to open the adapter. %s is not supported by
WinPcap\n", argv[1]);
return 2;
}
/* Supposing to be on ethernet, set mac destination to 1:1:1:1:1:1 */
packet[0]=1;
packet[1]=1;
packet[2]=1;
packet[3]=1;
packet[4]=1;
packet[5]=1;
/* set mac source to 2:2:2:2:2:2 */
packet[6]=2;
packet[7]=2;
packet[8]=2;
packet[9]=2;
packet[10]=2;
packet[11]=2;
/* Fill the rest of the packet */
for(i=12;i<100;i++)
{
packet[i]=i%256;
}
/* Send down the packet */
if (pcap_sendpacket(fp, // Adapter
packet, // buffer with the packet
100 // size
) != 0)
{
fprintf(stderr,"\nError sending the packet: \n", pcap_geterr(fp));
return 3;
}
pcap_close(fp);
return 0;
}
The way to find the name of the network-adapter can be found here:
http://www.winpcap.org/docs/docs31/html/group__wpcap__tut1.html
thanks to all of you for the help.
roggey
Article: 97181Jim Granville wrote: > For those looking at smaller FPGA and USB, this new device has > both Host and Peripheral modes, and has a 26MHz SPI link. > Interface is via 32 registers, includes 15KV ESD USB drivers. > > Opens up FPGA access USB Flash drives as storage, and USB keyboards etc... > -jg > Yup, that definitly looks nice ! I'd like some of those ... But I didn't find them at digikey or farnell ... Are they already available ? Sylvain.Article: 97182
On Sat, 18 Feb 2006 11:02:38 +0100, Sylvain Munaut <com.246tNt@tnt> wrote: >Jim Granville wrote: >> For those looking at smaller FPGA and USB, this new device has >> both Host and Peripheral modes, and has a 26MHz SPI link. >> Interface is via 32 registers, includes 15KV ESD USB drivers. >> >> Opens up FPGA access USB Flash drives as storage, and USB keyboards etc... >> -jg >> > >Yup, that definitly looks nice ! > >I'd like some of those ... But I didn't find them at digikey or farnell >... Are they already available ? > > > Sylvain. It's Maxim - do you really expect them to be available..?Article: 97183
On Fri, 17 Feb 2006 19:14:31 -0500, "MM" <mbmsv@yahoo.com> wrote: >I am just guessing here. Are your constraints by any chance included in >between the following lines? > >#PACE: Start of Constraints generated by PACE >..... >#PACE: End of Constraints generated by PACE > >I would expect PACE to respect only whatever is outside of these lines... >But I don't really know how it works in practice... > >/Mikhail > As of 6.1, the floorplanner certainly didn't respect area constraints. At least it wouldn't preserve them in any UCF it wrote back out. Maybe related, maybe not. - BrianArticle: 97184
2ALuPin@web.de, Related to DQS and DQ. I can not really know! I could just guess. I think it was clear from my previous post. 2Gabor, Thanks. I am using an Avnet Xilinx Virtex II Development Board-XC2V4000-FF1152 board (it has ADS-XLX-V2-DEV4000XP product code). I was running different tests but still can not get why it does not work. I just read some kind of random data.Article: 97185
ada wrote: > 2ALuPin@web.de, > Related to DQS and DQ. I can not really know! I could just guess. I think > it was clear from my previous post. > > 2Gabor, > Thanks. > I am using an Avnet Xilinx Virtex II Development Board-XC2V4000-FF1152 > board (it has ADS-XLX-V2-DEV4000XP product code). > I was running different tests but still can not get why it does not work. > I just read some kind of random data. > I don't know the controller you're using, nor your board. But my experience with ddr and ddr-controllers is that somewhere you have a DCM to generate the read clock and that DCM has a phase-shift and you need to adapt this timeshift according to your board (you can just try some value, find the lowest for which it work, then the highest and finally take a value in the middle ...) SylvainArticle: 97186
Try opencores.com this will work. Regards, Luc On 16 Feb 2006 23:05:37 GMT, pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote: >Anyone know what happened to opencores.org ..? > >The last trail is 2005-May.Article: 97187
The system I am designing is a pc scope. I guess I will know the trigger point. What I dont really understand is how you can generate precise offsets from the trigger if you want to sample in the GHz region as you are talking about picosecond values. I guess I dont fully understand the procedure Jon >"maxascent" <maxascent@yahoo.co.uk> wrote in message >news:kYydnaQMQMIAzmveRVn_vQ@giganews.com... >>I am designing a data aqu system using an fpga and adc sampling at 250MHz. >> I want to use equivalent time sampling to increase the sampling rate to a >> few GHz for repetative signals. I am not sure how to go about implementing >> it though. >> >> Any info would be welcome, thanks. >> >> Jon > >Are the aquisition triggers deterministic? You have different requirements >for a general purpose piece of test equipment versus an eye-diagram >analyzer. > >A general purpose piece of test equipment would tend to continuously acquire >data and decide which "bins" to put the samples in based on where the >trigger actually occurs within the acquisition clock period. This provides >the ability to "bin" as precisely as one can determine where in the period >the trigger occurs. > >A dedicated piece of equipment with known trigger points such as a telecom >analyzer can slave the sampling clock to the waveform being sampled and >"force" the alignment relative to the sample clock period (or conversely >align the sample clock to the bins). PLLs and DDS work beautifully here. > >So - do you want general purpose? Do you just want data 20 ns after the >trigger and later only? Do you want large pretriggers? > >I've seen equivalent time equipment (no real time permitted) where the >samples were 1 point per trigger with the data 10 ns or more after the >trigger. In this case, the single sample event could be delayed from the >trigger event precisely on a point-by-point basis. Since the trigger is >usually the point of interest, that test equipment used a high fidelity >delay line to sample the delayed channel a precise delay after the trigger >allowing a small pre-trigger. > >There are many ways to skin this cat. Engineering tradeoffs can't yet be >made with the information supplied. > > >Article: 97188
HI,
I just want to know is there any Virtex 4 based development board
on which i can add a 400 pin microprocessor and a SD RAM. I am not
worried about the board development but not found any board which has
that much free connections to the Virtex 4 chip. Please advice.
Thanks Sumesh V S
Article: 97189a small intro howto http://xilant.com/content/view/37/2/ and direct link to download for MB and PPC Win32 GCC binaries (compiled from EDK 8.1 release) http://xilant.com/component/option,com_remository/Itemid,53/func,select/id,9/ AnttiArticle: 97190
"ada" wrote: >> CUT > I am just a bit confused - among all nets in original UCF file I have > CLK_DDR_FB_IN and CLK_DDR_FB_OUT. In my design I am using only > CLK_DDR_FB_IN for giving my feedback signal to DDR. Should I use both? I > do not see any reason for it. > As far as I know there are two main schemes for DDR controller mainly adopted with virtex-4 (and virtex-2 , I think). One is that with the delay compensation line made from the ddr_clk_p line, fed back to fpga (in a clock bank): if I'm not wrong, this is the method adopted in opencores controller (and also by microblaze opb bus ddr controller with virtex-4). The second scheme has a dedicated line for delay compensation: look at your board schematics! From your citation or your board ucf file, I think this is the scheme adopted by you dev board. There's an output pin (CLK_DDR_FB_OUT) and an input pin (CLK_DDR_FB_IN): they are shorted with an appropriated length net (for compensating delay). This is the method I found in xilinx MIG. I'm not very experienced with ddr controller, but I think that there are hardware discrepancies between the two schemes (the delay length are different, if I'm not wrong) and perhaps also hdl descriptions are not directly reusable: perhaps they can be easily adjusted, but I don't really know. Opencores controller, in my opinion, is quite well described and very simple also for a newbie as me; but due to performances (I'm using on virtex-4) I focused my attention to xilinx website designs (using mig 1.4 ... poorly documented, in my opinion, for ddr - much better on ddr2). The fact that with chipscope you experience read problems, let me think that the problem is just in the feedback scheme/delay. If I've understood, this is just the re-syncronization trick for readings. Hope this may be useful to you and sorry if I've written some inaccuracies. Regards, stefanoArticle: 97191
Hi, I have a hardmacro that's quite small (2 slices) and that have 2 LUTs in them and I'd like to be able to choose the INIT string of theses two luts when I instanciate them. Is this somehow possible ? I have to instanciate quite a few of them with different parameters and I'd _hate_ to have to make as many hardmacro as I need different LUT4 config ... SylvainArticle: 97192
Mike Harrison <mike@whitewing.co.uk> wrote: > On Sat, 18 Feb 2006 11:02:38 +0100, Sylvain Munaut <com.246tNt@tnt> wrote: > It's Maxim - do you really expect them to be available..? > At least you can request samples now and the "buy"section tells about 2 weeks lead time. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 97193
"Sylvain Munaut" <com.246tNt@tnt> schrieb im Newsbeitrag news:43f72795$0$18969$ba620e4c@news.skynet.be... > Hi, > > > I have a hardmacro that's quite small (2 slices) and that have 2 LUTs in > them and I'd like to be able to choose the INIT string of theses two > luts when I instanciate them. Is this somehow possible ? > > I have to instanciate quite a few of them with different parameters and > I'd _hate_ to have to make as many hardmacro as I need different LUT4 > config ... > > > Sylvain convert .NMC to XDL and back, maybe it works that way (NMC is same format as NCD) AnttiArticle: 97194
A few weeks back I posted about importing a VHDL, actually a Xilinx Core,
into a system generator project as a black box. The help files give explicit
instructions under a heading specifically titled "Importing a Xilinx Core
into a Simulink Model". Well the issue was about inserting a CE pin into a
core wrapper for a core that does not have a CE pin. I kept trying to build
the wrapper and every time I brought it into the Simulink model it would
show a CE and CLK pin which it should not. After awhile I gave up and put it
aside for awhile.
The other day I was reading another part of the help documentation about
requirements on the VHDL code to import as a black box an saw that the
Verilog code must have all ports in lower case letters. My core is in VHDL
but I went and changed the added CE pin to use lower case letters and I
think I also put the ce pin after the CLK pin in the entity and component
declarations. Low and behold the importation to the simulink model did not
have the CE and CLK pins showing and the model even ran calling up Modelsim
and everything. What a PITA!!!!!!!!!.
Now that my model is running a bit, I still have issues with the rate at
which the model is running. The core I am using is a multichannel MAC FIR.
The help files show how to use a CE enable block to drive the ND pin of the
core. The core was initially designed to run at 100 KHz input rate and by
doing a x2 interpolation I expected a 200KHz output rate.
To feed the mulitichannel filter I put a TimeDivision multiplexer in
front of the filter driven by 4 sine wave blocks. I had to set the sample
time of the sine wave blocks to 1/ 25000. To drive the CE enable block I use
the output of the input TimeDivision multiplexer as an input. In my Modelsim
output I always see the ND pin high when I want it to toggle at the 100 KHz
rate. I've tried putting upsamplers and downsamplers on the input to the CE
enable block and always get errors about my sample rates not matching the
filter input rates or other errors.
Basically I'm a bit confused as you can probably tell about this whole
sample time setting in the blocks. I really first thought if I want the
filter to be fed at a 100KSa/s rate I should make all my sinewaves at that
rate. But then the multichannel time multiplexer was increasing the sample
rate of the sinewaves by 4 so I was getting a 400 KSa/ rate input to my
filter. Therefore I made the initial sine waves each at 25 KSa/s. When I
turn on the format according to sample rate option I see the output of the
multiplexer and the output of the CE block are the same color and both those
outputs go to the filter. When I look in Modelsim I see the filter doing a
x2 interpolation but the rates of the ND and RDY signals are no where near
what I expect 100 and 200 KSa/s respectively? Anyone out there playing with
this type stuff?
Tks
Chuck
Article: 97195Antti Lukats wrote: > "Sylvain Munaut" <com.246tNt@tnt> schrieb im Newsbeitrag > news:43f72795$0$18969$ba620e4c@news.skynet.be... > >>Hi, >> >> >>I have a hardmacro that's quite small (2 slices) and that have 2 LUTs in >>them and I'd like to be able to choose the INIT string of theses two >>luts when I instanciate them. Is this somehow possible ? >> >>I have to instanciate quite a few of them with different parameters and >>I'd _hate_ to have to make as many hardmacro as I need different LUT4 >>config ... >> >> >>Sylvain > > > convert .NMC to XDL and back, maybe it works that way > > (NMC is same format as NCD) How is that gonna help me ? What I'd like to do is when I instanciate in my VHDL code, be able to use generic to pass the INIT string of my two LUT4 like inst_I: my_hard_macro generic map ( INIT_LUT4_1 => x"0123", INIT_LUT4_2 => x"1234" ) port map ( -- my ports, ... ); SylvainArticle: 97196
In 7.1 I was editing the assigned pins. PACE would overwrite my existing UCF file about half way through and basically made it useless. It would leave out existing constraints and hack up others by breaking them in two. I think it has a parsing issue with long lines or comments. I ended up copying my original ucf file, going in to PACE to do the pin assignments I wanted to add and then closed PACE. I'd then go and edit the ucf in the text editor and add the lines from my original ucf file that got destroyed. Something is definitely broken here? Chuck ----- Original Message ----- From: "Roger" <enquiries@rwconcepts.co.uk> Newsgroups: comp.arch.fpga Sent: Friday, February 17, 2006 1:28 PM Subject: Xilinx UCF area constraints disappearing >I have a design with an Aurora RocketIO core and in the UCF file I've >added the following lines: > > INST Inst_rio0_top/Inst_rio0/lane_0_phase_align_i/phase_align_flops_r* > AREA_GROUP="PHASE_ALIGN_0_GRP"; > > # Place RIO0 lane_0_mgt_i at location X0Y1 > INST Inst_rio0_top/Inst_rio0/lane_0_mgt_i LOC=GT_X0Y1; > > AREA_GROUP "PHASE_ALIGN_0_GRP" RANGE=SLICE_X14Y152:SLICE_X15Y153; > > When I use PACE to modify a pin assignment or something equally trivial > and save the UCF, the AREA_GROUP "PHASE_ ..........;" line has > disappeared. Although the Aurora core does still seem to work, I thought > that the placement of the phase alignment FFs was important and was > explicitly indicated for good reason. Can anyone tell me what's going on > here please? Even if there's some setting somewhere that's telling the PAR > to ignore this type of constraint, why does it disappear? Is it something > to do with the fact that except for the pin assignments, all the UCF file > has been added textually i.e. not via PACE or the Constraints Editor? > > TIA, > > Rog. > >Article: 97197
On Sat, 18 Feb 2006 06:23:28 -0600, "maxascent" <maxascent@yahoo.co.uk> wrote: >The system I am designing is a pc scope. I guess I will know the trigger >point. What I dont really understand is how you can generate precise >offsets from the trigger if you want to sample in the GHz region as you >are talking about picosecond values. I guess I dont fully understand the >procedure One solution for triggering is to have a fast, continuous time trigger comparator start an analog ramp voltage (like in a monostable). This ramp voltage is then digitised with an ADC similar to the ones digitising the input voltages. Inspecting the values of the digitised ramp voltage will allow you to estimate the trigger point with respect to the sample instants. The accuracy is limited by the comparator jitter, which might be as low as some picoseconds. Regards, AllanArticle: 97198
"Sylvain Munaut" <com.246tNt@tnt> schrieb im Newsbeitrag news:43f72f54$0$27124$ba620e4c@news.skynet.be... > Antti Lukats wrote: >> "Sylvain Munaut" <com.246tNt@tnt> schrieb im Newsbeitrag >> news:43f72795$0$18969$ba620e4c@news.skynet.be... >> >>>Hi, >>> >>> >>>I have a hardmacro that's quite small (2 slices) and that have 2 LUTs in >>>them and I'd like to be able to choose the INIT string of theses two >>>luts when I instanciate them. Is this somehow possible ? >>> >>>I have to instanciate quite a few of them with different parameters and >>>I'd _hate_ to have to make as many hardmacro as I need different LUT4 >>>config ... >>> >>> >>>Sylvain >> >> >> convert .NMC to XDL and back, maybe it works that way >> >> (NMC is same format as NCD) > > How is that gonna help me ? > > What I'd like to do is when I instanciate in my VHDL code, be able to > use generic to pass the INIT string of my two LUT4 like > > inst_I: my_hard_macro > generic map ( > INIT_LUT4_1 => x"0123", > INIT_LUT4_2 => x"1234" > ) > port map ( > -- my ports, ... > ); > > > > Sylvain you cant do that ASFAIK, so XDL may be the only possibility to change an existing hardmacro, sure it involves some scripting to be done, etc, AnttiArticle: 97199
Our products are probably one of the closest matches to your needs. We have a new product Broaddown4 that will hopefully be showing at DATE in a couple of weeks but failing that will appear within the month after. If you are interested send me an email, on our board sales email that you can find on our website, with your specific requirements and I will be able to tell you if we can meet your requirements. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "vssumesh" <vssumesh_asic@yahoo.com> wrote in message news:1140266367.260187.89910@o13g2000cwo.googlegroups.com... > HI, > I just want to know is there any Virtex 4 based development board > on which i can add a 400 pin microprocessor and a SD RAM. I am not > worried about the board development but not found any board which has > that much free connections to the Virtex 4 chip. Please advice. > Thanks Sumesh V S >
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